JP3483296B2 - Information processing equipment - Google Patents

Description

Detailed Description of the Invention

(Table of contents) Industrial applications Conventional technology Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Action (Fig. 1) Example (FIGS. 2 to 5) The invention's effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device having a hierarchical storage system (hierarchical arrangement of buffer storage devices) between a processing device and a storage device for the purpose of speeding up data access. In particular, the present invention relates to an information processing device in which error handling in each buffer storage device is improved.

[0003]

2. Description of the Related Art In recent years, a processing speed of an information processing apparatus including a plurality of processing devices (hereinafter, sometimes referred to as CPUs) and a storage device shared by these CPUs (hereinafter, sometimes referred to as main memory device) In order to improve performance, a storage system may be configured in a hierarchical manner, that is, a buffer storage device (hereinafter, also referred to as cache or cache memory) may be provided in a hierarchical manner between each processing device and the main storage device. Has been done.

Although the use of the cache memory for shortening the access time to the main memory device is sufficiently effective as described above, an error occurs in each cache memory as in the main memory device. Has occurred, and various methods have been adopted to recover the error. Store
C if a through cache is used
When the content of the data is rewritten by the PU, the changed content is written not only in the cache but also in the main storage device. Therefore, if a cache error occurs, the cache data is discarded and the data in the main storage device is discarded. The cache error can be immediately recovered by referring to / reading the corresponding data of.

However, with the increase in the number of CPUs (arithmetic processing units) connected to the main storage device, the increase in the number of accesses to the main storage device has been a cause of system speed reduction. The store-in method (a method of writing the changed contents of data by the CPU only in the cache and writing it in the main storage device as needed) has been changed.

However, this store-in system is not without problems, and the first problem is that when a data error occurs in the cache, its contents are
Since it is not stored in the main storage device, it cannot be recovered from the main storage device and is lost. Since this is the same in the main storage device, reliability can be maintained by performing the same processing as in the main storage device.

As a second problem, the cache holds information indicating which address on the main storage device the data called a tag corresponds to each data. If the address information in is corrupted, the data stored in the cache is unknown, meaning that the data is lost. Therefore, in the store-in method, it is necessary to take thorough countermeasures against errors in tags.

Therefore, the following techniques have been conventionally adopted to increase the reliability of the tag. An ECC (Error Check and Correction) code is added to the tag. Redundant tags. The tag error of the upper layer is used to recover the tag error by using the copy of the tag in the upper layer, which is prepared so that the inquiry from the lower layer can be dealt with promptly. Is shown, and lower means that it is closer to the main storage side).

In addition to these, various proposals have been made regarding detailed techniques for executing the above-mentioned method.
Each of these proposals is essentially a technique shown as the above-mentioned three methods.

[0010]

However, adding the ECC to the tag as described above as a measure against the error of the tag leads to extension of the processing time and impedes the purpose of improving the processing speed by the cache. become.
In addition, as a measure against a tag error, the duplication as in the above item causes an increase in memory resources and an increase in cost.

In the method of the above item, since the tag copy is also used for data processing in the cache, it is necessary to deal with the tag copy error. Furthermore, measures against data errors are also necessary, but since it is performed in a separate procedure that is different from the case of tag errors, the error processing method becomes complicated and it is also costly. ing.

The present invention was devised in view of the above problems, and performs error recovery processing in the shortest time according to the error situation while suppressing wasteful increase of memory resources, and an error processing procedure. It is an object of the present invention to provide an information processing apparatus that is simplified and easily manages data and has improved reliability.

[0013]

FIG. 1 is a block diagram of the principle of the present invention. In FIG. 1, 1 is a storage device (main storage device) for storing data, and 2 is based on the data of the storage device 1. At least one processing unit (CP
U) and 3 are buffer storage devices (caches, cache memories) hierarchically provided between the processing device 2 and the storage device 1. From these storage device 1, processing device 2 and buffer storage device 3 of the present invention, An information processing device is configured.

In each buffer storage device 3, a data section 4 for holding a part (DATA) of the data in the storage apparatus 1, and tag information (TAG) including the address and status of the data held in the data section 4 are stored. Tag part 5 for holding
And a tag copying unit 6 that holds a copy (TAG copy) of the tag information of the buffer storage device 3 on the upper layer side of the own buffer storage device 3, and the data holding state of each buffer storage device 3 is stored. It is designed to be controlled in-system.

In the present invention, each buffer storage device 3 has an error detecting means 7, a first notifying means 8, a searching means 9, a second notifying means 10, a process executing means 11 and a third notifying means. Twelve are provided. Here, the error detection means 7 is in the self buffer storage device 3 (data section 4,
The first notifying unit 8 detects an error in the tag unit 5 and the tag copying unit 6), and when the error detecting unit 7 detects an error, the entry address of the error occurrence portion and the error detection are performed. The fact and the other layers [lower layer when an error is detected in the data section 4 and the tag section 5 (storage device 1 side); upper layer when an error is detected in the tag copying section 6 (processing apparatus 2)
Side)] to the buffer storage device 3.

Further, the search means 9 is a self-buffer storage device.
The on from the buffer memory 3 of the upper layer side of the location 3
Tag part 5 or data in the buffer storage device on the upper hierarchy side
When the error detection fact of the section 4 is notified, the tag copying section 6 is searched with the notified entry address, and the address and status of the data indicated by the entry address is retrieved. The second notifying means Reference numeral 10 denotes a buffer storage device of the layer in which the error notification is issued, together with the address of the data retrieved by the retrieval means 9, based on the status retrieved by the retrieval means 9, an invalidation request or a moveout request for the error occurrence portion. Three
To notify.

Further, when the invalidation request or the moveout request is notified from the buffer storage device 3 of the other layer, the processing execution means 11 executes the invalidation processing or the moveout processing for the corresponding data. ,
When the invalidation request or the move-out request is notified from the buffer storage device 3 of the other layer, the third notifying unit 12 stores the corresponding data in the buffer storage device 3 on the upper layer side of the own buffer storage device 3. Whether it exists in
It is checked by referring to the tag copying unit 6, and if it exists, the invalidation request or the moveout request is notified to the buffer storage device 3 on the upper layer side. When the error in the tag part 5 or the data unit 4 in its own buffer storage device 3 is detected to be generated by the error detection means 7, first notification means 8, the tag part 5 or the data that caused the error Part 4 entry
Address, which notifies the buffer storage device 3 in the lower hierarchy side of the own buffer memory 3, the buffer storage device 3 of the lower layer side, the search unit 9, the tag copying with the notified entry address searching for parts 6 are those to leave <br/> takes the address of the data indicated by the entry address, second notification means 10 shall notify the retrieved address in the self buffer memory 3 so
There, the self buffer store 3 before Symbol buffer memory 3 of the upper layer side than the lower layer side by referring to the own buffer store tag copying unit 6 by notified address from the buffer memory 3 of 3 It is checked whether the latest data exists, and if the latest data does not exist and the data in the own buffer storage device 3 is not the latest data, the data is invalidated, and the latest data does not exist. the data as long as the data in its own buffer memory 3 is current invalidates the data block of the lower layer side of the own buffer storage device generated the error from the move-out to the buffer memory 3 3 , if the latest data exists in the upper layer side of the buffer storage device 3 notifies the front Symbol address in buffer memory 3 of the upper layer side And than, the self buffer store
3 and the buffer memory 3 of the upper layer side, leaving the latest data in the lower layer side of the buffer memory 3,
And, in which invalidates all data blocks with the same address as the latest data in the own buffer storage device 3 and the upper layer side of the buffer memory 3
There is . Further, when it is detected that an error has occurred by the error detection means 7 to the tag copying unit 6 in its own buffer memory 3, first notification means 8 entry address of the tag copying unit 6 that caused the error To the buffer storage device 3 on the upper layer side than the self buffer storage device 3
And the buffer storage device 3 on the upper layer side.
Retrieves the address of the data indicated by the entry address by searching the tag part 5 in notification entries address, Installing the issued address by referring to the tag copying unit 6 of the upper layer side It is checked whether or not the latest data exists in the buffer storage device 3 on the higher hierarchy side than the buffer storage device 3, and the latest data does not exist, and the data in the buffer storage device 3 on the higher hierarchy side is the latest data. If not, the data is invalidated, and if the latest data does not exist and the data in the buffer storage device 3 on the upper hierarchy side is the latest, the data is moved out to the own buffer storage device 3. the data block of the upper layer side of the buffer memory 3 to disable from further upper floors than the buffer memory 3 of the upper layer side If the latest data exists on the side of the buffer memory 3, which notifies the previous SL address in buffer memory 3 further upper layer side of the buffer storage device 3 of the upper layer side, the upper layer Side bar
Ffa storage device 3 and the upper layer side of the buffer memory 3 buffer memory device further upper layer side than 3
Leaves the latest data on the self buffer memory 3, and the latest in the upper layer side of the buffer memory 3 and the buffer memory 3 further upper layer side of the buffer storage device 3 of the upper layer side one that invalidates all the data blocks with the same address as the data
There is .

[0018]

In the information processing apparatus of the present invention described above, when the error detecting means 7 detects an error in the data section 4 or the tag section 5 of the own buffer storage device 3, the first notifying means 8 is provided.
By this, the entry address of the error occurrence portion and the fact of error detection are notified to the buffer storage device 3 on the lower hierarchy side, while the error detection means 7 detects an error in the tag copying section 6 of the own buffer storage device 3. When done, first
By the notification means 8 of
The address and the fact of error detection are notified to the buffer storage device 3 on the upper layer side.

Then, in the buffer storage device 3 notified of the fact of error detection from the buffer storage device 3 of the other layer,
After the search means 9 searches the tag copying unit 6 with the notified entry address and the address and status of the data indicated by the entry address is retrieved, the second notification means 10 causes the search means 9 to perform the search. Based on the retrieved status, an invalidation request or a move-out request for the error occurrence part is notified to the buffer storage device 3 of the layer having the error notification, together with the address of the data retrieved by the retrieval means 9.

In the buffer storage device 3 notified of the invalidation request or the move-out request from the buffer storage device 3 of the other layer, the process execution means 11 performs the invalidation process or the move-out process on the corresponding data. In addition to the above, the third notifying unit 12 checks whether or not the corresponding data exists in the buffer storage device 3 on the higher hierarchy side than the own buffer storage device 3 by referring to the tag copying unit 6. If it exists, the invalidation request or the moveout request is further notified to the buffer storage device 3 on the upper layer side.

In this way, the data (block) in which the error of the data section 4, the error of the tag section 5, and the error of the tag copying section 6 in the buffer storage device 3 of each layer all correspond to the error occurrence portion by the same method. Will be restored by excluding the item from each layer.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. The memory system (storage system) of the information processing apparatus described here comprises a store-in type cache (buffer storage device) in a hierarchical manner. A data block existing in the cache (hereinafter, sometimes simply referred to as a block) always exists in the cache of the lower hierarchy [storage device (main storage device) side].

The nth-order cache and the nth-mth order (m = 1, 2,
, N-1), no error occurs at the same time, and no error occurs at the same time for the data and its address in the cache of the same layer. In other words, the faults to be excluded as those that do not occur here are when an error occurs simultaneously in data or addresses that point to the same block in different layers, and when errors occur simultaneously in corresponding data and addresses in the same cache in the same layer. When occurs. These assumptions are when two blocks that are physically unrelated, but distant, and logically related, suddenly fail at the same time, so the frequency of errors and the probability of this happening. It is reasonable from the point of view.

Data transfer is performed only between adjacent layers. This is a method for reducing the number of pins of the chip and also a method for simplifying the processing. Now, first, an outline of cache error processing performed by the information processing apparatus of the present invention will be described.

First, considering the error of the tag part and the error of the data part separately, it is considered that the tag part and the tag copying part are duplicated by copying each other.
When an error occurs, the correct tag information (address, status) can be obtained by referring to the pair of unbroken tag parts (or tag copying parts).

Next, when an error occurs in the data section ,
According to the store-in method, the correct value is obtained by referring to the data block of the address that should exist in the cache memory of the lower layer, or if the data block is in the cache memory of the upper layer, it is shared ( Other CPU
Or even the state can use this data block) is thus subjected to error processing in passing to invalidate.

Therefore, these three steps are simplified so that when an error occurs in the tag part or the data part , the cache memory in the lower layer is referred to, and when an error occurs in the tag copying part, the upper layer Will refer to the cache memory of. And the data that caused the error
If the block rewrites the correct data to it and still has a hard error (that part of the LSI is damaged and there is no possibility of recovery, or it will cause frequent failures) Since error processing can be wasted, the data block in which the error occurred is eliminated from the data section, the tag section, and the tag copy section which forms a pair with it.

By processing the error in the tag part and the error in the data part by the same procedure, the error in the tag part and the error in the data part can be treated as the same without discriminating them. The same procedure means that a processing procedure is adopted in which both errors are recovered without determining whether the error is in the tag part or the error in the data part.

Next, the cache error processing of this embodiment will be generally described with reference to FIG. In FIG. 2, m
In the case of providing a cache memory of a hierarchy, among the cache memories of these m hierarchies, the (n-1) th cache memory 20- (n-1), the nth cache memory 20-n and the (n + 1) th cache memory The three cache memories 20- (n + 1) are shown.

Each cache memory 20- (n-1)-
20- (n + 1) contains a part of the data in the storage device 1 (D
ATA) holding data part 21 and this data part 21
A tag unit 22 that holds tag information (TAG) that includes the address and status of the data that is held in the tag storage unit, and a copy of the tag information in the buffer storage device 3 one layer higher than the self buffer storage device 3 (TAG copy). And a tag copying section 23 for holding the tag.

It should be noted that the (n-1) th level cache memory 20
-(N-1) is on the upper layer (CPU) side of the nth cache memory 20-n, and the (n + 1) th cache memory 20- (n + 1) is higher than the nth cache memory 20-n. It is on the lower layer (main memory) side. Further, in each of the m-level cache memories, the error detecting means 7, the first notifying means 8, the searching means 9, the second notifying means 10, the processing executing means 11 and the third means described above with reference to FIG.
The function as the notification means 12 is provided.

At this time, the nth cache memory 20
-N indicates that an error has occurred in the tag unit 22 or the data unit 21, and the tag copying unit 2
The case where an error occurs in 3 will be described separately. When it is detected that an error has occurred in the tag portion 22 or the data portion 21 (function as the error detecting means 7 shown in FIG. 1)
The entry of the tag unit 22 (entry address), that is, the number of the block of the tag unit 22 or the data unit 21 in which the error has occurred in the n-th cache memory 20-n is indicated by the (n + 1) th cache cache. Memory 20- (n
+1) (function as the first notifying means 8 shown in FIG. 1).

N + 1st level cache memory 20- (n
+1), the n + 1th level cache memory 20- (n
The absolute address is searched and generated from the (+1) tag copying unit 23 (function as the searching means 9 shown in FIG. 1), and this is used as the nth
The next cache memory 20-n is notified (function as the second notifying means 10 shown in FIG. 1). In the nth-level cache memory 20-n , the tag copying unit 23 in the memory 20-n is referred to in the nth-level cache by its absolute address, and the cache memory 20- (n-
Check whether there is a possibility that the latest data exists in 1). If it does not exist and the data in the nth cache memory 20-n is not the latest, it is invalidated. If it does not exist and the data in the nth cache memory 20-n is the latest, the nth +
After sending data to the primary cache memory 20- (n + 1) (after move-out processing), the nth error occurred
The block of the next cache memory 20-n is invalidated. Upper layer cache memory 20- (n-1)
If the latest data exists in the cache memory, the entry of the tag copying unit 23 is sent to the (n-1) th cache memory 20- (n-1) to request the same processing (the second cache memory shown in FIG. 1). Function as the notification means 10 and the processing execution means 11).

If necessary, the process proceeds to the (n−2) th cache, the (n−3) th cache, ... And repeats until the latest data is finally sent to the (n + 1) th cache memory 20- (n + 1). (Third notification means 1 shown in FIG. 1
Function as 2.) In the state where the processing is completed, the latest data remains in the (n + 1) th level cache memory 20- (n + 1), and all the blocks having the same absolute address in the cache memory on the upper hierarchy side are invalid. This is a system created considering the device configuration with multiple CPUs, so that access from other CPUs can be dealt with swiftly, and data management is centralized at the lowest level to simplify processing and improve reliability. It depends on the policy adopted to make it easier to improve.

On the other hand, when it is detected that an error has occurred in the tag copying unit 23 (function as an error detection unit 7 shown in FIG. 1) is the entry address of the tag copying unit 2 cubic first n-1 It is sent to the cache memory 20- (n-1) (function as the first notifying means 8 shown in FIG. 1). Nth
In the -1st level cache memory 20- (n-1), this is returned to the absolute address and the (n-1) th level cache memory
The tag copying unit 23 at 20- (n-1) is referred to check whether or not there is the latest data in the cache memory on the upper layer side, and the same as in the case of an error in the tag unit 22 or the data unit 21. And proceed with processing, and finally the latest data is the nth
All blocks existing in the next cache memory 20-n and having the same absolute address on the upper hierarchy side are invalid.

A more specific example will be described with reference to FIGS. Here, FIG. 3 is a block diagram showing an information processing apparatus as one embodiment of the present invention, FIG. 4 is a block diagram showing a main part of a storage system of this embodiment, and FIG. 5 is a function of the SLB of this embodiment. 3 is a block diagram for explaining the above, and here, as shown in FIGS. 3 and 4, an information processing apparatus (computer system) having a memory structure of three layers will be described.

[0037] That is, FIG. 3, 4, 31 is a storage device [hereinafter for storing data, MSU (Main St o rage U
nit; main memory)), 32A, 32
B is a processing unit (CPU) that operates based on the data of the MSU 31. These MSU31 and CPU32A
Between the first buffer storage device [hereinafter, FLB
(First Level Buffer st o rage) is sometimes referred to] 3
3A, secondary buffer storage device [hereinafter, SLB (Second
Level Buffer st o rage) is sometimes referred] 34A and the main storage controller [hereinafter, MCU (Main st o rage Con
control unit)] and the FLB is provided between the MSU 31 and the CPU 32B.
33B, SLB34B and MCU35 are provided,
These memory hierarchical structure, MSU31, CPU32
The information processing apparatus (computer system) of this embodiment is configured by A and 32B.

Here, the MCU 35 has two CPUs 32.
It is commonly used in a two-system memory hierarchical structure for A and 32B, and performs data read (load) from MSU31 and data write (store) to MSU31, and FLB33A, 33B, SLB34A, 3
The data holding state in 4B is controlled by the store-in method.

Further, as shown in FIG. 4, FLB33A
In (33B), a part of the data of MSU 31 (DAT
A) holding the data section 36 and a part of the absolute address of the FLB data held in the data section 36 (FLB-
TAG) and a tag unit 37 that holds tag information including a status described later. SLB34A
In (34B), a part of the data of MSU31 (DAT
A) which holds A), and a part of the absolute address of the SLB data (SLB-
The tag unit 39 holds tag information including TAG) and a status described later, and the tag copy unit 40 holds a copy of the tag information (FLB-TAGC) in the tag unit 37 of the FLB 33A (33B).

Furthermore, a copy of the tag information in the tag section 39 of the SLB 34A (SLB-TAG) is displayed on the MCU 35.
A tag copying section 41A for the CPU 32A holding C) is provided, and the same as the tag copying section 41A,
A tag copying section 41B for the CPU 32B is also provided. Although not shown in FIG. 4, the MCU 35 and the CPU
32B, FLB33A, SL shown in FIG.
FLB33B and SLB34B having the same structure as B34A are provided.

Also in this embodiment, each FLB 33A,
33B, SLB34A, 34B and MCU35,
The error detecting means, the first notifying means described above with reference to FIG.
All or part of the functions of the searching means, the second notifying means, the processing executing means, and the third notifying means are provided. For example, the SLBs 34A and 34B have all of these functions as shown in FIG.

That is, in FIG. 5, reference numeral 42 is the own SLB3.
4A (34B) data section 38, tag section 39, and error detecting means for detecting an error in tag copying section 40, and 43, when the error detecting means 42 detects an error, the entry address of the error occurrence part It is a first notifying means for notifying the FLB 33A (33B) or the MCU 35 of the fact of error detection.

Further, reference numeral 44 searches the tag copying section 39 with the entry address notified when the error detection fact is notified from the FLB 33A (33B) or the MCU 35, and retrieves the address and status of the data indicated by the entry address. Search means for taking out, 45 means for searching 4
It is a second notifying means for notifying the FLB 33A (33B) of the invalidation request or the moveout request for the error occurrence part together with the address of the data fetched by the searching means 44 based on the status fetched by 4.

Further, 46 is processing execution means for executing invalidation processing or moveout processing for the corresponding data when the invalidation request or moveout request is notified from the MCU 35, and 47 is an invalidation request or moveout from the MCU 35. When the request is notified, it is checked by referring to the tag copying unit 40 whether or not the corresponding data exists in the buffer storage device on the upper layer side of the own SLB 34A (34B), that is, the FLB 33A (33B), and exists. In the case, the FLB 33A (33B) is further notified of an invalidation request or a moveout request.
Is the notification means.

The operation of the information processing apparatus of the present embodiment configured to have the above-mentioned functions will be described below. First, terms used in the following description will be described. The statuses held in the tag units 37 and 39 as the above-mentioned tag information include CHG, SH, EX, and I.
There is NV. CHG (change) is a state where the data has been changed and the changed contents have not been sent to the lower layer, SH
(Share) is a state where another CPU may have the same block, and EX (exclusive) is another C
State that PU does not have the same block (CHG including), INV (inval i d, disabled) shows the state data is unavailable. These statuses are used as tag information, if necessary, in TAG and TA of the tag parts 37 and 39.
Written to GC.

In the following description, ABS (absolute) is the absolute data address and the entry address is TAG.
In the serial number given to each data block in [TAG contents] + [entry address] = [A
BS]. The command between different layers is command + ABS
This is done as + etc., But since the contents of the TAG are ignored if necessary, the entry address or ABS is actually sent.

Further, in the following description, a block is a unit of data, and data is transferred in block units (for example, 8 bytes × 8) instead of byte units. Now, in the computer configuration used in this embodiment, data management is performed as follows. The existence status of a block in the cache is as follows.
Limit to 3 cases.

When the status of the SLB 34A (34B) is INV, the status of the FLB 33A (33B) is INV. If the status of SLB34A (34B) is SH,
The status of FLB33A (33B) is SH. The status of SLB34A (34B) is EX / CHG
In case of, the status of FLB33A (33B) is IN
Any of V, SH, EX, CHG.

The reason for limiting in this way is that the lower layer accurately knows the state of the upper layer. In the case of the present embodiment, it is not necessary to distinguish between the TAG error and the data error, and therefore the error occurrence is 1. 1. The tag section 37 or the data section 36 of the FLB 33A (33B). Tag copy unit 40 of SLB 34A (34B) 3. 3. Tag portion 39 or data portion 38 of SLB 34A (34B) 4. There are four types of the tag copy unit 41A (41B) of the MCU 35, which will be described below in order. In the following description, CPU 32A, FLB 33A, SLB 34A,
The operation of the memory hierarchical structure on the tag copying section 41A side will be described. The CPU 32B, FLB 33B, SLB 34
It goes without saying that the operation of the memory hierarchical structure on the side of the tag copying unit 41B is also performed in exactly the same manner.

When an error occurs in the tag section 37 or the data section 36 of the 1.1 FLB 33A (33B) First, the entry address of the tag section 37 is set to the SLB 34A.
And notify that an error has been detected (error detection fact). In the 1.2 SLB 34A, the tag copying unit 40 (FLB-TAGC) is based on the notified entry address.
To retrieve the ABS and status.

If the status of the tag copy unit 40 (FLB-TAGC) is EX, the entry address of the block is sent to the FLB 33A and this block is sent to the SLB 34A, and the tag unit 37 (FLB of the FLB 33A is sent.
Send a request (moveout request, invalidation request) to change the status of (TAG) to INV. FLB33A notifies that this block is sent to SLB34A,
When the data bus becomes available, block SLB34
Send to A, and tag section 37 (FLB-TA of FLB33A).
After setting the status of G) to INV, set the status of the tag copying unit 40 (FLB-TAGC) of the SLB 34A to IN.
Request V.

Further, the tag copying section 40 (FLB-TAG
If the status of C) is SH or INV, SLB
The status of the tag copying unit 40 (FLB-TAGC) of 34A is set to INV, and the second notifying unit 45 causes the FL to be FL.
Send the entry address to B33A and also FLB
A request is made to set the status of the tag section 37 (FLB-TAG) of 33A to INV. (Above, operation according to 1.2) Tag copying unit 40 (FLB) of SLB 34A (34B)
-TAGC) when an error occurs First, the entry address of the tag copying unit 40 (FLB-TAGC) is sent to the FLB 33A, and the fact that an error has been detected is notified.

In the FLB 33A, the notified entry
Based on the address, the tag section 37 (FLB-TAG) is searched to retrieve the ABS and status. Tag part 3
If the status of 7 (FLB-TAG) is EX, S
Sends ABS to LB34A and notifies that the block will be sent. When the data bus becomes available, the block is sent to SLB34A and the status of the tag section 37 (FLB-TAG) of FLB33A is set to INV. Tag copy unit 40 (FLB-T of SLB34A)
Request that the status of AGC) be INV.

If the status of the tag unit 37 (FLB-TAG) is SH or INV, the ABS of the block is sent to the SLB 34A and the status of the tag copying unit 40 (FLB-TAG) is set to INV. Request and notify that no data in this block will be sent. At the same time, the tag portion 37 (F
LB-TAG) status to INV.

3. Tag part 39 of SLB34A (34B)
Alternatively, when an error occurs in the data section 38, first, the entry address of the tag section 39 is sent to the MCU 35 and the fact that an error has been detected is notified. M
The CU 35 searches the tag copy unit 41A (SLB-TAGC) on the basis of the notified entry address to extract the ABS and the status.

If the status of the tag copying section 41A (SLB-TAGC) is EX, the ABS of the block is sent to the SLB 34A and the data of this block is transferred to M.
Request to send to CU35. When receiving this request, S
The LB 34A performs the above-mentioned operation according to items 1 and 2. However, when the tag copying unit 40 (FLB-TAGC) is searched and it is found that the FLB 33A does not have this block, the operation according to the above items 1 and 2 is immediately stopped and the next operation is performed.

Thereafter, the ABS is sent and the block is sent, and when the data bus becomes available, the block is sent to the MCU 35, the status of the tag section 39 (SLB-TAG) of the SLB 34A is set to INV,
Tag copy unit 41A (SLB-TAG) for MCU 35
Request the status of C) to be INV. If the status of the tag copy unit 41A (SLB-TAGC) is EX, the ABS of the block is sent to the SLB 34A and the tag unit 39 (SLB-TAG) of the SLB 34A is sent.
Request to set the status of INV to INV.

Upon receipt of this request, the SLB 34A retrieves the tag copy unit 40 (FLB-TAGC) and FLB 33A.
If you have this block, the tag part 3 of FLB33A
7 (FLB-TAG) status is requested to be INV, and the status of the tag copying unit 40 (FLB-TAGC) is set to INB. If the FLB 33A does not have this block, it requests serialization. Here, the serialization is an instruction for adjusting the writing / reading order of information with another CPU (32B), and the serialization reverses the writing order and loses the latest correct data. In addition to preventing the above, it prevents accidental reading of new data more than necessary.

After that, the tag section 39 (SL
B-TAG) status to INV and M
The CU 35 is notified that the error processing has been completed. By this notification, the tag copy unit 41A (SLB-
The status of (TAGC) becomes INV, and the error processing ends. 4. When an error occurs in the tag copy unit 41A (41B) of the MCU 35 In this case as well, first, the tag copy unit 41A (SLB-TAG).
The entry address of C) is sent to the SLB 34A and the error is notified.

In the SLB 34A, the notified entry
The tag portion 39 (SLB-TAG) is searched by the address to retrieve the ABS and status. And that A
The tag copying unit 40 (FLB-TAGC) is searched based on the BS, and the following status combinations of SLB-TAG and FLB-TAGC are obtained. [A] When SLB-TAG is INV (it is not necessary to search FLB-TAGC at this time).

[B-a] SLB-TAG is SH and FLB
-When the TAG does not have this block. [B-b] SLB-TAG is SH and FLB-TAG is S
When you have this block in H. [C-a] SLB-TAG is EX but FLB-TAG does not have this block because it is not CHG.

[Cb] When SLB-TAG is EX but FLB-TAG is SH but not CHG and has this block. [C-c] SLB-TAG is EX but not CHG but FLB-TAG is EX and has this block instead of CHG. [C-d] SLB-TAG is EX but not CHG, but FLB-TAG is CHG and has this block.

[D-a] SLB-TAG is CHG and FL
When B-TAG does not have this block. [D-b] When SLB-TAG is CHG and FLB-TAG is SH and has this block. [D-c] SLB-TAG is CHG and FLB-TAG is EX or CHG and does not have this block.

In the case of the above cases, the following processing is performed in this embodiment. [A] SLB-TAG is set to INV, ABS is sent to the MCU 35, and SLB-TAGC is set to INB.
Ask you to. The same processing as [Ba] and [A] is performed.

[Bb] Sends the entry address to the FLB 33A and requests the FLB-TAG to be set to INV, and sets FLB-TAGC to INV. MC
The U35 is notified that it will not move out while sending ABS, and will request SLB-TAG to be INV and SLB-TAGC to be INV.

[C-a] Sends ABS to the MCU 35 and notifies the MCU 35 that the move-out will not be performed, and SLB-
Set TAG to INV and SLB-TAGC to IN
Request V. The same processing as [Cb] and [Bb] is performed. [C-c] FLB-TAGC entry address is F
Send this block to LB33A and SLB34
Send to A and send a request to bring FLB-TAG to INV.

In FLB33A, this block is SLB
34A, send the block to the SLB 34A when the data bus is available, FLB-TAG
To INV and request FLB-TAGC to INV. After executing this, the MCU 35 is notified of sending ABS and not sending the data of this block, and requests SLB-TAG to be INV and SLB-TAGC to be INV.

[C-d] FLB-TAGC entry
The address is sent to FLB 33A, this block is sent to SLB 34A, and a request is sent to set FLB-TAG to INV. In FLB33A, this block is S
Notify to send to LB34A and send block to SLB34A when data bus becomes available, FLB-T
Set AG to INV and set FLB-TAGC to IN
Request V.

After executing this, A is sent to the MCU 35.
While sending BS and SLB-TAG status,
Notify that the data of this block will be sent, and when the data bus becomes available, send the block to MCU 35, and
LB-TAG is set to INV and SLB-TAG
Request C to be INV. At this time, the data is not written in the SLB 34A, but the data is saved in some buffer and this processing is performed.

[Da] ABS and S for MCU 35
The LB-TAG status is sent, and the data of this block is notified to be sent. When the data bus becomes available, the block is sent to the MCU 35, and the SLB-T is sent.
Set AG to INV and SLB-TAGC to IN
Request V. [D-b] Sends the entry address to FLB 34A, requests FLB-TAG to be INV, and sets FLB-TAGC to INV.

ABS and SLB-T for the MCU 35
In addition to sending the status of AG, it notifies that the data of this block will be sent. When the data bus becomes available, the block is sent to MCU 35 and SLB-TAG is set to I.
Request to SLV-TAGC to INV as well as to NV. The same processing as [D-c] and [C-d] is performed.

As described above, according to this embodiment, a copy of tag information originally used for another purpose (TAGC).
FLB33A, 33B, SL by utilizing
The error handling in the B34A, 34B, and MCU 35 is improved, and the error recovery process can be performed in the shortest time according to the error situation while suppressing the wasteful increase of the memory resource. Therefore, the error handling procedure is simplified. As a result, it becomes easier to manage data, and the reliability of the information processing device (computer system) is greatly improved.

In the above embodiment, the case where two CPUs are provided and the memory structure of three layers is provided between each CPU and the MSU has been described, but the present invention is not limited to this. However, it is needless to say that the present invention can be similarly applied to a case where three or more CPUs are provided or a case where a memory structure having two or four or more hierarchies is provided, and the same effect as the above-described embodiment can be obtained.

[0074]

As described above in detail, according to the information processing apparatus of the present invention (claims 1 and 2), while utilizing the copy of the tag information originally used for another purpose, Errors in the tag unit, the data unit, and the tag copying unit of the buffer storage device can be recovered by removing the data corresponding to the error-occurring part from each layer by the same method. While suppressing, error recovery processing can be performed in the shortest time according to the error situation, error processing procedure can be simplified, data management can be easily performed, and reliability as an information processing device can be significantly improved. .

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing a main part of a storage system in order to explain a general operation of the present invention.

FIG. 3 is a block diagram showing an information processing apparatus as an embodiment of the present invention.

FIG. 4 is a block diagram showing a main part of a storage system of this embodiment.

FIG. 5 is a block diagram for explaining the function of the SLB of this embodiment.

[Explanation of symbols]

1 Storage Device (Main Storage Device) 2 Processing Device (CPU) 3 Buffer Storage Device (Cache, Cache Memory) 4 Data Unit 5 Tag Unit 6 Tag Copying Unit 7 Error Detection Means 8 First Notification Means 9 Search Means 10 Second Notifying means 11 Process executing means 12 Third notifying means 20- (n-1) n-1st level cache memory (buffer storage device) 20-n nth level cache memory (buffer storage device) 20- ( n + 1) n + 1st-order cache memory (buffer storage device) 21 data unit 22 tag unit 23 tag copying unit 31 MSU (main storage device, storage device) 32A, 32B CPU (processing device) 33A, 33B FLB (primary buffer) Storage device) 34A, 34B SLB (secondary buffer storage device) 35 MCU (main storage control device) 36 data unit 37 tag unit 8 data unit 39 tag portion 40,41A, 41B tag copying unit 42 error detection unit 43 first notification unit 44 retrieving means 45 second notification unit 46 processing execution unit 47 the third notification means

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masayuki Okada 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) Reference JP-A-5-265859 (JP, A) JP-A-53-125735 (JP, A) JP 57-113493 (JP, A) JP 58-6597 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 12 / 08-12 / 12

Claims (2)

(57) [Claims] 1. A storage device and at least one processing device that operates based on data in the storage device, and a buffer storage device is hierarchically provided between each processing device and the storage device. The buffer storage device has a data part that holds a part of the data of the storage device, a tag part that holds tag information including the address and status of the data held in the data part, and a higher-order buffer than the own buffer storage device. And a tag copying unit that holds a copy of the tag information of the buffer storage device on the hierarchical level, and stores the data holding state of each of the buffer storage devices described above.
In the information processing apparatus controlled by the IN system, each buffer storage device has an error detection means for detecting an error in its own buffer storage device and an entry of an error occurrence part when the error detection means detects an error. First notification means for notifying the address and the error detection fact to the buffer storage device of the other layer, and the tag unit in the buffer storage device of the upper hierarchy side from the buffer storage device of the higher hierarchy side than the own buffer storage device Well
Or the fact that an error detection fact of the data section is notified, the tag copying section is searched by the entry address and the address and status of the data indicated by the entry address are retrieved by the retrieval section. Based on the status
Second notifying means for notifying the buffer storage device of the layer having the error notification of the invalidation request or the moveout request for the error occurrence part together with the address of the data retrieved by the searching means, when you are notified of the invalidation request or move-out request from the buffer store, which equipped with a processing execution unit for executing invalidation processing or move-out processing for the corresponding data, the own buffer storage by said error detection means When it is detected that an error has occurred in the tag part or the data part in the device, the first notifying means sets the entry address of the tag part or the data part in which the error has occurred in its own buffer storage device. It is intended to notify the buffer storage device in the lower hierarchy side of, of the lower layer side buffer Stories In the apparatus, the search means searches the tag copying unit at the notified entry address are those responsible to extract the address of the data indicated by the entry address, the notification means of the second is taken also address notifying the own buffer storage device
And than, the self buffer storage device, the latest data before Symbol buffer storage of the upper layer side than the reference to the own buffer store the tag copying unit by notified address from the lower layer side of the buffer store Check if it exists,
If the latest data does not exist and the data in the own buffer storage device is not the latest, invalidates the data, and if the latest data does not exist and the data in the own buffer storage device is the latest After moving out the data to the buffer storage device on the lower layer side, the data block of the own buffer storage device in which the error occurred is invalidated, and the latest data exists in the buffer storage device on the upper layer side. lever, der pre Symbol address shall notify the buffer memory of the upper layer side
Ri, the self buffer store and the upper layer side of the buffer storage device, leaving the latest data in the buffer storage device of the lower layer side, and, in the buffer storage device of the self buffer storage device and the upper layer side characterized in that said all data blocks with the same address as the latest data is to disable the information processing apparatus. If wherein errors to the tag copying unit in its own buffer storage by said error detection means detects that it has generated, the notification means of the first, an entry of the tag copying unit that caused the error - an address, and notifies the buffer storage device of the upper layer side than the self buffer store
Is intended, the upper layer side of the buffer memory device, retrieves the address of the data indicated by the entry address by searching the tag portion in notification entries address, said by Installing issued address tag By referring to the copy unit, it is checked whether or not the latest data exists in the buffer storage device on the higher hierarchy side than the buffer storage device on the higher hierarchy side,
If the latest data does not exist and the data in the buffer storage device on the upper layer side is not the latest, the data is invalidated, and the latest data does not exist and in the buffer storage device on the upper layer side. data to invalidate the data block of the latest value, if the move out and the upper layer side of the buffer storage device from the data to the own buffer storage device, further than the upper layer side of the buffer store if the latest data exists in the buffer storage device of the upper layer side, which informs the previous SL address in buffer memory device further upper layer side of the buffer storage device of the upper layer side, the upper layer side the buffer storage device and the buffer memory device of the upper layer side further than the upper layer side of the buffer memory, the latest data Data in the buffer storage device on the upper layer side and on the buffer storage device on the layer further higher than the buffer storage device on the upper layer side and having the same address as the latest data. What invalidates all blocks
And characterized in that, the information processing apparatus according to claim 1.