JPH045221B2 - - Google Patents

Description

[Detailed description of the invention] 〔table of contents〕 The present invention will be described in the order of the following items.

A Overview B Industrial application field C Conventional technology D Problem to be solved by the invention E Means for solving the problem (Figure 1) F Effect G Example (Figures 2 and 3) G ₁ Configuration description G ₂ Operation description H Effect A Overview In the store-through buffer storage error processing method using hardware, the error occurrence location is invalidated after an error occurs and becomes non-hit in another access. When the data moved in from the main memory is read out, it is determined whether the error is a hard (fixed) error or a soft (intermittent) error based on the presence or absence of an error, and error processing is performed.

B. Field of Industrial Application The present invention determines whether, when an error occurs in a buffer storage in which writing is performed using the store-through method, the error is a soft (intermittent) error or a hard (fixed) error. This invention relates to a buffer storage error processing method that determines and processes errors using simple hardware control.

Batsuhua Storage (hereinafter referred to as BS)
A high-speed, small-capacity storage device that is separate from main memory and stores some of the data on main memory. By accessing this BS, the CPU can shorten the time it takes to access the main memory and speed up the overall data processing.

There are two methods for writing data to the BS: the store-through method and the swap method. In the store-through method, data is written to blocks in both the main memory and the BS, and the contents of both blocks always match. In the swap method, only the BS is written and the main memory is not written.

The present invention relates to an error processing method for a store-through type BS, and the BS in the following description is assumed to be of a store-through type.

When an error occurs in the data retrieved from this BS, processing differs depending on whether the error is a BS hard error or a soft error. In the former case, it is a failure of the memory element that makes up the BS, so it is necessary, for example, to separate the block and prevent it from being used.In the latter case, it is a temporary destruction of data due to noise, alpha rays, etc. , BS hardware is normal. Therefore, when an error occurs in the BS, it is necessary to determine whether the error is a hard error or a soft error and then process it.

C. Prior Art When an error occurs in the BS, an error processing method using a CPU microprogram and an error processing method using hardware are used.

In the microprogram method, when the microprogram is notified of the occurrence of a BS error from the BS control unit, it retries the error location a certain number of times. If this retry fails, it is assumed to be due to a hard error.
Based on the error address notified from the BS control unit at the same time as the error occurs, the BS block unit and
It is common to disconnect in WAY units.

Although it is possible to handle such errors using hardware, since the control to retry at the location where the error occurred is complicated, simple hardware control can reduce BS errors to soft errors. It was difficult to determine whether there was a problem or a hard error.

For this reason, for BS error handling, conventionally
Error handling methods using CPU microprograms were often used.

D Problems to be solved by the invention The BS error processing method using a microprogram distinguishes between hard errors and soft errors.
It is easy to determine which type of error it is, but on the other hand, it requires a means for the BS control unit to notify the microprogram of the error address and a means for the microprogram to instruct the BS control unit to disconnect the faulty block. However, there was a problem in that the interface between the BS and the microprogram became complicated due to an increase in the amount of hardware and the complexity of control.

On the other hand, the hardware-based BS error processing method simplifies the interface between the BS and the microprogram, but as mentioned above, it does not make it easy to determine whether a BS error is caused by a soft error or a hard error. There was a problem that it could not be determined.

E. Means for solving the problems The means taken by the present invention to solve the above problems will be explained with reference to FIG. FIG. 1 is a block diagram showing the structure of the present invention.

In Figure 1, 110 is a buffer storage (BS) device, which, like conventional BS devices, has internal
BS array 111 and tag (TAG) that constitute BS
112 and other peripheral parts (not shown) necessary for writing to and reading from the BS. Data is stored in the BS array 111 in a certain storage unit. Also, in TAG112,
A control bit (V) is provided to indicate whether the data in the storage unit is valid or invalid. The storage unit is usually a block.

120 is an error detection circuit, and the BS array 111
Detects the presence or absence of errors in data read from.

130 is error control bit memory (ECBM)
It is provided separately from the BS array 111, and the data in each block of the BS array 111 is in a first state in which there is no error, a second state in which an error occurs, and a third state in which the storage unit is separated. An error control bit is provided corresponding to each storage unit.

140 is an error control circuit, and the BS array 111
When an error is detected in the storage unit data of
The error control bit of the storage unit in the ECBM 130 is changed from the first state (for example, “00”) to the second state.
The storage unit is updated to the state (for example, "01") and the storage unit is invalidated. Furthermore, the error control bit is
If an error is detected in the data read from the storage unit after the move-in by another access is completed after the state (01) is reached,
The corresponding error control bit in the ECBM 130 is updated from the second state (01) to the third state (for example, "11"), and the storage unit is invalidated and separated. If no error is detected in the read data after the move-in, the error control bit is returned from the second state (01) to the first state (00) in which there is no error.

Reference numeral 150 denotes a replacement determining means, which moves data in the main memory (MSU) to the invalidated storage unit when the storage unit invalidated by the error control circuit 140 is subsequently accessed and is not hit. Move In.

F Effect Initially, data is written from the MSU to each storage unit of the BS array 111 by a fetch request,
The address of each storage unit is written into the TAG 112, and the control bit V is set to valid "1". Further, the ECBM 130 is set to the first state (00) in which there is no error in data by the initialization operation.

Data read from the BS array 111 accessed by the read request address from the CPU to the BS is transferred to the CPU and is also applied to the error detection circuit 120.

When an error is detected in the data, the error detection circuit 120 notifies the error control circuit 140 of the occurrence of the error.

Upon receiving the error occurrence notification, the error control circuit 140 updates the error control bit in the storage unit of the ECBM 130 from the first state (00) to the second state (01) instructing the occurrence of an error, and Disable units, specifically:
The control bit V of the entry for the storage unit in the TAG 112 is invalidated to "0".

After that, other accesses to the invalidated storage unit or retries by the CPU microprogram did not hit the BS (non-hit).
In this case, the non-hit signal is the replacement determining means 15.
Sent to 0.

When the replacement determining means 150 receives this non-hit signal, it determines the replacement way (WAY), that is, the storage unit to be replaced. However, since the storage unit in which the error was detected earlier has been invalidated (the corresponding storage unit in the TAG 112 The control bit V of the entry is set to "0"), so that this storage unit is replaced.

After the replacement process is completed, the MSU data will be
In accordance with the instructions from the replacement determining means 150, the data is moved into this replaced storage unit. At this time, a new address is written to the TAG 112 and the control bit V is set to valid "1", but the error control bit of the ECBM 130 remains in the second state (01).

Thereafter, when another access reads this storage unit of data for the first time, the error detection circuit 120
detects the presence or absence of errors in this data.

If an error is detected again in the read data, the error control circuit 140 determines that it is a hard error in the BS since the error has been detected twice in a row with a move-in write from the same storage unit in between. Then, the error control bit corresponding to the storage unit in the ECBM 130 is updated from the second state (01) to the third state (11), and the storage unit is invalidated and separated. The separated storage unit will no longer be used for address comparison or replacement for hit detection.

If no error is detected in the read after the move-in, the error control circuit 140 regards the first error as a soft error (intermittent error) and sets the corresponding error control bit of the ECBM 130 to the second state (01). to the first state (00).

As described above, by simply adding the small-capacity ECBM 130 and the error control circuit 140 that requires a simple circuit configuration (the replacement determining means 150 is
(also used in BS processing method), can perform BS error processing. In addition, a dedicated write cycle is not provided to write data after an error occurs, and data is moved in from the MSU to the BS array 111 at the time of a BS non-hit. Processing control is simplified.

Intermittent errors that occur in the RAM that constitutes the BS array 111 can be recovered by writing normal data.
The present invention focuses on this property, and if no error is detected after data is written after an error occurs, it is regarded as an intermittent error and storage processing is not separated. This prevents unnecessary disconnection processing and simplifies BS error handling.

G. Embodiment An embodiment of the present invention will be described with reference to FIGS. 2 and 3. FIG. 2 is a block diagram illustrating the configuration of the present invention, and FIG. 3 is a diagram illustrating a TAG entry and an error control bit memory provided therein.

_G1 Configuration Description In FIG. 2, the error detection circuit 120,
The parts other than the ECBM 130, the error control circuit 140, and the replacement determining means 150 are the BS device 1.
It is 10.

In the BS device 110, the BS array 111 is
It has a 2WAY configuration 111A and 111B,
Data is written or read in storage units consisting of blocks, and is accessed by lower addresses among the addresses. TAG112 is also 2WAY
They are configured as 112A and 112B, and are accessed by lower-order addresses.
As shown in FIG. 3, the TAG entry corresponding to each block in the BS array 111 is provided with the upper address of the corresponding block and a control bit V indicating whether the block is valid or invalid, as will be explained later. Error control bits (EC ₀ , EC ₁ ) of the ECBM 130 are provided to ensure this. BS array 11
1 and TAG 112 constitute a BS.

113 is the address register (ADR), BS
The address to access is set. The address is sent to the MSU and the data at that address is read, and the lower address is the BS array 111,
TAG 112 and LRU memory (described below), and the upper address is applied to comparator 114.

There are two comparators 114 according to the TAG 112.
4A and 114B are provided, and the upper address of the ADR 113 is compared with each upper address in the 2WAY TAG entry.

115 is a gate, comparators 114A and 114
When a match between the upper addresses is not detected in both B and B, a non-hit signal is output and sent to the CPU and the replacement determining circuit 150.

116 is main memory data register (MSDR)
Then, the MSU data is set. 117 is buffer storage data register (BSDR)
Then, the data read from the BS array 111 is set. 118 is a BS array selector (BS/SEL) which receives the output of the comparator 114,
When TAG112A hits, BS array 111
Select the data of A, and when TAG112B hits, select the data of BS array 111B and write it to BSDR117. 119 is a control bit selector (V SEL), and a comparator 114A
When TAG112A hits after receiving the output of
Select control bit V of TAG112A,
When TAG112B is hit, the control bit V of TAG112B is selected and added to the replacement determination circuit 150.

The error detection circuit 120 detects the presence or absence of an error in the data read from the BS array 111 by a parity check.

ECBM130 is installed inside TAG112.
2WAY configuration 130A, 13 like TAG112
0B, and as shown in Figure 3, each TAG
Two error control bits EC ₀ and EC ₁ are provided in which error information of the data of the corresponding block of BS array 111 is set in the entry. Error control bits EC ₀ and EC ₁ are set to "00" in the first state where there is no error in the data, set to "01" in the second state where an error occurs, and set to "01" in the third state when the block is disconnected. In the current state, it is set to "11". 131 is an error control bit selector (ECB/SEL), and comparator 114
When TAG112A hits after receiving the output, select ECBM130A and select TAG112B.
When the signal is hit, the ECBM 130B is selected and sent to the error control circuit 140.

The error control circuit 140 is as described in FIG.

In the replacement determining means 150, 151 is
In LRU (Least Recently Used) table, BS
The past usage status of each block in array 111 is recorded. 152 is LRU register (LRUR)
Then, the block of the BS array 111 to be replaced taken out from the LRU table 151 is
iD (either WAY ₀ or WAY ₁ ) is written. 153 is a replacement decision circuit, and gate 11
When a non-hit signal is received from 5, a block to be replaced is determined by the known LRU method using the LRU table 151, but at this time, blocks that were invalidated due to data errors are replaced first. controlled by. In other words, LRU
TAG control bit V = ₀ than by the value from
Replace blocks with priority.

_G2 Operation Description First, data is written from the MSU to each block of the BS array 111 in response to a fetch request.
The upper address of each block is written into the TAG 112, and the control bit V is set to valid "1". Also, the error control bit EC ₀ of ECBM130
and EC ₁ are set to the first error-free state "00" by the initialization operation.

Read request address from CPU to BS is ADR
113, and the TAG is set to the lower address.
112, BS array 111 and LRU table 15
1 are accessed simultaneously. When a lower address is provided to TAG 112, the upper address within that TAG is read and applied to comparator 114.

Comparator 114 compares the upper addresses of ADR 113 and TAG 112. BS array 1 corresponding to TAG112 with matching upper address
The block data in 11 is set in BSDR 118 and added to the CPU and error detection circuit 120.

The error detection circuit 120 performs error detection by parity check, and when an error is detected in the data, it notifies the error control circuit 140 and the microprogram of the CPU.

Upon receiving the error occurrence notification, the error control circuit 140 sets the error control bits EC ₀ and EC ₁ of the block in the ECBM 130 to the first state (00).
The block is updated from the block to the second state (01) which indicates the occurrence of an error, and the control bit V of the block is set to "0" to invalidate the block.

After that, when another access whose lower address is the same as the error access or a retry by the CPU microprogram does not hit the BS because the upper address does not match, the comparator 114
The gate 115 sends a non-hit signal to the replacement determination circuit 153. On the other hand, control bit selector 119 sends a control bit "0" indicating that the block at the lower address is invalidated.

The replacement determination circuit 153 determines a block to be replaced by a known LRU method using the LRU table 151. At this time, the block that was invalidated due to an error occurring in the data is replaced first, giving priority to the LRU method. control so that it is done.

On the other hand, the address that accessed the BS is ADR11
3 will be sent to MSU. After a certain period of time, the data sent from the MSU is set in the MSDR 116, and then transferred to the BS specified by the replacement determination circuit 153.
It is written to a block in array 111A or 11B.

At this time, there is a block to which writing is performed.
TAG corresponding to BS array 111A or 111B
A new upper address is written into the entry 112A or 112B, and the control bit V of that entry is set to valid "1". However, the error control bit EC ₀ in that entry
and EC ₁ remains in the second state (01).

Thereafter, when another access first reads the data in this replaced block, the error detection circuit 120 detects the presence or absence of an error in this data by a parity check.

If an error is detected again in the read data, the error control circuit 140 handles this error.
It is determined that it is a hard error in BS,
TAG corresponding to the block in TAG112
Error control bits EC ₀ and EC ₁ at entry
is updated from the second state (01) to the third state (11), and the control bit B is set to invalid "0" to separate the block. The detached block will no longer be subject to address comparison or replacement for hit detection.

If no error is detected, the error control circuit 140 determines that the first error is an intermittent error that occurred in the RAM that constitutes the BS array 111, and that the information in the RAM has been successfully recovered by the move-in. The error control bits EC ₀ and EC ₁ in the TAG entry are returned from the second state (01) to the first state (00) indicating no error. Since the control bit V is set to valid "1", the TAG entry indicates that the corresponding block in the BS array 111 has valid data without errors.

Although one embodiment of the present invention has been described above,
Each configuration of the present invention is not limited to the configuration of this embodiment.

For example, error control bit memory (ECBM)
Of course, 130 may be provided separately without being shared with TAG 112.

Also, if the block of BS array 111 and the storage unit for normal reading are different, TAG1
Identification information indicating the error location within the block in 12
Hard errors occur by providing an ID and controlling the device so that if an error occurs when rereading the same location, it is disconnected, and if there is no error when rereading the same location, it returns to the first state with no error. However, it is possible to cut out only the error part without cutting out the normal part unnecessarily.

H Effect of invention The present invention has the following effects.

(b) By simply adding a small capacity error control bit memory and a simple error control circuit, buffer storage error handling can be improved from intermittent errors to
Since fixed errors can be distinguished,
By adding a small amount of hardware, it is possible to implement buffer, storage, and error processing using hardware.

(b) After an error occurs, there is no dedicated write cycle for writing data for error processing, and data is moved in from the main memory to the buffer storage array in the case of a normal buffer storage non-hit. Since this is done using , BS error processing control can be simplified.

[Brief explanation of drawings]

Fig. 1 - Block explanatory diagram of the configuration of the present invention, Fig. 2
FIG. 3 is an explanatory diagram of a tag (TAG) entry and error control bit memory in the embodiment of the present invention. In FIG. 1, 110... buffer storage (BS) device, 111... buffer storage (BS) array, 112... tag (TAG),
120...Error detection circuit, 130...Error control bit memory (ECBM), 140...Error control circuit, 150...Replacement determining means.

Claims (1)

[Claims] 1. In a buffer storage error handling method in which error processing is performed by hardware when an error occurs in a buffer storage in which writing is performed using a store-through method, (a) a buffer storage array; 111, and each storage unit in the buffer storage array 111 is in a first state with no error, a second state with an error, or a third state with the storage unit separated. (b) When an error is detected in the data of the storage unit of the buffer storage array 111, an error control bit is provided corresponding to each storage unit. The error control of the storage unit in the error control bit memory 130 changes the bit from the first state to the second state.
(c) an error control circuit 140 that updates the storage unit to the state and invalidates the storage unit, detects the presence or absence of an error in data read from the storage unit after the move-in by another access, and performs error processing; A buffer storage characterized by comprising: a replacement determining means 150 for moving data in main memory into the invalidated storage unit when the invalidated storage unit is accessed and is not hit.・Error handling method. 2. If the error processing in the error control circuit 140 detects an error again in the data read from the storage unit, the error control circuit 140 changes the corresponding error control bit in the error control bit memory 130 from the second state to the third state. 2. The buffer storage error processing method according to claim 1, wherein the buffer storage error processing method is a process of updating the storage unit to the state shown in FIG. 3. If the error processing in the error control circuit 140 detects no error in the data read from the storage unit, the error control circuit 140 changes the corresponding error control bit in the error control bit memory 130 from the second state to the first state. 2. The buffer storage error processing method according to claim 1, wherein the buffer storage error processing method is a process for returning to the state of.