JPS61258390A - Address transition detecting circuit - Google Patents

Abstract

PURPOSE:To increase extremely the margin with respect to an address skew without increasing the access time by accepting address changes up to a time point immediately before the rise of a word line starts. CONSTITUTION:An old address value is held owing to a latch constitution including a clocked gate 12 and an inverter 11 while an address transition detection start signal FE is kept at 'H'. Therefore, an inside address is never changed before the fall of a word line. Then a new address is latched by a clock inverter 5 and an inverter 4 as soon as the signal FE is set at 'L'. At the same time, a clock inverter 15 is active and therefore the new address is transmitted to the inside. Here the level of the signal FE is reduced immediately before the rise of the word line. Thus the new address can be fetched inside at that time point. As a result, the satisfactory margin is secured with respect to the address skew.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of an address transition detection circuit in a semiconductor memory device.

[Summary of the invention]

The present invention relates to the configuration of an address transition detection circuit in a semiconductor memory device, in which an old address is held in an internal address decoder means when an address transition detection start signal is present, and when the address transition detection start signal is no longer present, the current address is address skinny (address variation) by sending it to a new address decoder that has been
This increases the margin of the semiconductor memory device without increasing the access time.

[Prior art]

The address transition detection circuit used in conventional pseudo-static RAM (hereinafter referred to as PSRAM) is as shown in Figure 3. Here, 'PSRAM' refers to dynamic RAM.
M (hereinafter referred to as DRAM) and static RAM (
Hereinafter, it will be referred to as SRAM. ), and because it uses the same memory element as DRAM, the unit cost per bit is low.Also, DRAM is difficult to use because it is troublesome to refresh, but it has an internal memory for realesche. The built-in address counter makes refresh control easy. Also PSR
Like SRAM, many AMs have a built-in address transition detection circuit. The prior art will be explained below with reference to FIG. 5 and FIG. 4, which is a timing chart of FIG. 3.

(1) In Fig. 5, the old address is 1H", that is, points A, B, O, and D are all 1K, the address transition detection start signal (FK) is "H-," and the chip select signal (1) Assume that the is in the "L" state and is waiting for the address to change.

(2) When the address changes from -1 to 1L'', the A point becomes IL#, the output of EXOR8 becomes @H#, and as a result, address transition detection signal B is output.

(3) When address shift detection signal B is output, P
A control circuit within the SRAM starts operating and pulls the word line down.

(4) At the new address, the word line is lowered by delay inverter 6, and the transistor of the RAM cell is set to 07I.
After a certain period of time commensurate with the time taken to reach I', it is transmitted to the internal address decoder (Row@). What must be noted here is that if the internal address changes while the word line is 1", the RAM in PSRAM
RAM because the M cell is essentially the same as RAM
The data in the cell will be destroyed.

(5) Before the word line rises again, the internal address must be determined for the same reason as explained in (4) above. Therefore, the address transition detection start signal needs to be lowered early in consideration of the delay time of the delay inverter 6.

(6) If the input address changes after the address transition detection start signal falls, the new address will not be internalized, so the output will be as shown in Figure 4.
It becomes AI data.

[Problems and Objects to be Solved by the Invention] However, in the prior art described above, a delay circuit is used at the input because it is necessary to hold the old address internally until the word line goes down.

For this reason, it is necessary to determine the internal address before the word line rises, so the address transition detection start signal must be lowered earlier by the address delay time. Therefore, when there is a skinny address input as shown in FIG. 4, if the address access time (TAA) is shortened, there is a problem that the margin for the skinny becomes extremely small. SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a semiconductor memory device that can provide a sufficient margin for address skinny even if the address access time TAA is shortened.

[Means for solving problems]

The semiconductor memory device of the present invention includes (1) α) a first address latch means inside, and when an address transition detection start signal is present, the first address latch means inside the first address latch means is provided.
The old address value held in the address latch means of
In an address transition detection circuit that issues an address transition detection pulse when a newly input address value is different, b) connected in series with the first address latch means;
C) a second address latch means whose output is connected to an internal address decoder means; It is characterized by being in reverse phase.

[Effect]

According to the above configuration of the present invention, in order to capture a new address internally when the address transition detection start signal is lowered,
The address transition detection start signal can be kept valid until just before the word line rises, making it possible to increase the margin for address skinny.

〔Example〕

FIG. 1 shows an embodiment of an address transition detection circuit according to the present invention.
Further, FIG. 2 is a timing chart diagram for explaining the circuit operation of FIG. 1.

Embodiments of the present invention will be described in detail below based on FIG.

(1) Assume that the old address was "H" in FIG. In other words, point A, point B, point 0, and point D are all 1H.
".At this time, the chip select signal (1) is "L".
”, the address transition detection start signal (71c) is “H”, and this state is a state in which changes in the address can be detected.In addition, the internal address value is 1H when the address transition detection start signal (?E) is “H”. Clocked Gate 12 for #
is ONL, and it is 71R”.

(2) Address is current -I! When changing from "to 1L", point A becomes @L"°, so EX"'6R8 appears and disappears to 1H", and as a result, address transition detection signal B is output. However, after a while, the output of delay inverter 6 becomes 1H". Therefore, the input of EXτa8 becomes "L" again and the address transition detection signal B is reset.

(8) When the address transition detection signal B is output in (2) above, the internal control circuit starts a series of operations. Here, since the operation of the word line is largely related to the circuit of the present invention, the explanation of the present invention will be continued based on the operation of the word line.

(4) Does the input new address cause the word line to drop and the transistors in the internal memory cells to be 100? Because it is necessary to change the internal address after a time period of 1, the address transition detection start signal is held until it becomes "L".

What should be noted here is that if the internal address changes while the word line is @H'', the data in the memory cells of PSRAM will be destroyed because the memory cell A/ of PSRAM is the same as that of DRAM.

(6) For the same reason as (4) above, the internal address must be established before the word line starts rising again. In this example, by adopting the following configuration, a sufficient margin can be obtained for the skinny address.
Moreover, before the word line starts rising, the internal address is always fixed and does not move. That is, when the address transition detection start signal 7E is "■", the old address value is held by the latch configuration of the clocked gate 12 and inverter 11, so the internal address does not change before the word line falls. Further, at the moment when the address transition detection start signal 7E becomes 1L'', the new address is latched by the clocked inverter 5 and the inverter 4, and the clocked inverter 15 becomes active, so that the new address is transmitted internally. If the address transition detection start signal IE is lowered just before the word line rises, it is possible to provide a sufficient margin for the address skinny so that the new address at that time can be internalized.

On the other hand, in the conventional method, since there is always a certain delay in the input address, the delay is taken into consideration before the word line rises, and the address transition detection start signal 'f! We have to lower E. This means that it is not possible to increase the margin for address skew because address transitions cannot be detected.

〔Effect of the invention〕

As described above, according to the present invention, when the address transition detection start signal is output for a newly input address, the old address is held by the second address latch means, and the address transition detection start signal is output. By transmitting the new address twice to the first address latch means and internally when the address is exhausted, address changes can be accepted until the word line starts to rise, so the margin for address skinny is the access time. It has the effect of increasing dramatically without increasing the amount. Although the present invention has been described with respect to a PSRAM, the scope of application of the present invention is not limited to this embodiment.

[Brief explanation of drawings]

The first sound of the whistle is the second atres transition detection circuit diagram of *high 8113.
Figure 5 is a timing chart of the address transition detection circuit of the present invention Figure 5 is a conventional address transition detection circuit Figure 4 is a timing chart of a conventional address transition detection circuit Figure 1 . . . N0R 2o'e7* 9. jO, 11, 15, 14...
...Inverter 3.5, 12.15...Clocked inverter 6...Delay inverter 8...EXOR 15...Address 16... ...Chip select signal OS17...
...Address detection signal B1 day...Internal address O or above E Fig. 1 ts2 Fig.

Claims (1)

[Claims] (1)a) A first address latch means is provided internally, and when an address transition detection start signal is received, the old address value held in the internal first address latch means and the newly input address value are In an address transition detection circuit that issues an address transition detection pulse when the address transition is different, b) a second address latch connected in series with the first address latch means and whose output is connected to internal address decoder means; c) An address transition detection circuit characterized in that the control signal of the second address latch means is in opposite phase to the address transition detection start signal which is the control signal of the first address latch means.