JPS612570A - Trouble-detecting circuit for printing head driver - Google Patents
Trouble-detecting circuit for printing head driverInfo
- Publication number
- JPS612570A JPS612570A JP10242884A JP10242884A JPS612570A JP S612570 A JPS612570 A JP S612570A JP 10242884 A JP10242884 A JP 10242884A JP 10242884 A JP10242884 A JP 10242884A JP S612570 A JPS612570 A JP S612570A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- voltage
- trouble
- short
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/22—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of impact or pressure on a printing material or impression-transfer material
- B41J2/23—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of impact or pressure on a printing material or impression-transfer material using print wires
- B41J2/30—Control circuits for actuators
Abstract
Description
【発明の詳細な説明】
(1)産業上の利用分野
本発明はプリンタの複数の印字ヘッドピンドライバの短
絡異常を検知する検知回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (1) Field of Industrial Application The present invention relates to a detection circuit for detecting short-circuit abnormalities in a plurality of print head pin drivers of a printer.
(2)従来技術と問題点
従来、シリアルドツトプリンタの印字ヘッドピンドライ
バ(駆動回路)は第2図の従来回路に示すように、エミ
ッター接地の駆動トランジスタ11〜1Nのベースに駆
動入力1〜Nを与え、それぞれのコレクタから駆動コイ
ルL1〜LHを介し第1の電源VCclに接続される。(2) Prior art and problems Conventionally, the print head pin driver (drive circuit) of a serial dot printer applies drive inputs 1 to N to the bases of drive transistors 11 to 1N whose emitters are grounded, as shown in the conventional circuit in Figure 2. , are connected to a first power supply VCcl from their respective collectors via drive coils L1 to LH.
このトランジスタ11〜1Nのコレクタよシダイオード
を介して共通にし、第2の電源Vcc2から抵抗r1で
バイアスした@点に接続し、この電圧■を比較器2の負
端子に入力するとともに、第2の電源Vcc2に接続し
た抵抗r2*r3の分圧点■から参照電圧V6を取出し
比較器2の正端子に入力する。この比較器2の出力を第
2の電源Vcc2から抵抗デ4でバイアスした0点に接
続Q1この信号を(入力1〜人力N)の反転信号ととも
にAND回路3を通してクリップフロップ(FF)4を
セットして出力させる。The collectors of these transistors 11 to 1N are made common via a diode and connected to a point @ which is biased with a resistor r1 from the second power supply Vcc2, and this voltage ■ is input to the negative terminal of the comparator 2, and the second A reference voltage V6 is taken out from the voltage dividing point (3) of the resistor r2*r3 connected to the power supply Vcc2 of the comparator 2 and inputted to the positive terminal of the comparator 2. Connect the output of this comparator 2 from the second power supply Vcc2 to the 0 point biased with a resistor D4 Q1. This signal is passed through an AND circuit 3 together with the inverted signal of (input 1 to human power N) to set a clip-flop (FF) 4. and output it.
すなわち、印字ヘッドピンドライバ11〜1Nの何れか
がオンとなると、比較器2の出力は高レベルとなるが、
短絡異常の場合には入力1〜人力Nを与えなくても高レ
ベルとなJ AND回路5が出力されてFF4をセット
する。これにより異常が検知される。That is, when any of the print head pin drivers 11 to 1N is turned on, the output of the comparator 2 becomes high level, but
In the case of a short-circuit abnormality, the JAND circuit 5 outputs a high level even if inputs 1 to N are not applied, and sets FF4. This allows abnormalities to be detected.
しかし、この回路の欠点は、比較器2は常時オンされ参
照電圧vbが確立しているのに対し、トランジスタ11
〜1Nは間欠的であるから、第3図の■VcC1と■V
cc2のタイミングで示すように、■CC1の立上りは
Vcc2の確立後に行なわれ、従って0点の電圧レベル
■αが0点の参照電圧Vb以下になる期間Pが存在する
ため0点電圧が高レベルとなシ、異常でないにもかかわ
らず異常とみなされてしまう。この対策として、Vcc
1投入よシ一定時間だけ異常検知を無効とする方法がと
られた。この時間は電源の変動、バラツキを考慮して多
きめに設定する必要があるが本当の異常時を包含してし
まい、印字ヘッドを焼損する危険性があった。However, the drawback of this circuit is that the comparator 2 is always on and the reference voltage vb is established, whereas the transistor 11
~1N is intermittent, so ■VcC1 and ■V in Figure 3
As shown by the timing of cc2, ■The rise of CC1 is performed after the establishment of Vcc2, and therefore the voltage level of the 0 point ■There is a period P in which α is less than the reference voltage Vb of the 0 point, so the 0 point voltage is at a high level Tonashi, it is considered abnormal even though it is not abnormal. As a countermeasure for this, Vcc
A method was adopted in which abnormality detection was disabled for a certain period of time after one injection. This time needs to be set long enough to take account of fluctuations and dispersions in the power supply, but it includes true abnormal times, and there is a risk of burning out the print head.
(3)発明の目的
本発明の目的はプリンタの複数の印字ヘッドピンドライ
バの短絡異常を正確に判別検知できる印字ヘッドドライ
バ異常検知回路を提供するととである。(3) Object of the Invention An object of the present invention is to provide a print head driver abnormality detection circuit that can accurately determine and detect short-circuit abnormalities in a plurality of print head pin drivers of a printer.
(4)発明の構成
前記目的を達成するため、本発明の印字ヘッドドライバ
異常検知回路は第1の電源により給電され複数の印字ヘ
ッドピンドライバの何れかのオンを検知する検知回路と
、該第1の電源により給電され該検知回路の出力と前記
印字へラドビンドライバの何れかの短絡異常に対応する
第1の参照値とを比較する第1の比較回路と、第2の電
源に接続され前記第1の比較回路の出力を所定の時定数
回路を通して第2の参照値とを比較する第2の比較回路
とを具え、該第2の比較回路出力により正常印字を除き
短絡異常を判別検知することを特徴とするものである。(4) Structure of the Invention In order to achieve the above object, the print head driver abnormality detection circuit of the present invention includes a detection circuit that is powered by a first power source and detects whether any of a plurality of print head pin drivers is turned on; a first comparison circuit that is powered by a power source and compares the output of the detection circuit with a first reference value corresponding to a short-circuit abnormality in one of the printing Radbin drivers; and a second comparison circuit that compares the output of the first comparison circuit with a second reference value through a predetermined time constant circuit, and uses the output of the second comparison circuit to determine and detect short-circuit abnormalities except for normal printing. It is characterized by this.
(5)発明の実施例
本発明の原理は、第2図の従来例では比較器2の入力■
と■とがP期間に反転しているのは、■は第1の電源V
cclに依存しているのに対し、■は第2の電源VcC
2のみにより確立していることに起因している。そこで
比較器2の入力VA、VBとも第1の電源の立上シに追
従させるようにし、さらにこの比較器出力に時定数を設
け、印字の場合と短絡異常の場合とでは時定数の立上シ
ミ圧が異なるから、所定の参照値を設けた第2の比較器
で異常を検出するようにしたものである。(5) Embodiment of the Invention The principle of the present invention is that in the conventional example shown in FIG.
The reason that and ■ are inverted during the P period is because ■ is the first power supply V
ccl, while ■ is dependent on the second power supply VcC.
This is due to the fact that it is established only by 2. Therefore, inputs VA and VB of comparator 2 are made to follow the rise of the first power supply, and a time constant is provided for the output of this comparator, and the time constant rises in the case of printing and in the case of short circuit abnormality. Since the stain pressures are different, a second comparator provided with a predetermined reference value is used to detect an abnormality.
第1図は本発明の実施例の構成説明図である。FIG. 1 is an explanatory diagram of the configuration of an embodiment of the present invention.
同図において駆動用トランジスタ11〜1Nのコレクタ
からダイオードを介して共通にし、第1の電源Vcc1
により給電されたコレクタ側接地のトランジスタ11の
ベースに接続する。コレクタ回路の抵抗R3+ R4の
分圧点■の電圧■ムと、Veclから別に分岐させた抵
抗R1+ R2の分圧点■の電圧Vnを取出し、比較器
12の正、負端子にそれぞれ入力させる。In the figure, the collectors of the driving transistors 11 to 1N are connected in common through diodes, and connected to a first power supply Vcc1.
The base of the transistor 11 whose collector side is grounded is connected to the base of the transistor 11 whose collector side is supplied with power. The voltage (2) at the voltage dividing point (2) of the resistors R3+R4 of the collector circuit and the voltage Vn at the voltage dividing point (2) of the resistors R1+R2 separately branched from Vecl are taken out and input to the positive and negative terminals of the comparator 12, respectively.
この比較器12の出力を抵抗R5を介して第2の電源V
cc2に接続された時定数回路R6a、間の0点に接続
され、さらに抵抗R7を介して別の比較器16の正端子
に入力する。負端子には同じ電源Vce2に接続した抵
抗R8+ R9の分圧点0点の参照電圧Vffiを入力
する。そして該比較器13の出力によりフリップフロッ
グ(FF)4をセットさせる。The output of this comparator 12 is connected to the second power supply V via a resistor R5.
It is connected to the 0 point between the time constant circuit R6a connected to cc2, and further inputted to the positive terminal of another comparator 16 via a resistor R7. A reference voltage Vffi at a voltage dividing point 0 of resistors R8+R9 connected to the same power supply Vce2 is input to the negative terminal. Then, a flip-flop (FF) 4 is set by the output of the comparator 13.
この構成では、トランジスタ1、〜1Nの何れかが破損
短絡してトランジスタ11がオンとなると■点、■点電
圧vA 、Vnとも第1の電源Vcc1に依存して立上
シ、第4図■Vcclの波形の関係となる。逆にこのよ
うに短絡時VB> VAとなるように抵抗R1゜R2、
R3,R4を設定しておく。これにより比較器12の出
力は高レベルとなる。このとき同図■VC62は■点、
■点電圧には関与しない。In this configuration, if any of the transistors 1 to 1N is damaged or short-circuited and the transistor 11 is turned on, the voltages vA and Vn at points 2 and 2 both start up depending on the first power supply Vcc1, as shown in FIG. This is the relationship between the Vccl waveform. Conversely, resistors R1゜R2, so that VB > VA when short-circuited,
Set R3 and R4. As a result, the output of the comparator 12 becomes high level. At this time, ■ VC62 in the same figure is ■ point,
■Not involved in point voltage.
この比較回路12の出力を抵抗R5を介して時定数回路
R6+ C1の接続点@のレベルをその時定数に応じて
上昇させる。この場合、同図■に示すようにVB v
v、 l VDの関係は立上シから同じ関係で配列され
途中で相互に反転することはない。The output of this comparison circuit 12 is passed through a resistor R5 to increase the level at the connection point @ of the time constant circuit R6+C1 in accordance with the time constant. In this case, as shown in ■ in the same figure, VB v
The relationship between v and l VD is arranged in the same relationship from start-up, and there is no mutual inversion during the process.
との0点の電圧VDを抵抗孔7を介して比、較器13の
負端子に、参照電圧VI+を正端子に入力して比較する
ことにより、第5図に示すように、Vo>Vmの場合に
異常が検出される。By comparing the voltage VD at the 0 point through the resistor hole 7 and inputting the reference voltage VI+ to the positive terminal of the comparator 13, as shown in FIG. 5, Vo>Vm An abnormality is detected when .
これに対し、通常の印字の場合はvrに示されるように
立上シミ圧が■!に達L7ないうちに下降しVgを超え
ないように設定される。このようにして印字と短絡異常
を識別することができる。On the other hand, in the case of normal printing, the rising stain pressure is ■! as shown in vr. It is set so that the voltage decreases before reaching L7 and does not exceed Vg. In this way, printing and short-circuit abnormalities can be distinguished.
(6)発明の詳細
な説明したように、本発明によれば、複数の印字ヘッド
ドライバの短絡異常を検知する場合、第1の電源の立上
シ後一定時間異常検出を無効とするようなこともなく正
確に印字と短絡異常を判別検知することができるもので
ある。(6) As described in detail, according to the present invention, when detecting a short-circuit abnormality in a plurality of print head drivers, the abnormality detection is disabled for a certain period of time after the first power source is turned on. It is possible to accurately distinguish and detect printing and short-circuit abnormalities without any problems.
第1図は本発明の実施例の構成説明図、第2図は従来例
の構成説明図、第3図は従来例の問題点の説明図、第4
図、第5図は本発明の実施例の原理および動作説明図で
ア)、図中、11〜1Nは駆動トランジスタ、4はフリ
ップフロップ、11はトランジスタ、12.13は比較
器を示す。FIG. 1 is an explanatory diagram of the configuration of the embodiment of the present invention, FIG. 2 is an explanatory diagram of the configuration of the conventional example, FIG. 3 is an explanatory diagram of problems in the conventional example, and FIG.
Figure 5 is a diagram explaining the principle and operation of an embodiment of the present invention.A) In the figure, 11 to 1N are drive transistors, 4 is a flip-flop, 11 is a transistor, and 12 and 13 are comparators.
Claims (1)
バの何れかのオンを検知する検知回路と、該第1の電源
により給電され該検知回路の出力と前記印字ヘッドピン
ドライバの何れかの短絡異常に対応する第1の参照値と
を比較する第1の比較回路と、第2の電源に接続され前
記第1の比較回路の出力を所定の時定数回路を通して第
2の参照値とを比較する第2の比較回路とを具え、該第
2の比較回路出力により正常印字を除き短絡異常を判別
検知することを特徴とする印字ヘッドドライバ異常検知
回路。A detection circuit that is powered by a first power source and detects whether any of the plurality of print head pin drivers is turned on; and a detection circuit that is powered by the first power source and responds to a short-circuit abnormality between the output of the detection circuit and any of the print head pin drivers. a first comparison circuit that is connected to a second power supply and that compares the output of the first comparison circuit with a second reference value through a predetermined time constant circuit; A print head driver abnormality detection circuit, comprising: a comparison circuit, and detects short-circuit abnormality by excluding normal printing based on the output of the second comparison circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10242884A JPS612570A (en) | 1984-05-21 | 1984-05-21 | Trouble-detecting circuit for printing head driver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10242884A JPS612570A (en) | 1984-05-21 | 1984-05-21 | Trouble-detecting circuit for printing head driver |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS612570A true JPS612570A (en) | 1986-01-08 |
JPH047711B2 JPH047711B2 (en) | 1992-02-12 |
Family
ID=14327186
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10242884A Granted JPS612570A (en) | 1984-05-21 | 1984-05-21 | Trouble-detecting circuit for printing head driver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS612570A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4875409A (en) * | 1987-07-01 | 1989-10-24 | Printronix, Inc. | Magnetic print hammer actuator protection circuit |
US5302033A (en) * | 1991-03-26 | 1994-04-12 | Citizen Watch Co., Ltd. | Burning damage protecting apparatus and method for a printing head in a printer |
WO2007097298A1 (en) | 2006-02-27 | 2007-08-30 | Feather Safety Razor Co., Ltd. | Edged tool |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59104956A (en) * | 1982-12-09 | 1984-06-18 | Tokyo Electric Co Ltd | Failure detecting apparatus in wire drive circuit of dot printer |
-
1984
- 1984-05-21 JP JP10242884A patent/JPS612570A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59104956A (en) * | 1982-12-09 | 1984-06-18 | Tokyo Electric Co Ltd | Failure detecting apparatus in wire drive circuit of dot printer |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4875409A (en) * | 1987-07-01 | 1989-10-24 | Printronix, Inc. | Magnetic print hammer actuator protection circuit |
US5302033A (en) * | 1991-03-26 | 1994-04-12 | Citizen Watch Co., Ltd. | Burning damage protecting apparatus and method for a printing head in a printer |
WO2007097298A1 (en) | 2006-02-27 | 2007-08-30 | Feather Safety Razor Co., Ltd. | Edged tool |
US20100137894A1 (en) * | 2006-02-27 | 2010-06-03 | Feather Safety Razor Co., Ltd | Edged tool |
Also Published As
Publication number | Publication date |
---|---|
JPH047711B2 (en) | 1992-02-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |