JPH01129714A - Power interruption detecting circuit - Google Patents

Power interruption detecting circuit

Info

Publication number
JPH01129714A
JPH01129714A JP28812887A JP28812887A JPH01129714A JP H01129714 A JPH01129714 A JP H01129714A JP 28812887 A JP28812887 A JP 28812887A JP 28812887 A JP28812887 A JP 28812887A JP H01129714 A JPH01129714 A JP H01129714A
Authority
JP
Japan
Prior art keywords
level
power interruption
printer
power failure
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP28812887A
Other languages
Japanese (ja)
Other versions
JPH0787669B2 (en
Inventor
Yoshitomo Sasaki
佐々木 義朋
Shinji Hasegawa
慎二 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba TEC Corp
Original Assignee
Tokyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electric Co Ltd filed Critical Tokyo Electric Co Ltd
Priority to JP62288128A priority Critical patent/JPH0787669B2/en
Publication of JPH01129714A publication Critical patent/JPH01129714A/en
Publication of JPH0787669B2 publication Critical patent/JPH0787669B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09BORGANIC DYES OR CLOSELY-RELATED COMPOUNDS FOR PRODUCING DYES, e.g. PIGMENTS; MORDANTS; LAKES
    • C09B5/00Dyes with an anthracene nucleus condensed with one or more heterocyclic rings with or without carbocyclic rings
    • C09B5/02Dyes with an anthracene nucleus condensed with one or more heterocyclic rings with or without carbocyclic rings the heterocyclic ring being only condensed in peri position
    • C09B5/14Benz-azabenzanthrones (anthrapyridones)

Landscapes

  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

PURPOSE:To eliminate erroneous detection of source voltage drop except in case of power interruption, by judging power interruption with high or low level respectively for turning ON or OFF of an incorporated printer. CONSTITUTION:When a motor is driving, an output(b) from a first Zener diode ZD1 set with a lowest voltage level, as a Zener voltage, of a head in an incorporated printer is fed as a power interruption detecting level to an integrated circuit IC1 for an inverter. If source voltage level (a) is lower than a lowest operating level at this time, power interruption is detected and printing operation is stopped. When the motor is stopped, an output (c) of a second Zener diode ZD2 set with a Zener voltage lower than the Zener voltage when the motor is driving is fed as a power interruption detecting level to the integrated circuit IC1 for inverter. Even if the source voltage level (a) drops due to an optional machine and the like, power interruption is not detected so long as the droppage is within the output voltage level (c).

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、電子式キャッシュレジスタ等のようにプリン
タを内蔵した電子機器に利用される停電検出回路に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power outage detection circuit used in electronic equipment having a built-in printer, such as an electronic cash register.

【従来の技術l 一般に電子機器には停電検出回路が組込まれており、そ
の停電検出レベルは従来一定で固定されていた。このこ
とは電子式キャッシュレジスタ等のように内蔵プリンタ
例えばドツトプリンタを内蔵した電子機器においても同
様である。ところがドツトプリンタの場合、ヘッド電圧
として例えば20ボルトの高電圧が必要となり、これよ
りも低くなると印字文字が薄くなる等の不具合を生じる
[Prior Art 1] Generally, electronic equipment has a built-in power failure detection circuit, and the power failure detection level has conventionally been fixed at a constant level. This also applies to electronic devices such as electronic cash registers that include a built-in printer, such as a dot printer. However, in the case of a dot printer, a high voltage of, for example, 20 volts is required as the head voltage, and if it is lower than this, problems such as printed characters becoming thinner occur.

このため、この種電子機器においては、内蔵プリンタの
ヘッド電圧を確保するために一定の停電検出レベルを比
較的高レベルに設定する必要があった。
Therefore, in this type of electronic equipment, it is necessary to set a certain power failure detection level to a relatively high level in order to ensure the head voltage of the built-in printer.

[発明が解決しようとする問題点]     ′しかる
に、停電検出レベルを高レベルに設定した場合には内蔵
プリンタのオフ時に生じる停電以外の電源電圧レベルの
降下を停電とみなしてしまうことがあった。特に、この
種″電子機器に内蔵プリンタとは別のプリンタなどのオ
プション機器が外部接続された場合、上記オプション機
器のM源オン時に生じるN′m電圧レベルの降下を停電
とみなすおそれがあった。
[Problems to be Solved by the Invention] 'However, when the power failure detection level is set to a high level, a drop in the power supply voltage level other than a power failure that occurs when the built-in printer is turned off may be regarded as a power failure. In particular, when an optional device such as a printer other than the built-in printer is externally connected to this type of electronic device, there is a risk that the drop in the N'm voltage level that occurs when the M power source of the optional device is turned on may be regarded as a power outage. .

そこで本発明は、内蔵プリンタのヘッド電圧に対する停
電検出精度を充分に確保でき、かつ停電以外の電源電圧
レベルの低下を誤検出するおそれがなく、高信頼度で実
用性の高い停電検出回路を提供しようとするものである
Therefore, the present invention provides a highly reliable and highly practical power failure detection circuit that can sufficiently ensure power failure detection accuracy for the head voltage of a built-in printer and is free from the risk of erroneously detecting a drop in power supply voltage level other than a power failure. This is what I am trying to do.

[問題点を解決するための手段] 本発明は、プリンタを内蔵した宵子m器の停電検出回路
において、第1の停電検出レベルを設定する第1の設定
部と、この第1の停電検出レベルよりも低い第2の停電
検出レベルを設定する第2の設定部と、内蔵プリンタの
オン時には第1の停電検出レベルを選択し、内蔵プリン
タのオフ時には第2の停電検出レベルを選択するレベル
選択部と、この選択部により選択された停電検出レベル
に基いて停電判定を行なう停電判定部とからなるもので
ある。
[Means for Solving the Problems] The present invention provides a power outage detection circuit for a Yoiko meter with a built-in printer, including a first setting section for setting a first power outage detection level, and a first setting section for setting a first power outage detection level. a second setting section for setting a second power failure detection level lower than the power failure detection level; and a level for selecting the first power failure detection level when the built-in printer is turned on and selecting the second power failure detection level when the built-in printer is turned off. It consists of a selection section and a power outage determination section that makes a power outage determination based on the power outage detection level selected by the selection section.

[作用] このような手段を講じたことにより、内蔵プリンタのオ
ン時には比較的高レベルで停電判定が行なわれ、プリン
タのヘッド電圧が充分に保障される。内蔵プリンタのオ
フ時には比較的低レベルで停電判定が行なわれ、停電以
外に電源電圧レベルの低下を誤検出することがない。
[Operation] By taking such measures, a power failure determination is made at a relatively high level when the built-in printer is turned on, and the head voltage of the printer is sufficiently guaranteed. When the built-in printer is turned off, a power failure determination is made at a relatively low level, and there is no possibility of erroneously detecting a drop in the power supply voltage level other than a power failure.

[実施例] 以下、本発明を電子式キャッシュレジスタ等のドツトプ
リンタ内蔵型の電子機器に適用した一実施例について図
面を参照しながら説明する。
[Embodiment] Hereinafter, an embodiment in which the present invention is applied to an electronic device with a built-in dot printer, such as an electronic cash register, will be described with reference to the drawings.

第1図は本実施例の回路構成図、第2図は第1図中のポ
イント(a)〜(f)における信号波形図である。第1
図において11はIR電源入力端子あり、この端子11
には第1のツェナダイオードZD1と第2のツェナダイ
オードZD2の各カソードが並列に接続されている。第
1のツェナダイオードZD1は、ツェナ電圧V1として
内蔵プリンタのヘッド電圧の最低動作レベル例えば20
ボルトが設定されており、そのアノードはインバータ用
集積回路ICIの入力端子に接続されている。
FIG. 1 is a circuit configuration diagram of this embodiment, and FIG. 2 is a signal waveform diagram at points (a) to (f) in FIG. 1. 1st
In the figure, 11 is an IR power input terminal, and this terminal 11
The cathodes of a first Zener diode ZD1 and a second Zener diode ZD2 are connected in parallel. The first Zener diode ZD1 has a Zener voltage V1 of the lowest operating level of the head voltage of the built-in printer, for example 20.
Volt is set and its anode is connected to the input terminal of the inverter integrated circuit ICI.

第2のツェナダイオードZD2は、ツェナ電圧■2とし
て上記第1のツェナダイオードZDIのツェナ電圧■1
よりも低い例えば12ボルトが設定されており、そのア
ノードはPNP型の第1のトランジスタQ1のエミッタ
に接続されている。
The second Zener diode ZD2 uses the Zener voltage ■1 of the first Zener diode ZDI as the Zener voltage ■2.
12 volts, for example, and its anode is connected to the emitter of the first PNP transistor Q1.

上記トランジスタQ1のエミッタ・ベース間には抵抗R
1が介在されており、ベースは抵抗R2を介してNPN
型の第2のトランジスタQ2のコレクタに接続している
。また、上記第1のトランジスタQ1のコレクタには前
記インバータ用集積回路ICIの入力端子が接続されて
いる。
There is a resistor R between the emitter and base of the transistor Q1.
1 is interposed, and the base is NPN via resistor R2.
Q2 is connected to the collector of the second transistor Q2 of type Q2. Further, the input terminal of the inverter integrated circuit ICI is connected to the collector of the first transistor Q1.

12は内蔵プリンタのモータ駆動信号の入力端子であり
、この端子I2には第2のインバータ用集積回路IC2
の入力端子が接続されている。上記インバータ用集積回
路IC2の出力端子には抵抗R3を介して前記第2のト
ランシタQ2のベースが接続されている。上記第2のト
ランジスタQ2のエミッタは接地されており、ベース・
エミッタ間には抵抗R4が介在されている。
12 is an input terminal for a motor drive signal of the built-in printer, and this terminal I2 is connected to a second inverter integrated circuit IC2.
input terminal is connected. The output terminal of the inverter integrated circuit IC2 is connected to the base of the second transistor Q2 via a resistor R3. The emitter of the second transistor Q2 is grounded, and the base
A resistor R4 is interposed between the emitters.

前記第1のインバータ用集積回路IC1には抵抗R5お
よびコンデンサCの8値によって決められるスレッシュ
ホールドレベルSHが設定されており、その出力端子は
停電検出信号の出力端子PFに接続している。
A threshold level SH determined by eight values of a resistor R5 and a capacitor C is set in the first inverter integrated circuit IC1, and its output terminal is connected to an output terminal PF of a power failure detection signal.

次に、電源入力端子11および信号入力端子■2に第2
図中(a)および(d>に示す計時的変化をとる電源電
圧およびモータ駆動信号が供給された場合の本実施例回
路の動作について説明する。すなわち、時点toにおい
て電源電圧が入力され、その電圧レベルが第1.第2の
ツェナダイオードZD1.ZD2f)’)工を電圧V1
.V2にiすると、各ダイオードZD1.ZD2のカソ
ードに同図中(b)、(c)に示す波形の電圧が出力さ
れる。なお、上記出力(b)の電圧レベルv4は[V3
−V1]となり、出力(c)(7)電JIレベルV5は
[V3−V2]となる。そして、電源電圧入力時にはモ
ータ駆動信号がLOWレベル(停止指令)なので第2の
トランジスタQ2がオンであり、これにより第1のトラ
ンジスタQ1もオンである。したがって第2のツェナダ
イオードZD2の出力(C)が選択され、この出力(C
)がインバータ用集積回路IC1への入力(e)となる
。その結果、時点t1において上記入力(e)がインバ
ータ用集積回路IC1のスレッシュホールドレベルSH
に達すると、この回路ICIの出力が反転してLOWレ
ベルの停電検出波形(f)となる。
Next, the second
The operation of the circuit of this embodiment will be explained when a power supply voltage and a motor drive signal that change over time as shown in (a) and (d) in the figure are supplied.In other words, the power supply voltage is input at time to, and the The voltage level of the first and second Zener diodes ZD1.ZD2f)') is set to the voltage V1.
.. V2, each diode ZD1. Voltages with waveforms shown in (b) and (c) in the figure are output to the cathode of ZD2. Note that the voltage level v4 of the above output (b) is [V3
-V1], and the output (c) (7) electric JI level V5 becomes [V3-V2]. When the power supply voltage is input, the motor drive signal is at a LOW level (stop command), so the second transistor Q2 is on, and thereby the first transistor Q1 is also on. Therefore, the output (C) of the second Zener diode ZD2 is selected;
) becomes the input (e) to the inverter integrated circuit IC1. As a result, at time t1, the input (e) is at the threshold level SH of the inverter integrated circuit IC1.
When the output of this circuit ICI is inverted, it becomes a power failure detection waveform (f) of LOW level.

この状態で、時点t2においてモータ駆動信号(d)が
HIGHレベル(駆動指令)になると第2のトランジス
タQ2がオフとなるので第1のトランジスタQ1もオフ
する。したがって第1のツェナダイオードZD1の出力
(b)が選択され、この出力(b)がインバータ用集積
回路ICIへの入力(e)となる。
In this state, when the motor drive signal (d) becomes HIGH level (drive command) at time t2, the second transistor Q2 is turned off, and therefore the first transistor Q1 is also turned off. Therefore, the output (b) of the first Zener diode ZD1 is selected, and this output (b) becomes the input (e) to the inverter integrated circuit ICI.

その後、時点t3においてモータ駆動信号がLOWレベ
ルになると、第1.第2のトランジスタQ1.Q2がオ
フすることによりインバータ用集積回路ICIへの入力
(e)として第2のツェナダイオードZD2の出力(C
)が選択される。
Thereafter, when the motor drive signal becomes LOW level at time t3, the first . Second transistor Q1. When Q2 is turned off, the output of the second Zener diode ZD2 (C
) is selected.

時点t4からt5にかけては、内蔵プリンタの運転停止
時において例えば本実施例の電子機器に外部接続された
プリンタなどのオプション機器の起動により電源電圧レ
ベル(a)が落込んだ場合を示している。
From time t4 to time t5, a case is shown in which the power supply voltage level (a) drops due to activation of an optional device such as a printer externally connected to the electronic device of this embodiment when the built-in printer is stopped.

そして、時点t6において電源がオフし、時点t7にお
いてインバータ用集積回路1c1の入力(e)がインバ
ータ用集積回路IC1のスレッシュホールドレベルSH
まで低下すると、この回路ICIの出力(f)が反転覆
る。このとき、インバータ用集積回路ICIの入力(e
)としてはモータ駆動信りがLOWレベルであるのでツ
ェナダイオードZD2の出力(C)が選択されている。
Then, at time t6, the power is turned off, and at time t7, the input (e) of the inverter integrated circuit 1c1 reaches the threshold level SH of the inverter integrated circuit IC1.
When the output (f) of this circuit ICI is inverted and reversed. At this time, the input of the inverter integrated circuit ICI (e
), the motor drive signal is at a LOW level, so the output (C) of the Zener diode ZD2 is selected.

このように本実施例においては、モータ駆動時すなわち
モータ駆動信号(d)がHIGHレベルの場合にはツェ
ナ電圧V1として内蔵プリンタのヘッドの最低動作レベ
ルが設定された第1のツェナダイオードzD1の出力(
b)が停電検出レベルとして選択され、インバータ用集
積回路ICIに供給される。したがって、このときにa
!電源電圧レベルa)が最低動作レベル■1を下回った
場合には停電検出がかかり、プリンタの印字動作が停止
する。その結果、プリンタのヘッド電圧を充分に確保す
ることができ、安定な印字動作が可能となる。
As described above, in this embodiment, when the motor is driven, that is, when the motor drive signal (d) is at the HIGH level, the output of the first Zener diode zD1 is set as the Zener voltage V1 to the lowest operating level of the head of the built-in printer. (
b) is selected as the power failure detection level and supplied to the inverter integrated circuit ICI. Therefore, at this time a
! When the power supply voltage level a) falls below the minimum operating level (1), a power failure is detected and the printing operation of the printer is stopped. As a result, sufficient head voltage of the printer can be ensured, and stable printing operation becomes possible.

一方、モータ停止時すなわちモータ駆動信号(d)がL
OWレベルの場合にはツェナ電圧v2として第1のツェ
ナダイオードzD1のツェナ電圧v1よりも低い電圧レ
ベルが設定された第2のツェナダイオードZD2の出力
(C)が停電検出レベルとして選択され、インバータ用
集積回路IC1に供給される。したがって、このときに
オプション機器の起動等により電源電圧レベル(a)が
落込んでも、その落込みが電圧レベルV5−V3−V2
の範囲内であれば停電検出はかからない。ところが、停
電検出レベルとしてヘッド電圧を青虫した第1のツェナ
ダイオードzD1の出力(b)を選択すると、落込みが
V5の範囲内であっても停電検出がかかるおそれがある
。その結果、内蔵プリンタ停止時において、停電以外の
電圧レベルの落込みに誤動作するおそれがなくなり、信
頼性の向上をはかり得、実用性が高められる。
On the other hand, when the motor is stopped, that is, the motor drive signal (d) is L.
In the case of the OW level, the output (C) of the second Zener diode ZD2, in which a voltage level lower than the Zener voltage v1 of the first Zener diode ZD1 is set as the Zener voltage v2, is selected as the power failure detection level, and the voltage level for the inverter is It is supplied to the integrated circuit IC1. Therefore, even if the power supply voltage level (a) drops due to activation of an optional device, etc. at this time, the drop will be at voltage level V5-V3-V2.
If it is within the range, power outage detection will not occur. However, if the output (b) of the first Zener diode zD1 with the head voltage adjusted is selected as the power failure detection level, there is a possibility that a power failure will be detected even if the drop is within the range of V5. As a result, when the built-in printer is stopped, there is no risk of malfunction due to a drop in voltage level other than a power outage, improving reliability and increasing practicality.

また、従来においてオプション機器の起動等による電圧
レベルの低下を抑制するために電源容量を拡大すること
により誤動作を低減させることが可能であるが、本実施
例を適用することにより特にその必要もなくなる。
Additionally, in the past, it was possible to reduce malfunctions by expanding the power supply capacity in order to suppress the drop in voltage level due to activation of optional equipment, etc., but by applying this embodiment, this is no longer necessary. .

[発明の効果] 以上詳述したように、本発明によれば、内蔵プリンタの
ヘッド電圧に対する停電検出精度を充分に確保でき、か
つ停電以外の電源電圧レベルの低下を誤検出するおそれ
がなく、高信頼度で実用性の高い停電検出回路を提供で
きる。
[Effects of the Invention] As described in detail above, according to the present invention, it is possible to sufficiently ensure power failure detection accuracy for the head voltage of the built-in printer, and there is no risk of erroneously detecting a drop in the power supply voltage level other than a power failure. A highly reliable and highly practical power failure detection circuit can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本実施例の回路構成図、第2図は同実施例にお
ける回路主要部の信号波形図である。 ZDl、ZD2・・・ツェナダイオード、Ql。 Q2・・・トランジスタ、IC1,1C2・・・インバ
ータ用集積回路。 出願人代理人 弁理士 鈴江武彦
FIG. 1 is a circuit configuration diagram of this embodiment, and FIG. 2 is a signal waveform diagram of the main parts of the circuit in the same embodiment. ZDl, ZD2... Zener diode, Ql. Q2...Transistor, IC1, 1C2...Inverter integrated circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

【特許請求の範囲】[Claims] プリンタを内蔵した電子機器の停電検出回路において、
第1の停電検出レベルを設定する第1の設定部と、前記
第1の停電検出レベルよりも低い第2の停電検出レベル
を設定する第2の設定部と、前記内蔵プリンタのオン時
には前記第1の停電検出レベルを選択し、前記内蔵プリ
ンタのオフ時には前記第2の停電検出レベルを選択する
レベル選択部と、この選択部により選択された停電検出
レベルに基いて停電判定を行なう停電判定部とからなる
ことを特徴とする停電検出回路。
In the power failure detection circuit of electronic equipment with a built-in printer,
a first setting unit for setting a first power failure detection level; a second setting unit for setting a second power failure detection level lower than the first power failure detection level; and a second setting unit for setting a second power failure detection level lower than the first power failure detection level; a level selection section that selects a first power outage detection level and selects a second power outage detection level when the built-in printer is turned off; and a power outage determination section that makes a power outage determination based on the power outage detection level selected by the selection section. A power outage detection circuit comprising:
JP62288128A 1987-11-13 1987-11-13 Power failure detection circuit Expired - Fee Related JPH0787669B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62288128A JPH0787669B2 (en) 1987-11-13 1987-11-13 Power failure detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62288128A JPH0787669B2 (en) 1987-11-13 1987-11-13 Power failure detection circuit

Publications (2)

Publication Number Publication Date
JPH01129714A true JPH01129714A (en) 1989-05-23
JPH0787669B2 JPH0787669B2 (en) 1995-09-20

Family

ID=17726171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62288128A Expired - Fee Related JPH0787669B2 (en) 1987-11-13 1987-11-13 Power failure detection circuit

Country Status (1)

Country Link
JP (1) JPH0787669B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0352511A (en) * 1989-07-19 1991-03-06 Tokyo Electric Co Ltd Service interruption detection circuit

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5190452A (en) * 1975-02-05 1976-08-07
JPS5875418A (en) * 1981-10-30 1983-05-07 株式会社日立製作所 Overcurrent detecting system for power source
JPS59176328U (en) * 1983-05-12 1984-11-26 横河電機株式会社 Power outage detection circuit
JPS59220816A (en) * 1983-05-27 1984-12-12 Hitachi Ltd Overcurrent detection system
JPS6049417A (en) * 1983-08-29 1985-03-18 Nec Corp Overcurrent detecting circuit
JPS6375877U (en) * 1986-11-07 1988-05-20

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5190452A (en) * 1975-02-05 1976-08-07
JPS5875418A (en) * 1981-10-30 1983-05-07 株式会社日立製作所 Overcurrent detecting system for power source
JPS59176328U (en) * 1983-05-12 1984-11-26 横河電機株式会社 Power outage detection circuit
JPS59220816A (en) * 1983-05-27 1984-12-12 Hitachi Ltd Overcurrent detection system
JPS6049417A (en) * 1983-08-29 1985-03-18 Nec Corp Overcurrent detecting circuit
JPS6375877U (en) * 1986-11-07 1988-05-20

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0352511A (en) * 1989-07-19 1991-03-06 Tokyo Electric Co Ltd Service interruption detection circuit

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