JPS61257093A - Automatic frequency control circuit - Google Patents

Abstract

PURPOSE:To obtain an AFC operation that follows the deviation of the locally generated frequency of a block down converter by controlling a tuning voltage so as to determine a white/black noise contained in the output from a detecting circuit and to equalize the number of peak white noises to the number of peak black noises. CONSTITUTION:Black and white peak detecting circuits 22 and 24 detect black and white level noise signals NB and NW, respectively, and pulse shaping circuits 23 and 25 shape noise signals NB and NW into pulses, respectively. Counters 28B and 28W count black and white peak noises, respectively. Field counter 27F generates an output at every 16 fields, and clears the counters 28B and 28W, and the output then obtained from a comparator 28C is hold by a sample hold circuit 28H. When more than 16 noise pulses in one field are applied from an OR gate 26 to a counter 27P, 2<3>-output from the counter 27P changes from H-L, this change is transmitted to the terminal S of a flip-flop 29F, the flip-flop 29F is set, an output terminal Q becomes H, Q becomes L, the output from the sample hold circuit 28H passes through a switch 32S via a relay 29R and is transmitted to a PLL circuit 31.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an automatic frequency control circuit used particularly in a local frequency stabilization circuit of a satellite broadcast receiver.

Conventional technology Conventional control means of this type include: (1) Stabilization by applying a PLL to the 20th Cal frequency; In this method, the 10th Cull frequency (LN
If the local value of H is shifted, IF cannot be maintained accurately at fi.

■ Also, in the method of comparing the 20th Cull frequency fJ2 with the crystal oscillation frequency using PLI, the 20th Cull frequency f,2 is determined by the PLL frequency division ratio, regardless of the drift of the 10th Cull frequency. The intermediate frequency fL shifts.

Problems to be Solved by the Invention In the conventional method, the local deviation of the LNH is not detected, so it cannot cope with the local deviation of the LNB, and manual adjustment is required. is detected and the local frequency of the second mixer is shifted to match the local frequency of the LNB, thereby automatically controlling the frequency.

Means for Solving the Problems The automatic frequency control circuit according to the present invention counts white peak noise and black peak noise in the detection output, shifts the local frequency of the second mixer so that the numbers of both become equal, and calculates the LN
According to the present invention, if the IF frequency is f and the normal input frequency is fx, then if the PLL system is used, the frequency division ratio is nx. It's decided. When f is shifted, the white peak and black peak noise increase or decrease, so this is detected and the local f, 2 of the second mixer is shifted by Δf so that both become equal. That is, by changing the frequency division ratio to nz+Δn, f! +Δ
Correspond to f. The equation below is for the upper local fi2-fx=fi case. When the local frequency of LNB shifts, f,
, = f, +Δf, so if fi2""f12+Δf, then f 12"x'"(flQ+Δf)-(fx+Δf
')=f.

Therefore, the IF frequency is always kept at a normal value.

Embodiment Fig. 1 shows the main part of the present invention, Fig. 2 A and B show examples of screens before and after implementing the present invention, and Fig. 3 shows a satellite broadcast incorporating the embodiment of the present invention. Overall configuration of receiver, 4th
The figures each show changes in signal waveforms when the present invention is implemented.

In Figure 3, 1 is a parabolic antenna that receives satellite broadcast radio waves, and 2 is a parabolic antenna that receives ultra-high frequency signals (for example, radio waves in the 12 GHz band or 4 GHz band) received by the parabolic antenna 1 in the 1G band (here, 950M) + E ~ 1450MHz. It is a low-noise converter (LNB) that converts radio waves into radio waves. Reference numeral 3 denotes a column of the parabolic antenna 1, and a mechanism for rotating the parabolic antenna 1 is attached when receiving radio waves from a plurality of satellites. 4 has good high frequency characteristics (,1G
) This is a cable that does not attenuate lz band signals. 1-4
is installed outdoors. Bean is a satellite receiver, IDU
(abbreviation for indoor unit). 6 is a tuner called a second mixer, which converts the signal of one channel among the IGlb band signals to an IF frequency (for example, 402.751vl-?, 51 oM) & ). 7 is an IF amplifier, and 8 is an FM broadband detector, which has good nearness characteristics over a band of 30 MHz or more, for example. Reference numeral 9 denotes an audio demodulation circuit, which performs PCM demodulation in the case of PCM and FM detection in the case of FM.

Reference numeral 14 denotes a circuit which controls the 20th cull so that the numbers of white peak noise signals and black peak noise signals are approximately equal, which is a feature of the present invention. Note that if this circuit 14 is simply a buffer amplifier, it will have the same configuration as a normal IDU. 11 is
A buffer 7 amplifier for outputting video and audio signals in the base frequency band; 1o is an audio demodulation circuit 9 and a control circuit 14;
This is a converter that converts the output of the RF signal into an RF signal output.

The RF specific output of this RF converter 10 is in the VHF band, and this is continued to the antenna input of a normal television receiver 13 via a VHF band cable 12 to obtain an image as shown in FIG. 2A. In the transmission system between 1 and 8, C/N deteriorates and L
When the local of NB2 shifts, a lot of noise N, either a white peak or a black peak, appears on the screen as shown in FIG. 2A.

If the circuit of the present invention is used, the above phenomenon can be realized by making the white and black peak noises almost equal as shown in FIG. 2B, thereby making it possible to compensate for the local deviation of LNB2.

The specific configuration of the control circuit 14 is shown in blocks in FIGS. 16 to 33. In FIG. 1, 16 is a pedestal clamp circuit, and the pedestal clamp signal is formed by circuit 18. 16 is a synchronous separation circuit, and its output is used for horizontal AF
The C circuit 17 is synchronized.

19 integrates the output of the synchronization separation circuit 1θ and performs vertical synchronization.
This is a pulse generation circuit (vertical synchronization) that generates pulses. The clamp pulse generating circuit 18 appropriately shapes and delays the output of the horizontal AFC circuit 17 to form a pedestal clamp pulse having a phase as shown in FIG. 4B. The output of the vertical synchronizing pulse generation circuit 19 and the output of the horizontal AFC circuit 17 are shown in Fig. 6 φ3.
As shown in FIG. 3, a pulse that is at a low (or high) level only during the Q period over the vertical retrace period (VBL) is formed by the counter gate 2°. This counter gate 20 has a counter,
It can be easily configured with flip-flops. This changes the pedestal clamp operation of the pedestal clamp circuit 15 to VB
This is to prohibit L and to stop the pulse counter 27P during VBL.

Figure 5 φ is a video signal seen with vertical synchronization, and t.

~t3 is the vertical retrace period, and the 3H width hatched part starting from tl of φ1 is the vertical synchronization pulse, and when this is integrated,
φ2 in FIG. 6 is obtained as the output of the vertical synchronization pulse generation circuit 19. In this manner, the signal shown in FIG. 4A is pedestally clamped by the pedestal clamp circuit 15 during the period from t3 to t0 in FIG. At this time, the color burst is often superimposed on the pedestal part, so when clamping,
Needless to say, so-called soft clamping is performed so as not to affect the burst signal. In FIGS. 4A and 4B, the pedestal level vP and the black level VB are selected to be equal for simplicity. Therefore, when the black level VB is clamped to a constant level, the detection output value becomes constant, and the white level VW also becomes constant.

Upper amplifier 21 is DC coupled. The next black peak detection circuit 22 detects a noise signal NB having a blacker level than the black level VB of FIG. 4A, and the pulse shaping circuit 23 converts the level and shapes it into a pulse.

In this case, the output of the pulse shaping circuit 23 is as shown in the fourth diagram. On the other hand, the white peak detection circuit 24 detects a noise signal Nw exceeding the white level vw in FIG.
Step 6 converts the level and shapes it into a pulse. The output of this pulse shaping circuit 25 is as shown in FIG. 4C. When the logical sum of C and D in FIG. 4 is formed by the OR gate 26, the OR gate 26
The output is shown in Figure 4E. 27P is a pulse counter,
As mentioned above, the OR gate 2 during the period t3 to to in FIG.
Count the output of 6 for each field. Pulse counter 2 completed P
When the flip-flop 29F and the flip-flop 29F are configured as shown in FIG. 1, the counter 27P counts only from t3 to to because φ3 is at a low level. As the counter 27P, for example, a TTL binary counter 5N74 LS9
3 are possible.

On the other hand, the field counter 27F counts the output of the counter gate 20, for example, 4096 fields (
The flip-flop 29F is configured to be reset by generating a pulse once every 1.1 minutes). 16 or more noise pulses in one field
When applied from the R gate 26 to the counter 27P, the output 25 of the counter 27P changes to HL, this change is transmitted to the S terminal of the flip-flop 29F, the flip-flop 29F is set, and the output terminal Q becomes H1◇ becomes L, and the output of sample hold circuit 28H becomes relay 2.
It is transmitted to switch 32S via 9R.

When the output terminal Q of flip-flop 29F is H, relay 2
9R connects the output of sample hold circuit 2BH to switch 3
Tell 23. The counter 27P is set for each field.
Since it is cleared between 70 and t3, there are 15 in 1 field.
When the noise pulse is less than 1, the counter 27P is not set and the output of the sample hold circuit 28H is
It is not transmitted to the PLL circuit 31 via 9R2328. Approximately every minute, one field majority or one part counter 27
Although there is a time when P is not set, there is no problem because the long-term average value is used for AFC operation.

As described above, it has been explained that when the C/N value deteriorates, the flip-flop 29F turns on the relay 29R and transmits the output of the sample and hold circuit 2BH to the PLL circuit 31.

Next, control of the 20th cull frequency f12 will be described. Counter 28B counts black peak noise, and counter 28W counts white peak noise.

Field counter 27F generates an output every 16 fields, clears counters 2BB and 28W, and
The output of the comparator 28C at this time is sampled and held by the circuit 2.
Hold at 8H. FIG. 6 shows an example of the comparator 28G.

The shift in local frequency and the increase or decrease in white peak noise and black peak noise change depending on the modulation polarity of the carrier wave and how the local frequency is selected depending on the video signal. Assuming that the LNH receives the C band, the local frequency f,1 of the LNH is fixed, and if it is shifted higher by Δf, the desired carrier wave f8 will also be f+Δf. 2n of second mixer 6
If the local frequency f12 does not change, the IF frequency fip becomes f it = f 62 (fx + Δf),
It becomes lower by Δf. Assume that black peak noise increases when Δf increases.

The screen at this time will be as shown in FIG. 2A, and the FM detection date and time output will be as shown in FIG. 4A. The counter 28B counts the output of the pulse shaping circuit 23 (FIG. 4D), and the counter 28W counts the output of the pulse shaping circuit 2.5 (FIG. 4C). This counter (temporarily 8-bit binary)
) 28B.

Subtractor 283°28 with 28W output using 8-pit signal line
Tell 4. Note that 281 and 282 are each a set of 8 AND gates. When (28B-28W) becomes 10 or more, the subtracter 283 outputs a negative pulse once, and the other subtracter 284
is configured to output a negative pulse once when (28W-28B) becomes 10 or more. flip flop 286
is set by the output of the subtractor 283. This reset of the flip-flop 286 is performed by the field counter 2.
This is done every 16 fields by the output of 7F. The flip-flop 286 is set by the output of the subtracter 284, and reset to 1 by the output of the field counter 27F.
This is done every 6 fields. 287 is a voltage level converter that generates a positive voltage when the Q of the flip-flop 285 is at a high level, and becomes zero potential when the Q of the flip-flop 285 is at a low level;
A voltage generator which generates a negative voltage when the Q of the flip-flop 286 is at a high level and a zero potential when the Q of the flip-flop 286 is at a low level; 289 is a three-value voltage generating circuit consisting of a diode resistor; When the output of the other level converter 288 is positive, the output is positive; when the output of the other level converter 288 is negative, the output is negative; and when the outputs of the level converters 287 and 288 are both zero, the output is zero. In the above explanation, since there is a lot of black peak noise, the value of the counter 28B becomes 10 or more larger than the value of the counter 2aW within 16 fields, and the value of the subtracter 28B increases by 10 or more than the value of the counter 2aW.
A negative pulse appears at the output of flip-flop 28
Set 6. When the Q of the flip-flop 286 goes high, the output of the NOR gate 28G goes low, cutting off the AND gates 281 and 282.

Also, when the Q of the flip-flop 285 becomes high level,
The output of the three-value voltage generator 289 becomes a positive potential, and the output of the field counter 2γF causes the flip-flop 285.
When resetting/sorting 286, this positive potential is sampled and held by the sample and hold circuit 28H. The output of this sample and hold circuit 28H changes every 16 fields (sometimes it does not), so it is passed through the low-pass filter 28H.
Increase the time constant of F to smooth. However, if it is made too large, the response will become slow. The output of low-pass filter 28F is transmitted to switch 328 via relay 29R. When the AFC is working, the movable part of the switch 32S is set to the auto side as shown in FIG. 1, so a positive voltage is transmitted to the PLL circuit 31. The operation of the PLL circuit 31 is such that, according to the designation of the channel selection designation circuit 33, a frequency obtained by local frequency division, such as converting an nCH carrier wave to an intermediate frequency fi, is set to the reference frequency 1? lf, (crystal oscillation frequency), and a loop is constructed so that the difference between the two becomes zero. However, when the output of the sample and hold circuit 28H is at a positive potential, the output of the field counter 27F causes 1.
If the output of the sample hold circuit 2BH is read every six fields and the frequency division ratio is increased by Δ, the local frequency f12 will be increased by ΔF due to the operation of the PLL circuit 31. Even if the local frequency f,2 increases by ΔF, within 16 fields, the counters 2BB and 2
When the difference of 8W becomes 10 or more, the local frequency f,2 is further increased by ΔF as described above.

If this is repeated, when yxΔF (y is an integer) approaches Δf, neither the subtracters 283 nor 284 will generate an output. At this time, the IF frequency is close to the normal value. When there is a lot of white peak noise, contrary to the above, the value of the counter 28W is larger, so the flip-flop 286 is set with the output of the subtracter 284, and a negative voltage is applied to the PLL circuit 31.
, the branching ratio is reduced by Δ, and the local frequency f12 is lowered by ΔF. When the IF frequency f(r approaches the normal value, the flip-flop 286 is no longer set. Therefore, f, · is set very close to the normal value, and if it deviates from the base run, it will be pulled back by the above operation. .

When switch 32S in Fig. 1 is set to the manual side,
A positive or negative voltage is output from the local fine adjustment device 32F to the PLL.
The signal is transmitted to the circuit 31, and the frequency division ratio can be finely adjusted manually. In the case of manual fine adjustment, it is not possible to follow the positional deviation of the LNB.

In general, a PLL synthesizer one-type tuner (2nd mixer 6 and 2nd local oscillator 30 in Figure 1) determines the local frequency compared to a crystal oscillator, so AFC is not required, but satellite broadcast reception When frequency conversion is performed all at once in the first stage, a circuit is required to compensate for local variations in the first stage, and the present invention is one effective example of this. FIG. 2B and FIG. 4B show the improvement of the screen signal waveform due to the effects of the present invention.

Effects of the Invention As described above, according to the present invention, a circuit is provided for determining the amount of white peak noise and black peak noise in the output of the detection circuit,
By controlling the tuning voltage supplied to the local oscillation circuit so that the numbers of the white peak noise and black peak noise are equal, automatic frequency control is performed to follow the deviation of the local frequency of the block down converter. It can be used, and its practical effect is extremely good.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of an automatic frequency control circuit according to an embodiment of the present invention, and FIGS. 2A and 2B are screen examples for explaining the operation of the present invention compared with before implementing the present invention. 3 is a block diagram of a satellite broadcast receiving system to which the present invention is applied; FIGS. 4A and E are waveform diagrams for explaining the operation of the device of the present invention; and FIG. 6 is a diagram of the operation of the device of the present invention. A time chart for explanation and FIG. 6 is a block diagram of further essential parts of the apparatus of the present invention. 22... Black peak detection circuit, 23...
Pulse shaping circuit, 24...White peak detection circuit,
25...Pulse shaping circuit, 28B...
Counter, 28W...Counter, 28C・River・
・Comparator, 28H-o...°sample hold circuit, 3
1...PLL circuit. Name of agent: Patent attorney Toshio Nakao, 1st person, 2nd person
Figure N Figure 4

Claims (2)

[Claims] (1) Receive the output of a block down converter that collectively converts the frequency of multiple FM TV broadcast waves within a certain frequency band sent from a broadcasting satellite, and convert one of the TV broadcasts output from the block down converter. a tuner that selects a wave, a detection circuit that amplifies and detects the output of this tuner, a judgment circuit that judges the amount of white peak and black peak noise in the output of this detection circuit, and an output of this judgment circuit that detects the output of the tuner. a control circuit for controlling a tuning voltage supplied to the local oscillation circuit in the block down converter, and a control circuit for controlling the white peak and black peak in the output of the detection circuit, which increases or decreases in response to frequency changes of the local oscillation circuit in the block down converter. An automatic frequency control circuit characterized by controlling a tuning voltage supplied to the local oscillation circuit so that the number of noises is approximately equal. (2) A crystal oscillator circuit and a PLL circuit constitute a circuit that keeps the output frequency of the tuner constant, and when the number of white peak and black peak noise exceeds a certain number, the number of white peak and black peak noise pulses is Claim 1 characterized in that the equalizing circuit is operated.
The automatic frequency control circuit described in section.