JPS61255593A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To initialize the data of a memory without making complicate a circuit construction by providing a switching element in a memory cell and turning on and off by a control signal to initialize the memory. CONSTITUTION:There is provided a switching element 8 in a memory cell formed by the first and the second inverters 1, 2. When the element 8 is turned on by a control signal or the like from a power on clear circuit or the like outputting on the leading of the power source, an initialization of the memory cell is easily carried out through the earth connected element 8 without turning off the first and a second switching elements. In this manner, the data of the memory can be easily and effectively initialized without making complicate a circuit construction.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a rewritable semiconductor memory device (hereinafter referred to as RAM).
(referred to as ).

[Summary of the invention]

In a RAM consisting of a flip-flop constituted by a pair of inverters, this invention provides a switching element between the output of one inverter and a power supply terminal or a ground terminal, and opens and closes it using a control signal, thereby creating a complex circuit. This allows the data in the memory to be easily initialized without using it.

[Conventional technology]

Conventional RAM consists of a flip-flop consisting of a pair of inverters as shown in FIGS. 2 and 3, and a bit of data stored in the flip-flop in response to a word line signal.
It is obtained by arranging a plurality of memory cells each including a switching element for outputting to the bitT line.

[Problem that the invention seeks to solve]

However, when trying to initialize the contents of conventional RAM at power-up, the memory cells are bit-blocked by the word line.
, it is necessary to open bit lines one by one and set their contents, and the circuit for this is complicated, and in order to initialize all the necessary memory cells, the address must change accordingly. This has the drawback of requiring time for this purpose.

SUMMARY OF THE INVENTION In order to solve these conventional drawbacks, it is an object of the present invention to easily initialize a memory by providing a switching element in a memory cell and opening and closing it using a control signal.

[Means for solving problems]

In order to solve the above problems, the present invention newly provides a switching element between one output terminal of an inverter constituting a flip-flop in a conventional memory cell and a power supply or ground terminal, and connects its gate to The configuration is such that it is connected to a separate control circuit, making it easy to initialize the RAM.

[Effect]

It is clear that in the RAM configured as described above, the memory can be easily initialized by applying a control signal to the gate of the newly added switching element so as to turn it on. When used as a normal RAM, it is sufficient to apply a control signal to turn off the switching element.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows a first embodiment of the present invention, in which a switching element is connected between the output of one of the first and second input signal inverters (inverters) 1.2 constituting a flip-flop and the ground terminal. 8 is provided, and is opened and closed by a control signal applied to a control signal input terminal 9. The control signal includes, for example, the output of a circuit (power-on clear circuit) that outputs a pulse when the power is turned on. Switching element 8 is connected to inverter 2
It is also possible to initialize the memory cell to the opposite value by connecting it to the output of .

FIG. 4 and FIG. 5 show the second and third diagrams of this invention, respectively.
This is an example. In FIGS. 4 and 5, a load transistor may be used as the resistance means. In addition, Fig. 6 (a
) described the first embodiment of this invention as a two-layer metal complementary MIS.
The pattern diagram designed with transistors, Figure 6(b), is
FIG. 6 is a sectional view taken along line AA' in FIG. 6(a).

〔Effect of the invention〕

As explained above, this invention initializes the memory by opening and closing a new switching element in the memory cell, which eliminates the need for a complicated circuit and allows the memory to be initialized easily in a short time. It has the effect of being able to do the following.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention configured with complementary MIS transistors, FIGS. 2 and 3 are configuration diagrams of conventional memory cells, and FIG. 4 is a circuit diagram of a first embodiment of the present invention configured with complementary MIS transistors. FIG. 5 is a circuit diagram of a second embodiment of the present invention constituted by resistance means, and FIG. 5 is a circuit diagram of a third embodiment of the invention in which only the switching element 8 in FIG. 4 is replaced with a P-channel MIS transistor. , FIG. 6(a) is a pattern diagram of the first embodiment of the present invention designed using a two-layer metal complementary MIS transistor, and FIG. 6(b) is a pattern diagram of the first embodiment of the present invention.
It is a sectional view along the AA' line of a). 1-...-First input signal inversion device 2--Second input signal inversion device 3--B i is connected to line 4--Bit line 5--Word line 6- ---1st switching element'l---2nd
Switching elements 8--Third switching elements 9--111 Control signal input terminals Applicant: Seiko Electronics Co., Ltd. Ushibashi Diagram 2 of the memory purchase circuit diagram

Claims (4)

[Claims] (1) first and second whose outputs are connected to each other's inputs;
an input signal inversion device, a first switching element connected between the output of the first input signal inversion device and the bit line and opened and closed by the word line, and an output of the second input signal inversion device. a second switching element connected between the @bit@ line and opened/closed by the word line;
A semiconductor memory device comprising a third switching element connected between an input signal inverter and a power supply terminal or a ground terminal and opened and closed by a control signal. (2) The first and second input signal inversion devices are complementary type M
The first and second switching elements are N-channel MIS transistors, and the third switching element is a P-channel MIS transistor.
The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a transistor. (3) The first and second input signal inversion devices are constituted by an N-channel MIS transistor and a resistance means, and the first, second, and third switching elements are constituted by an N-channel MIS transistor.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is an S transistor. (4) The first and second input signal inversion devices are constituted by an N-channel MIS transistor and a resistance means, the first and second switching elements are constituted by an N-channel MIS transistor, and the third switching element is constituted by an N-channel MIS transistor. P
2. The semiconductor memory device according to claim 1, comprising a channel MIS transistor.