JPS61255115A - Binary transversal filter - Google Patents

Abstract

PURPOSE:To obtain a filter with stable operation and less power consumption by providing M-stage of shift registers reading an input data string in a speed being N times of the bit repetition, a weighting means with respect to the output of the shift registers and an adder means. CONSTITUTION:The M-stage shift registers 4 reading an input data string 100 in a speed being N times of the bit repetition, the weighting circuits 9 controlling the polarity of a constant in binary representation by the output of each stage and the digital adder circuit 10, and each weighting circuit 9 outputs a code of each bit of constant circuit 11 as it is when an input 102 in logical '0' and outputs a complement when logical '1'. The arithmetic time of each adder of the circuit 10 is selected to be finished within one period of the clock signal so as to attain the arithmetic processing in real time. Since all the weighted outputs of each tap are added by the digital processing, stable waveform shaping with high accuracy is attained. Further, each constituting circuit is realized by gate arrays and the power consumption is less.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a binary transversal filter, and in particular to a binary transversal filter that is used for waveform shaping of digital signals and has stable operation and low power consumption.
Regarding filters.

[Prior art]

Waveform shaping using a binary transversal filter is performed by approximating a desired impulse response with a staircase waveform, and passing the staircase waveform through a low-pass filter for smoothing. Its basic circuit configuration is as shown in FIG.
The output is input to an M-stage shift register l with Q and Q outputs that operates at a speed of N times 01 (an integer of N≧2), and the output of each stage of this shift register is weighted by a resistor before being converted to an analog signal. It is configured such that an adder circuit (SUM) 2 synthesizes the signals, and a sampling frequency (operating frequency of the shift register 1) component is removed by a low-pass filter (LPF) 3. In this configuration.

In order to improve the accuracy of waveform shaping, it is necessary to finely adjust the resistor of each tap, and there are also drawbacks such as being directly affected by amplitude fluctuations of the shift register output. Read-only memory (ROM) and D/A rounding eliminate this drawback.
The method shown in FIGS. 6 and 7 using a converter is published in the Institute of Electronics and Communication Engineers technical research report C383-43, P, 15-P.
22 has been proposed.

In Figure 6, a 2M word table is prepared in the ROM 5 with M-bit addresses corresponding to the number of output taps of the shift register, and bits are assigned to each corresponding to the output pattern of the M-stage shift register 4, which has only Q outputs. The configuration is such that a digital value is read from a ROM 5 and converted into an analog signal by a D/A converter 6. FIG. 7 shows that N series (N-4 in the figure) are operated in parallel in order to make the operating speed of the shift register the same as the data signal, and the clock signal for driving the shift register 7 of L stages in each series is Set the phase to 2π/
It is configured to drive at a speed that is isometrically KN times faster by shifting it by N.

In this method, the ROMg and the D/A converter 6 are each
However, the capacity of the ROMg can be made extremely small compared to the case shown in FIG.

[Problems to be solved by the invention]

However, the method shown in FIG. 6 described above has the disadvantage that if the number of stages of the shift register is increased in order to improve accuracy, the size of the ROM 5 becomes enormous, power consumption becomes large, and actual fiK is difficult. Also, the method shown in Fig. 7 is ``D/A''.
Since a plurality of converters are used and their outputs are summed in analog form, there are problems with stability and high power consumption. It is an object of the present invention to provide a binary transversal filter that is stable, consumes little power, and is easy to implement, by eliminating the drawbacks of the above-mentioned conventional method by only processing K.

[Means to solve the problem]

The monkey fill consists of an M-stage shift register that reads an input data string at a rate of H times (an integer of N≧2) the input data string, and a predetermined binary value for the output of each stage of this shift register. weighting means that corresponds to the positive and negative polarities of the M constants displayed; addition means that includes at least one adder and adds the M outputs of the weighting means; and converting the output of the addition means into an analog signal. Do D/
The D/A converter includes an A converter and a low-pass filter connected to the output of the D/A converter. Moreover, the binary transpersal filter of the second invention processes an input data string by 2π/N(N
≧2 integer) N shift registers each having L stages are read at N different phases, and the output of each stage of these shift registers is converted to the positive and negative polarities of NL constants in binary representation determined in advance. a first adding means for adding the outputs of the L weighting means of each of the shift registers, and a first adding means for adding the N outputs of the first adding means at a rate N times the bit repetition rate. a D/A converter that converts the output of the second adder into an analog signal; and a nine low-pass filter connected to the output of the D/A converter. It is composed of:

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of the first embodiment of the present invention, which includes an M-stage shift register 4 that reads an input data string 100 at a speed N times the bit repetition rate, and a binary output from each stage of the shift register 4. A weighting circuit 9 that controls the positive and negative polarities of display constants, a digital addition circuit 10 that adds the outputs of each weighting circuit 9, a D/A converter 6 that converts the output into an analog signal, and a low-pass filter 3. It is made up of.

Each weighting circuit 9 includes a constant circuit 11 that stores the weighting coefficient of each tap in natural binary representation of bits (in case of a negative value, representation in two's complement), and a constant circuit 11' that stores one bit of #0''. , EX-OR connected to constant circuit 11
Circuit 12. If the input 102 from the shift register 4 is "Om", the EX-OR circuit 12' connected to the constant circuit 11' outputs the sign of each bit of the constant circuit 11, and the input 102 becomes m12. In the case of , the sign of each bit is inverted and a 1's complement number is output.
The circuit 12' outputs m1# when the input 102 is #1, and adds the lowest bit "l" necessary for the constant subtraction process of the constant circuit 11 to the digital addition circuit 10. The digital adder circuit 10 is composed of a multi-stage adder group and a register group provided between them, and the adders 13 are first-stage adders and registers that add the outputs of the four weighting circuits 9, respectively. 14 is a shift register for temporarily storing the output; adder 15 and register 16 are a second stage adder and shift register for further adding the output of register 14; adder 17 and register 1;
8 is an adder and a shift register that further adds the output of the register 16. The calculation time of each adder is selected so as to be completed within one cycle of the clock signal that operates the shift register 4, and the adder is configured to perform calculation processing in real time. According to this configuration, since all the weighted outputs of the taps are added together by digital processing, stable and accurate waveform shaping can be performed. Further, all of these component circuits can be realized by a gate array, which has the advantage of reducing power consumption.

FIG. 2 is a block diagram of a second embodiment of the present invention. In the circuit of FIG. It is composed of Each selector circuit 19 prepares a constant circuit 20 with an added value of weighting coefficients corresponding to 16 possible combinations of the output patterns of the four stages of the shift register 4 as a constant, and selects the addition value according to the output patterns of the four taps. The transistor switching circuit 21 is configured to selectively output one of the transistors. The rest is the same as in the case of FIG. 1, and all the circuits including the selector circuit can be configured as a gate array, and the same effects as in FIG. 1 can be obtained.

FIG. 3 is a block diagram of a third embodiment of the present invention, in which the selector circuit 19, second stage adder 15, and register 16 in FIG. 2 are constructed by a ROM 22.

According to this configuration, the capacity of the ROM can be made relatively small, and its power consumption is not so large, so it is easy to implement.
Stable operation is achieved because everything is done digitally.

FIG. 4 is a block diagram of a fourth embodiment of the present invention, which is an example of a case where four columns of shift registers are connected in parallel and operated. Similar to the conventional example shown in FIG. 7 described above, the input data string 100 is read into the L-stage shift register 7 using clock signals having different phases by π/2, and the digital output corresponding to the output pattern of each shift register is output from the ROM 8. Read it and load it into the register 23. The contents of the register 23 are read out using a clock pulse 103 that is four times the clock frequency of the data signal, and are added by an adder 24.
It is outputted via a converter 6 and a low-pass filter 3. According to this configuration, a highly accurate binary transversal filter can be realized using only digital processing without performing analog addition.

In the embodiment shown in FIG. 1 described above, the constant circuit lIK stores constants in natural binary representation, but
It goes without saying that a similar configuration is possible by storing the data in decimal format (polarity display), controlling the polarity bit using the input 102 from the shift register, and calculating 2's complement for negative numbers. Also, in the embodiment of FIG. 4, R
It goes without saying that OM8 can be constructed from a weighting circuit and an adder circuit or a selector circuit similar to those shown in FIGS. 1 and 2.

〔Effect of the invention〕

As explained in detail above, according to the binary transversal filter of the present invention, all arithmetic processing is done digitally, and most of the circuits are constructed from gate arrays without using a large-capacity OM. As a result, power consumption is low, operation is stable, and waveform shaping can be performed with high precision.

[Brief explanation of drawings]

1st. 42 is a block diagram of the second embodiment of the present invention, FIG. 3 is a block diagram of the third embodiment of the present invention, and FIG. A block diagram of the fourth embodiment of the invention, FIG. 5 is a basic configuration diagram of a binary transversal filter, and FIGS. 6 and 7 are a block diagram of a binary transversal filter using a conventional ROM.
FIG. 2 is a block diagram of a filter. 1.4.7...Shift register, 2...
・Analog addition circuit, 3...Low pass filter, 5
．． 8. 22...ROM, 6...L
) 7 person converter, 9... weighting times $s lo
...Digital addition circuit, 1, j, 11
．． '20...Constant circuit, 12.12'...
...EX-OR circuit. 13.15, 17.24...Adder, 14
．． 16°18.23...Register% 19.
...Selector circuit, 21...Transistor switching circuit・1. ;, -゛V-1 Nail 7゜7 Conflict 4 @ Mine Yu Interview 6 Fig.

Claims (7)

[Claims] (1) Input data string is N times its bit repetition (N≧
an M-stage shift register that reads at a speed of (an integer of 2);
weighting means for making the outputs of each stage of the shift register correspond to the positive and negative polarities of M constants in predetermined binary representation; and at least one adder, which adds the M outputs of the weighting means. A D/A converter converts the output of the adder into an analog signal, and a low-pass filter connected to the output of the D/A converter. Binary transversal filter. (2) The adding means includes a plurality of partial adding means for dividing the M outputs of the weighting means into a plurality of sets and adding the outputs in each divided set, and further adding the outputs of these partial adding means. 2. The binary transversal filter according to claim 1, further comprising at least one adder. (3) The binary transversal filter according to claim 2, wherein the weighting means and the partial addition means are comprised of read-only memories. (4) N shift registers each having L stages that read the input data string at the same speed as the bit repetition and N phases different from each other by 2π/N (an integer of N≧2), and each stage of these shift registers. weighting means for making the outputs correspond to the positive and negative polarities of NL constants in predetermined binary representation; and first addition means for adding the outputs of the L weighting means of each of the shift registers;
a second addition means that samples and adds the N outputs of the first addition means at a rate N times the bit repetition; and a D/A that converts the output of the second addition means into an analog signal. A binary transversal filter comprising a converter and a low-pass filter connected to the output of the D/A converter. (5) The binary transversal filter according to claim 4, wherein the weighting means and the first addition means are comprised of read-only memories. (6) The first addition means includes a plurality of partial addition means for dividing the L outputs of the weighting means into a plurality of sets and adding the outputs in each divided set, and the outputs of these partial addition means. 5. The binary transversal filter according to claim 4, further comprising at least one adder for adding . (7) The binary transversal filter according to claim 6, wherein the weighting means and the partial addition means are comprised of read-only memories.