RU1786638C - Digital nonrecursive filter - Google Patents

Description

synchronization of the delay unit and the second, third and fourth memory registers, the second divider, the first input of which is connected to the output of the pulse counter, the second input is connected to the second inputs of the first divider and the comparison unit and is the input of the division coefficient, the third adder, the output of which is digital non-recursive filter output, as well as the first, second, third and fourth computing units, the first inputs of which are connected to the output of the second divider, the second inputs are connected respectively to the output of the first sum Mathor, the second memory register, the third memory register and the fourth memory register, and the outputs are connected to the corresponding inputs of the third adder ..

The principle of operation of the proposed digital non-recursive filter is based on preliminary grouping of samples carried out using the second adder and the first memory register. Subsequent processing of the digital signal is reduced to digital filtering followed by quadratic interpolation over four nodes, the preliminary grouping of the reports. It has the same effect as increasing the number of links in the prototype filter, and changing the number of pre-grouped samples (Nrp) allows electronic by controlling the memory interval of the proposed device, in addition, in the proposed device during the operation of digital filtering in the block of multipliers, weight blocks are used that have a common input for Ani coefficient multiplying (weighting for each individual unit), this is provided by virtue of the shape of the weighting function in the process of digital i FIR) filter. The operation of quadratic interpolation used in the digital non-recursive filter allows to restore the repetition rate of the signal samples to the original (i.e., that which was at the input), and in order to increase the accuracy, quadratic interpolation is performed at four nodal points using the second, the third, fourth memory registers, the second divider, the first, second, third and fourth computational units and the third adder, the pulse counter and the comparison unit are used to synchronize the circulating non-recursive filter.

The invention is illustrated by drawings, in which Fig. 1 shows a block diagram of a digital non-recursive filter, Fig. 2 shows a block diagram of a first adder, Fig. 3 shows

structural diagram of the third adder: figure 4 shows the diagrams of the digital non-recursive filter. Multi-bit bonds are denoted by double lines, single-bit bonds are denoted by single lines. 5 Digital non-recursive filter (Fig. 1) contains:

1 is a delay unit consisting of memory registers 1-1, ..., 1-N;

2 - block of multipliers, consisting of weight 0 output blocks 2-1, .. „2-N;

3 - the first adder;

4 - second adder; . 5 - first memory register ;.

6 - the first divider; 5 7 - second memory register;

8 is a third memory register;

9 is a fourth memory register;

10 - pulse counter;

11 is a comparison unit; 012 - the second divider,

13 - the first computing unit;

14 - second computing unit; 15th third computing unit; 16 - the fourth computing unit; 5 17 - the third adder.

The first adder (figure 2) contains cascade-connected two-input summato.

Ry. -, ...:. . .

The third adder (Fig.Z) contains three 0 two-input room.

In Fig. 4, the following designations are adopted:, neither: -. , :: - h-V;

x (i) -digit signal supplied to the input of a digital non-recursive filter; 5 s-sync signals supplied by X-ray digital non-recursive filter input; 5РГ - signals at the output of the first memory register 5; - .. - ;; - ..

11BS - signals at the output of the block compared to 0; 11 ;.

y (i) - signals at the output of the first adder 3.

The digital non-recursive filter contains the first memory register 5, serially connected 4 delay block 1, multiplier block 2, the second input of which is the input of the multiplication coefficients (filter weight function), and: the first adder 3, as well as sequentially connected to the second 7, third 8 and fourth 5th 9 memory registers, as well as a second adder 4, the first input of which is; information input of a digital non-recursive filter, and the output is connected to the information input of the first 5 memory registers, the first divider 6, the first input. which is connected to the output of the first 5 memory register and to the second input of the second 4 adder, and the output is connected to the information input of the delay unit, sequentially connected counter 10 pulses, the information input of which is connected to the synchronization input of the first memory register and is clockwise a digital non-recursive filter and a comparison unit 11, the output of which is reduced with the input to the zero counter setting: pulses 10 and the first 5 memory registers and with the synchronization inputs of the delay unit and the second 7; the third 8, and the fourth 9 registers of memory, the second is a 12 divider, the first input of which is connected to the outputs of the pulse counter 10, the second input is connected to the BTOL inputs of the first 6 divider and block 11 of the comparison and has inputs k6d: Division factor (grouping), the third 17 sou mmor; the output of which is; output of a digital non-recursive RGB filter, as well as the first 13, second 14, third 15. and the fourth .16 computing units, the first inputs of which are connected.-f with the output of the second 12 divider; the second ixoflbi are connected according to the output of the first 3 adder, the second 7, the third 8 and the fourth 9 register, memory, and the outputs are connected to the corresponding inputs of the third 17 adder, - -.; - -: /; / 1 1 .. ,: -. :: - - ..,:.-....,

The unit of multipliers 2 consists of weight units 2-1, ..., 2-N, which are implemented on integrated digital microchips of permanent storage devices (ROM). In this case, the first Weight Unit 2-1 is the first part; address inputs to the corresponding ROM chip, the second is the control input of the weight block 2-i is the second part of the address inputs of this ROM chip, and the output of the weight block 2-1 are the information outputs of this ROM chip, the codes recorded in The ROMs of the block of multipliers 2 are determined by the user in accordance with the required weight function, and the truth table of the ROMs is calculated according to the required weight functions, and the truth table of the ROMs is calculated according to the expression:: ..: :: -. ...., l -.; :; (birA2.A1 Y (A2,))) U. (1) where A1 is the number supplied to the first part of the (younger) address inputs of the ROM (the first input of the weight unit 2-I); A2 is the number supplied to the second part of the (senior) address inputs of the ROM (second input of the weight unit 2-I); P (A1) is the bit depth of the number (binary) supplied to the first input of the weight block 2-I; the value of the recorded weight, determined by the number supplied to the second input of the weight block 2-I, moreover, ,,,, N; N is the number of memory registers 1-k; ent is the operation of rounding to an integer; V -.

logical OR operations,. - arithmetic multiplication operation; D number

removed from the information, ROM output (output of the weight unit 2-1); 5 Example calculation of the truth table.

Suppose the bit number is fed to the first input of the weight block 2-1. P (A1) 8, bit 4 of the number fed to the second input b / d weight, block 2-P P (A2) 5, then 10 yes according to formula (1) table: the truths are calculated as follows about pS30f :: ±:: ; ;

:; In the second one, and all is in sixteen - in the form of sixteen digits, for example, the values are L1, A2 ;; - A is set by the user. in G according to the requirements of the required r .. ..; digital non-recursive filter. ; , The first shredder; b is not constantly implemented; nom apo; by me, the current line of yours and 0 is a controlled arithmetic:

: tic divisors, with the first part

 ; of the address inputs of the ROM (first; input of the first divider 6) the input information (number) is supplied, and the second: Part of the address inputs 25 of the ROM (second input of the divider b) is supplied ..: equal information (second number) and s. the information outputs of the ROM are removed; / exit inform acy; moreover, the table is used:; the obscurity of greeting with the expression: 30.-.- -i. - (2) ..;.

::: A1 - h islb,; P: 6yav aGemoe on the first part of the address inputs of the ROM (the first input is on;; divider b); Yauu ;; :; g d- :::; D:. .; :: A2 - chys lb fed to itbpyto part of 35 address inputs of ROM (second input of the first

divider .6); : -; $ -i:; .--. ; ent - one walkie-talkie rounding to the whole

: l. -..-/ 1:: -.;

  .. - operation arifmetychesko whom is clever40 WOMEN; : ;; ::%.;.:; D; /: ..; :/ 1 .- /:: . :; . ;

   p -; the number taken from the information output of the ROM (the output of the first divider

  fi -..-.- - ... .... ... .- -. - -. : .fy - V V VV: .- - ..-....:: .-. ; ....;, Calculation of the truth table of realizations - 45 liters is available for the above niDH

;;: Dm yo U; :; ; Used second divider. 12 and computing units 13-16 are implemented on integrated digital ROM chips and 50 serve in the described digital non-recursive filter for calculating special functions of the form:; .

 (A1, A2), .. (3). where A 1 is the number supplied to the first part of 55 address inputs of the ROM (the first input of the block

ROM) ::;:. . . :

A24 is a number; supplied to the second part of the address inputs of the ROM (second input of the ROM block) ;.

f is the symbol of a special function;

D is the number taken from the information output of the ROM) the output of the ROM block).

The described digital non-recursive filter uses ROM blocks in which the following "odes: second divider 12 are recorded.

 (A1 / A2) computing unit 13

(A1.A2. (A2-1) / 4): computing unit 14.

.. (A1.A2. (A2-5) / 4j,. Computing unit 15

. (A1. (A2-1). (A2 + 4) / 4), computing unit 16

D-ent (A1.A2. (A2-1) / 4), .... (8) where A1 is the number supplied to the first input of the computing unit; ;. . -A2-. Number supplied to the second input of the computing unit; ....:

ent-- operation rounds to an integer; .

....; - D is the number taken from the output of the computing unit,. .... v. : Bit At, A2, D is determined by the bit size of the input / data supplied to the first input of the second Adder 4 and

Bit of control data supplied to the second input of Comparison Unit 11.. All other blocks of the digital non-recursive filter are implemented on. integrated digital circuits of the K155 and K555 series in a standard inclusion. . The device operates as follows. A discrete digital signal x (i) is supplied to the input of the device (Fig. 4), each counting of which is accompanied by a clock pulse with (Fig. 4). Input signal

to the first input of the second adder 4, which together with the first memory register 5 is accumulatively summed; incoming signal in digital form. The process of accumulating summation consists in sequentially summing up a series of samples, followed by zeroing and repeating the indicated procedure (diagram 5РГ in Fig. 4). amount

of grouped samples, Nrp codes are set, which is supplied to the second input of comparator 11. Pulse counter 10, together with comparator 11, forms a counter with a variable division coefficient of the input clock pulses c, and at the output of comparator 11, BS 11 is generated (Fig. 4 ) When the 1MGy code matches the current code at the output of counter 10

(Fig. 4), which changes its state by +1 with the arrival of each clock pulse, the pulse from the output of comparator 11 resets counter 10 and the first memory register 5 (diagram 5 of the WP in Fig. 4). The first divisor b fulfills the function of the nomination signa7} a (code) supplied to its first input, the normalizing value being the code of the quantity Nrp arriving at. second entrance

10 of the first divider 6, The operation of the first divider 6 is described by formula (2). From the output of the first divider 6, the signal is fed to the information input of the delay unit T and is recorded in it by the pulse 11BS (Fig. 4)

15 of the output of comparator 11. The delay unit is a chain of series-connected memory registers 1-i, the first input of which is informational, and the second input is a synchronized move. The pulses from the output of comparator 11 to the sync input of the delay unit provide information from the input of each memory register 1-i to its output, due to which

25 provides simultaneous receipt

SEQUENCE OF ARRANGEMENT DETAILS FOR A FRIEND FOR ONE TIME OF SAMPLES.

Each of the delayed samples of dominoz:

 on the corresponding song factor in the weight blocks,, .2-j. block of multipliers 2. Received delayed bcounts, multiplied by the corresponding weighting factors are summed in the first adder 3. Thus, for a non-recursive filter, the signal arriving at.

, the input of register 1-2 of delay unit 1 and the signal taken from the output of the first adder 3 are related by the expression:

yi (nT)

;

bi x1 ((p-) T),

(9)

where x1 (pT) is the signal supplied to the input of registers 1-2 of delay unit 1, bj is the value of the weight coefficients recorded in the corresponding weight units 2-j;

y1 (PT) is the signal at the output of the first adder 3.. ....

The weight function of a non-recursive filter is described by the expression:

V (i

Fri) i t

bi.1 ((n- |) .T),

55f 1. (10) where 1 (n-1).

(0, n ±

x1 (PT) is the signal at the output of the grouping register 1-1, obtained by the corpse (11)

(12)

Nrp sampling of the samples of the input signal (x (nT) j (arriving at the first input of the second adder 4), followed by normalization in the first divider 6, and fixing in the group register .1-1, described by the following expression:

Nrp - 1 I-: -

  x1 (nT) x (Nrp.iH-k); or

 .- k o ..:;. ..-

: .- Nrp-v -::: -:;:

x1 ((n-1) T Ј x ((Nrp (n-l) + k) T,

y; .. ;;.; -.,.; ..:. ... k about.:. . :. .;.;.,. ; -. l; :: - ...: ,,, where Nrp is the grouped number of input samples (set at the second input of the comparison block 11);: ;; ;; /;.,/. - ..;.-....

 I.-number of memory register 1-1 of delay unit 1, ...-.: .., l; - .; WITH:: . -:. -. ; S is the weight coefficient; : - :. ::, -g

Then, substituting (12) and (9) we obtain:; .- ,; N Nrp -I -.; .- ,; :.:; -:.; -.

..:. Yl (nT) Ј bi (2 x ((NrP (n-l) + K) Tfe

:. ; ,. 1 . ,. to - o .; :.,:, .... (P)

 By take off the physical. formulas (13) can be as follows. ; j; -.;: -;

Let .m. , then the formula is 25 (1 3) stanbv ygs of the same form: mule (9), the memory interval q igfrg O vbgr of the non-recursive filter will be N, where N is the number of memory registers of the 1st i-digit non-recursive filter , and the Leb 30 function will be described by formula (10). Suppose then the formula (13) will accept id;:;: -; ; y - ::; ; :: 0 ;.

/ o ukpt) | b, fi -iff: 1 i3fi; ti4

and the weight function will be described as a-: wife m:, :: l- -.:i-i: y ..; .:. ::: ,,. . V.:.

V (nT) | b, lp (n-l) T) +1 ((2 (ri-l) +1) T),; 40

 . fi, -. : -:: f ..:: -:. - where 1 (2 (n-l) T) y ;;;; V: h L: G /

-.; ..:.: - V. (o, n /). ; V; :; -; rV ;;; -; :: / lv-; g;

This means that the length, weight 45 of the function V (nT) and, at least, the interval of memory of the non-recurrent filter increased by two times and became equal to 2.N, where N is the number of memory registers 1- i of the delay block T. Reasoning is similar, we get that 50 for some arbitrary value Nrp-. the memory interval of the described digital non-recursive filter will be equal to:

.N, (16) where L is the memory interval of the digital non-recursive filter; ..

N is the number of memory registers;

Nrp is the number of grouped samples.

Thus, a preliminary grouping of Nrp samples was carried out in accordance with formula (11) and only then

35

55

having carried out the digital filtering process in accordance with formula (9), it is possible to obtain the structure of a digital non-recursive filter with the ability to vary the length of its weight function and, therefore, the memory interval over a wide range without additional hardware (and energy) costs, and thanks to the use of controlled 2-j weight units (multipliers) during the digital filtering operation, it is possible to discretely change (select) the shape of the weight function, (input Ф in FIG. 1 - shows the smoothing number function). As a result of preliminary grouping of the samples of the input signal, the frequency of following the samples from the output of the first adder 3, the ratio to the repetition rate of the input samples decreased by a factor of Nlrp, therefore, to restore the result. of the sampling rate-to-gain during the digital recursive filter, it is necessary to carry out the interpolation process. In the described digital non-recursive filter, there is interpolation-. ocyaiectB jieTCflrd using the second share-, l. 12, computing blocks 13-16, five registers 7-8, and a third adder 17. Quadratic interpolation is performed at four nodal points y (i); (Fig. 4), the first, second and third nodal points being used for calculation of the first polynomial, and the second third and fourth points are used to calculate the second polynomial. After calculating the linear 6c at the indicated nodal points, their arithmetic average is calculated by the formula .; -i;: i: /; - -t::; V: -; : - v- :::: -: -:

l3 (F51 + P2) / 2,

(17).

wherein the polynomial P is used to calculate intermediate values between the second and third nodal points. This procedure improves the accuracy of the interpolation; in comparison: with quadratic interpolation at three nodal points,.: .. In general, for the case of quadratic interpolation at the first three points (see I. Bronstein, K. A. Semendev, Mathematics Handbook, M. : Science, 1981, p.663) we have:,.: - -.-.-, -. . , -.:. -., ....

- ::: (x-x2) (x-xz):; .

Y (xl-x2) (x1-x3) + -. y2 (x-x1) (x-x3), -.- (x2 - xl) (x2 - x3)

 UZ (x-x1) (x-x2) RS3-x1) (x3-x2)

.08)

Taking, and (0), (j) we get that

,,

(Nrp), (2Nrp). Then

Taking Vi -rt -1, we get p.Sfplv.f vr-lb 1

) - о .:: 1

(ii-0-.Cr-.;

Taking Vi -rt -1, we get p.Sfplv.f vr-lb 1

 .:,1

(21)

;; (mRL) -jv (/ - 2Nrp),

.-. .l -. T

:: ZDG -; .... .:

: + lMЈMizJ pJ

.L :; :;:, Ч 2 Nrp / ...; ..,.,:

For the obtained polynomial P1 (j), the value of j varies from 0 to (2Nrp-1) in steps of 1. Similarly, for the second polynomial and the second, third, and fourth nodal points, we have:

. (x-x3) (x-x4) A,; / ..; Y (x2-x3) (x2 -x4) ;;:

l :. G: y3 (x - x2) (x - x4;} ,: Y

:.;: / (x3 - x2) (x3 - x4). .;, - ..; ...

V; y4 (x -x2) (x -x3), r,. (X4 -x2) (x4 -x3)

(22)

Acceptance, and (0). (j) we get that: .... .- ... - ..,.

. ,. ..; -: Vv .. (23) -: -,:,:.; L v: - -W: (24) .., v:. :. (25)

;; (Nrp). ::: G :::: .-. (26) (2Nrp) .. j;:; ..; (27) Then. ....;; .-:: .- -; : V ;; ::. .: .. ::;

P20

.S (NrpKj-2Nrp) (j-3Nrp)

. S (2Nrp) () (j-3 Nrp)

: r-.V.

+

rp

, S (3Nrp) (j-Nrp (j-2Nrp :)

(28)

For the resulting polynomial P2 (j), the value of j varies from Nrp to 3Nrp-1; then, in accordance with formula (18), we obtain:. :.

. rw + bw

(

x (Vi -5) V, (Vi - 1). (thirty)

Since for the resulting polynomial, the value of j varies in the range from Nrp to 2Nrp, and the value of Vi varies in the range from 0 to

. . .. -.L .. ... .

1 in increments of tp. And from the fourth outputs 0

5

0

5

0

5

0

5

 k I

 -, -NrP ... ......, ... ..........,

ro 9, third 8 and second 7 memory registers nodal samples S (0), S (IMrp) and S (2Nrp) are taken respectively; and from the output of the first adder 3, the nodal sample S (3Nrp) is taken, which are fed to the first inputs of D1, the fourth 16, the third 15, the second 14 and the first .1.3. computing units, respectively. The functional purpose of the computing blocks 16-13 consists in calculating the first, vtvbrbgb, tpetber o H fourth terms. This is related to formula (30), and the variable Vr is used in each term of formula (30) and is calculated in the second divider 12, and then fed to the second inputs of each computing unit 13-1.6. The current value / of the variable Vi is calculated in the second divider 12 in accordance with formula (4), and the current value of the code changing its state from 0 to Nrp-1 is supplied to the first input of the second divider 12, and the value is supplied to the second input of the second divider 12 Nrp from the control input

DIGITAL NON-REcursive FILTER. In COOT;

In accordance with formula (30), the current values of the first, second, third, and fourth terms are calculated by computing units 16, 15, 14, 13, respectively, and the codes recorded in computing units 16d13 are calculated by formulas (8), (7), (6 ), (5), respectively. . . - ..,: The current value of the polynomial calculated by formula (30) is taken from the output of the third adder and fed to the input of the digital interpolation filter. .. The invention can be applied in digital signal processing devices, with adaptive digital filtering.

The use of the proposed combination of blocks and links in comparison with the prototype is essential. expands

functionality, namely the implementation of the grouping operation in a digital non-recursive filter, provides an extension of the memory interval of the digital, non-recursive filter. non-recursive filter without additional hardware and energy costs. The wide variation of both the memory and weight functions of the filter is equivalent to adjusting the amplitude-frequency characteristics of the filter, -; ::; ; -:, Formula and so take D Digital non-recursive filter containing a first memory register, a delay block, a multiplier block connected in series, the second input of which is the input of the multiplication factor setting and the first is an adder, as well as the second, third and fourth memory registers connected in series, t. l and h, and also with the fact that, in order to simplify the adjustment of the amplitude-frequency characteristics, a second adder is introduced, the first input of which is the information input of a digital non-recursive filter, in turn is connected to data

the input of the first memory register, the first divider the first input of which is connected to the output of the first memory register and the second input of the second adder, and the output is connected to the information input of the delay unit, the pulse counter is connected in series, the information input of which is connected to the synchronization input of the first memory register and is a clock input of a digital non-recursive filter, and a comparison unit, the output of which is connected to the installation input in O of the pulse counter and the first memory register and synchronization inputs, delay of the second, third and fourth register memory, the second divider having a first input connected to the output of the pulse counter, a second input connected to the inputs of the first divider vtorymi- and. block comparison and is the input of the division coefficient, the third adder, the output of which is the output of a digital non-recursive filter, as well as the first, second, third and fourth. Computing blocks, the first inputs of which are connected to the output of the second divider, the second inputs are connected. with the output of the first adder, the second memory register, the third memory register and the fourth memory register, and the outputs are connected to the corresponding inputs of the third adder :; -; ..-.-. ..-... Fng. 1

 FIG. 3

(i)

FIG. 4