JPS61254985A - Image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an image display device for displaying data in an image memory, and particularly relates to an image display device suitable for a field in which enlarging an image by an integral number of times in real time is required.

[Background of the invention]

CA D (Computer Aided Desi)
In image processing such as gn), image enlargement processing is frequently performed.

The processing speed is one important indicator. There are two general methods for enlarging the image: a computer performs arithmetic processing on the image memory contents to generate and display enlarged data, and a method involves preparing enlargement hardware between the image memory and the display. be. Although the former method uses a computer and is capable of fine-grained processing, it has the drawbacks of low load on the computer and low speed. Since the latter supports expansion using hardware, the load on the computer is small and real-time performance is ensured in terms of speed.

As an example of the latter, as shown in the document entitled "Digital Image and Color" by Ken Ito, published by Nikkan Kogyo Shimbun, for example, when magnifying 2x, the contents of the same address are read twice horizontally and vertically. There is a way to do this and expand it. Although the above-mentioned method can be easily realized with hardware and has a satisfactory speed, it has the disadvantage that the original image and the enlarged figure have different shapes because points are enlarged as areas. 8 as an example
The original image and the enlarged image at double magnification are shown in FIGS. 2 and 3, respectively.

[Purpose of the invention]

The present invention solves the above-mentioned drawbacks and provides an image display device that supports enlargement using hardware and enlarges the original image at high speed without damaging it.

□- [Summary of the Invention] The present invention provides an image display device comprising an image memory and an image display, and a means for cutting out data at an arbitrary minimum square lattice point in the image memory.

The apparatus is characterized in that it includes means for generating integer times enlarged data based on the cut out data, and displays said integer times enlarged data.

Furthermore, the means for generating the integer-fold enlarged data uses a rewritable memory, and by supplying data for an arbitrary enlargement factor to the memory, an arbitrary enlargement factor can be displayed.

[Embodiments of the invention]

In other words, cutting out an arbitrary minimum square lattice point on the image memory and enlarging it Q times as shown in FIG.
nt m)l between (n+1.m) and (n, m), (
In order to generate enlarged dots, the points are enlarged. Dots are generated based on the following principles: when a point or straight line is enlarged, its length increases but the line width remains unchanged, and the area surrounded by a point also expands in length and width.
The relationship between the input cover turn and the output cover turn, which shows the output cover turn with respect to the double-angle input cover turn, can be derived using the same concept as in FIG. 8 as long as the magnification is an integer.

After generating and displaying the output in Fig. 7 for the minimum square grid cut out from the image memory in Fig. 5, the next minimum square grid (n+1
．． m), (n+2.m), (n+1, m+1
), (n + 2, m + 1), the enlarged outputs are similarly displayed and processed one after another, thereby obtaining an integer times enlarged figure of the original image.

FIG. 4 shows a case where the original image 1 is enlarged eight times using the method of the present invention.

FIG. 1 shows an example of the configuration of an image display device having an enlargement processing circuit according to the present invention.

A display horizontal/vertical control unit 3 consisting of an X-axis pulse generator 1, a Y-axis pulse generator 2, an X-axis counter 4, and a Y-axis counter 5, which determine the dot period, an X-axis address counter 7, and a Y-axis address counter 9. an image memory 10 that outputs the contents of a designated address; an X-axis 1/n frequency divider 6 that drives the address counter; Y-axis 1/n frequency divider 8, 1-row delay circuit 12 for cutting out an arbitrary minimum square grid, 2-bit shift registers 11 and 13, expansion decoding circuit 14 for generating expanded data from the minimum square grid data, and It comprises a display 15 which is controlled by the display horizontal/vertical control section 3 and displays the enlarged data output from the enlarged decoding circuit 14.

In such a configuration, the contents of the image memory 10 are displayed on the display 15 in the following manner.

First, if there is no expansion, the X-axis 1/n frequency divider 6, the Y-axis 1
/n frequency divider 8 and one row delay circuit 12 for cutting out arbitrary minimum square grid data; 2-bit shift register 1
1, 13, the enlargement decoding circuit 14 is unnecessary, and the output of the image memory 10 is directly connected to the display 15. In the above configuration, the display horizontal and vertical control unit including the X-axis counter 4 and the Y-axis counter 5 controls the X-axis and Y-axis of the display 15, and is synchronized with the X-axis counter 4 and the Y-axis counter 5. The X-axis address counter 7 and Y-axis address counter 9 specify the address of the image memory 10 corresponding to the screen. The output of the image memory 10 is input to the display 15, and the operation at the time of zero-order n-fold enlargement in which the image in the image memory 10 is displayed on the display 15 will be described. When magnified n times.

It is clear that the image memory data is accessed only once for each n dot displayed on the display 15. Therefore, 1/n frequency dividers 6 and 8 are provided before the X-axis address counter 7 and Y-axis address counter 9, and the outputs of the pulse generators 1 and 2 are set to 1/n, and at the same time, the outputs of the pulse generators 1 and 2 are set to 1/n.
The n frequency dividers 6 and 8 specify rows and columns within the enlarged data to the enlarged decoding circuit 14. Circuits 11 to 13 for cutting out an arbitrary minimum square lattice from the image memory 10 output the dots (n, m) and (n + 1 v rn) in FIG.
It is possible to obtain dots (nt m+1) and (n+1.m+1) by a 2-bit shift register 13 connected after the dots. Using these four bits as input, the enlargement decoding circuit outputs an output pattern for the input pattern shown in FIG. 8 and displays it on the display 15, thereby making it possible to display an n-times enlarged figure of the image in the image memory 10.

FIG. 9 shows an example of the configuration of the enlarged decoding circuit 14. The input 4 dots of the minimum square lattice are used as address inputs to the decode RAM 17 to select the corresponding enlarged pattern, and the outputs from the X-axis frequency divider 6 and the Y-axis frequency divider 8 are used to decode one designated point of the enlarged pattern to the decode RAM 17. Output from In order to store the expanded pattern in the decode RAM 17 prior to expansion, a selector 16 is connected to the decode RAM 17 address, and when storing the pattern, the address is specified as an address by the select input from the address input line, and the pattern is written to the corresponding decode RAM storage bit. The configuration is such that it is possible to specify a pattern using specified input.

〔Effect of the invention〕

According to the present invention, a point can be enlarged, a line can be enlarged in the longitudinal direction, and an area can be enlarged in the vertical and horizontal directions, making it possible to enlarge faithfully to the original image. Further, it can be realized by a simple bird mower, and a high-speed enlarged display can be obtained with less processing load on the computer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image display circuit having a figure enlarging function according to the present invention, FIG. 2 is an original image before enlargement, and FIG. 3 is an 8 times enlarged figure of the original image according to a conventional method. Fig. 4 shows an 8x enlarged figure according to the present invention, Fig. 5 shows the given dot input, Fig. 6 shows the dot position with virtual lines added at 5x enlargement, and Fig. 7 shows the output dot for the given dot input. , FIG. 8 is a diagram showing the relationship between the input cover turn and the output cover turn, and FIG. 9 is an example of the configuration of the enlarged decoding circuit. 1...X-axis pulse generator, 2...Y-axis pulse generator. 3...Display horizontal/vertical control unit, 4...X-axis counter. 5...Y-axis counter, 6...X-axis 1/n frequency divider, 7...X-axis address counter, 8...Y-axis 1/n
n frequency divider, 9...Y-axis address counter, 10...
・Image memory, 11...2-bit shift register, 1
2...1 row delay circuit, 13...2-bit shift register, 14...enlargement decoding circuit, 15...display device, 16...selector, 17...RAM.

Claims (1)

[Scope of Claims] 1. In an image display device comprising an image memory and an image display, means for cutting out data at an arbitrary minimum square lattice point in the image memory, and integer-fold enlargement based on the cut out data. An image display device comprising: means for generating data, and displaying the integer-fold enlarged data. 2. The means for generating the integer-fold enlarged data uses a rewritable memory, and displays an arbitrary enlargement factor by supplying data for an arbitrary enlargement factor to the memory. The image display device according to item 1.