JPS6125226B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a static induction type transistor that is effective for high frequency applications.

Conventionally, electrostatic induction transistors have a buried-gate structure in which the gate region is buried inside the semiconductor, and transistors in which the gate region is formed on a flat semiconductor surface so that the gate electrode and source electrode run on the same surface. Gate structures with surface wiring gates have been developed. The latter structure is generally used as a high frequency element. The reason for this is that the stray capacitance between the gate and the source is small, the gate signal transmission resistance R is small, and the time constant (CR) formed by this and the capacitance C between the gate and channel can be made small. It is given.

However, such a surface wiring gate structure also has the following drawbacks. That is, since the gate and source are formed by diffusion from the same surface, the distance between them is small, and therefore the withstand voltage between the gate and source is low, and the stray capacitance between the gate and source cannot be made sufficiently small. Also, the change in drain current I _D with respect to the change in gate voltage Vg (ΔI _D /Δ
V _G ), that is, the mutual conductance g _n cannot be increased.

As a method for solving this problem, a method has been proposed in which the gate region 4 is formed at a deeper position than the source region 5, as shown in FIG.

That is, before forming the gate region 4 by diffusion,
Drain region 1 made of N-type semiconductor with high impurity concentration and N-type epitaxial layer 2 with low impurity concentration
For example, by partially removing the semiconductor body consisting of a silicon nitride film by selective etching using a silicon nitride film as a mask, a recess is formed only in the part where the gate region is to be formed, and then the gate region is formed using diffusion or the like. Form region 4, then source region 5
We are taking a method to form a (Note that 3 in the figure indicates that the protective film 6 is an electrode.) If such a structure and its manufacturing method are used, various problems will occur as listed below.

When forming a narrow slit-like recess by etching, it is difficult to level the bottom surface.

Difficulty in selectively etching a mask (for example, SiO ₂ ) to diffuse the gate only in the center of the recess.

A similar selective etching patterning problem of metallized metal for the formation of electrode 6.

Problem of disconnection of the metallized layer at the stepped portion at the end face of the diffusion layer.

Therefore, this technique is extremely difficult when obtaining a high frequency device with a fine pattern.

The present invention has been made with the object of solving the above-mentioned manufacturing problems and obtaining an element suitable for high frequency use, which has a high breakdown voltage, low stray capacitance, low gate resistance, and high mutual conductance. Embodiments of the invention will now be described in detail with reference to the drawings.

FIG. 2 shows a process flowchart for manufacturing a high frequency electrostatic induction transistor by the method of the present invention. FIG. 2a shows a silicon semiconductor in which an epitaxial layer 2 with an impurity concentration (N ^- ) sufficiently lower than that of the substrate 1 is formed on the surface of a highly impurity-concentrated N-type (N ⁺ ) semiconductor substrate 1 that will serve as a drain region. The figure shows a state in which the surface is oxidized to form an oxide film with a thickness of about 500 Å to 2000 Å, and patterned by photolithography so that only the oxide film 31 at the position where the gate is to be formed is left. It is.

Next, as shown in FIG. 2b, when silicon is vapor phase grown, a polycrystalline silicon film 22 is formed on the area where the oxide film 31 remains, and a single crystal silicon film 21 is formed on the exposed silicon surface. Grow selectively. At this time, if the thickness of the oxide film 31 is as thin as 2000 Å or less, the oxide film 31 will be etched in the epitaxial process and almost disappear.

Next, as shown in FIG. 2c, a single crystal silicon film 2 is formed.
A window is formed by patterning the photoresist 8 so as to include the boundary between the porous silicon layer 1 and the polycrystalline silicon film 22, thereby forming a porous silicon layer 7. The porous silicon layer 7 is formed by applying a direct current to a 50% hydrofluoric acid solution while keeping the substrate positive and the platinum electrode negative so as to face the semiconductor substrate and its surface. At this time, it is necessary to make the material porous to a depth corresponding to the depth of polycrystalline silicon, but this can be easily achieved by controlling the magnitude of the current and the duration of the current.

Next, as shown in FIG. 2d, oxidation treatment is performed in wet O ₂ to oxidize the porous silicon. At this time, the oxidation rate of porous silicon is fast, so the porous silicon will completely become the oxide film 3 in about 30 minutes at 1100℃, but the monocrystalline silicon and polycrystalline silicon parts will oxidize at most 4000~30 minutes at 1100℃. Only an oxide film 33 of 5000 Å is formed.

Thereafter, as shown in FIG. 2e, the oxide film 33 above the part where the gate region 4 is to be formed is partially removed, and the remaining oxide films 33, 3 are used as a mask to remove the polycrystalline silicon film 22 and its lower part. A p-type impurity is diffused at a high concentration into the epitaxial layer 2 to form a gate region 4 and a new oxide film 3 is formed on the surface.
form 4. Next, by the same method as above, the oxide film 3 made of porous silicon, the newly formed oxide film 34, and the previously formed oxide film 3 are formed.
A source region 5 is formed by diffusion using a part of the oxide film 3 as a mask, and at that time, a new oxide film 3 is formed on the surface of the source region 5.
form 5.

Thereafter, as shown in FIG. 3, metal is deposited and selectively etched to form electrode wiring.

In the present invention, since the oxide film 3 facilitates self-alignment during the diffusion and metal etching steps, even fine patterns can be easily formed. That is, since the oxide films 33, 34, etc. are sufficiently thinner than the oxide film 3, when etching them, the oxide film 3 may be etched at the same time. As long as it is on the oxide film 3, no higher alignment accuracy is required. In addition, in the above method, in the diffusion of the gate part,
An example has been described in which the polycrystalline silicon portion 22 and single crystal silicon are diffused into the epitaxial layer 2 at the same time. In this case, the process is simple, but the sheet resistance is lower than when the above diffusion is carried out separately. The cost will be slightly higher, so when implementing it, you should take this into consideration when deciding which method to use.
It is necessary to form the gate region 4 before forming the regions 1 and 22.

The present invention has been described above in detail using specific examples, and the present invention has the following effects.

Since the gate region 4 can be formed at a lower position than the source region 5, it is easy to control the drain current flowing through the channel, and therefore the mutual conductance g _n (=ΔI _D /ΔV
_G ) {I _D is the drain current, V _G is the gate voltage} can be increased.

Since there is an oxide film between the gate and source, it has a high breakdown voltage and the parasitic capacitance between the gate and source Cg _s
As a result, this is useful for improving high frequency characteristics.

Although the gate region 4 is located at a deep position, its upper part is covered with polycrystalline silicon, so the height of the surface above the gate region 4 is approximately the same as the height of the surface above the source region 5, so that the overall height difference is small. , Defects are less likely to occur when selective photolithography is applied, and metal wiring is less likely to be disconnected.

Since the gate region and the gate electrode are connected through a polycrystalline semiconductor with a high impurity concentration, series resistance is small, which helps improve high frequency characteristics.

Selective processing in the source and gate diffusion and metallization steps can be performed in a self-aligned manner by utilizing the difference in oxide film thickness, and microfabrication can be facilitated.

Although the present invention has been described above with respect to a method for manufacturing a static induction transistor, the method of the present invention is also applicable to other vertical field effect transistors, etc. in which electrodes are drawn out from at least a region formed inside a semiconductor using a polycrystalline semiconductor, and This method can be implemented in all cases where the crystal is separated from the single crystal on its outer periphery by an insulating part.

Furthermore, when forming a single crystal region and a polycrystalline region on a semiconductor substrate, in addition to using the oxide film described above, a thin polycrystalline film is formed on the semiconductor surface at a low temperature in advance, and then it is partially etched to form a polycrystalline region. Polycrystals may be grown on crystals and single crystals may be grown on single crystals. Furthermore, a strained layer may be formed partially on the surface of the semiconductor substrate, and polycrystals may be grown on other parts of the semiconductor substrate. may be formed.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a device obtained by the conventional method, Fig. 2 is a process flowchart showing each step in the manufacturing method of the present invention using a cross-sectional view of a semiconductor, and Fig. 3 is a cross-sectional view of a device obtained by the method of the present invention. FIG. 3 is a cross-sectional view showing an example of the obtained element. DESCRIPTION OF SYMBOLS 1... Semiconductor drain region, 2... Epitaxial layer, 3... Oxide film, 4... Gate region, 5...
... Source region, 6 ... Metal wiring, 7 ... Porous silicon layer, 8 ... Photoresist, 21 ... Single crystal silicon, 22 ... Polycrystalline silicon, 31,3
2, 33, 34...Oxide film.

Claims (1)

[Claims] 1. A single crystal region that serves as an operating region is selectively formed on the surface of a semiconductor single crystal substrate, and a polycrystalline region is formed adjacent to the single crystal region on the surface of the semiconductor single crystal substrate. and forming a porous semiconductor region at the boundary between the single crystal region and the polycrystalline region, and then converting the porous semiconductor region into an oxide film to separate the polycrystalline region and the single crystal region. separation by the oxide film, selectively diffusing impurities into the polycrystalline region using the oxide film as a mask, and using the polycrystalline region as an electrode extension portion from the semiconductor region formed on the semiconductor single crystal substrate; A method for manufacturing a semiconductor device, characterized by: 2. The semiconductor device according to claim 1, characterized in that impurities are simultaneously diffused into the polycrystalline region and the semiconductor substrate below the polycrystalline region using an oxide film obtained by converting the porous semiconductor region as a mask. manufacturing method. 3 With a thin semiconductor oxide film partially formed on the surface of the semiconductor substrate, epitaxially grow a polycrystalline region on the oxide film and a single crystal semiconductor region in other parts, and oxidize under the polycrystal. 2. The method of manufacturing a semiconductor device according to claim 1, wherein most of the film is eliminated.