JPS61251253A - Multiplexing system for multipoint circuit - Google Patents

Abstract

PURPOSE:To attain communication with branch-connected data terminals without putting a load on a software by connecting a multiplexer and a demultiplexer with an exchange side and a terminal side respectively. CONSTITUTION:An exchange side line multiplexing device 200, with concentrating three lines to a single line, is connected with terminal side line multiplexing devices 0, 1, 2, 300a, 300b and 300c respectively by a sending line SND and a receiving line RCV. The output of a parallel-series conversion circuit is time- divisionally multiplexed by the timing signal of a timing signal generating circuit. At a transmission buffer, the multiplexed data are stored temporarily and an interface between a modulation device is matched and through the modulation device, a data transmission to the sending line SND is carried out. Data within a receiving buffer is separated to the said destinated terminal only by the demultiplexer and through a serial-parallel conversion circuit and the parallel-serial conversion circuit, the data speed of it is restored to the one before it is multiplexed by the exchange side line multiplexing device 200.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a branch line multiplexing system, and in particular to a high-level data link control procedure (hereinafter referred to as
This is called the HDLC procedure. ) relates to a branch line multiplexing method in a data communication system having data transmitting/receiving terminals controlled by.

〔overview〕

The present invention provides a branch line multiplexing method for a data communication system having a line network in which a plurality of data transmitting/receiving terminals controlled by an HDLC procedure are branch-connected to a line. A line multiplexing device including a multiplexer that multiplexes data on a line using a time division multiplexing method, and a demultiplexer that divides data on one line into data on multiple lines is provided on each of the exchange side and the terminal side. This allows terminal recognition,
This eliminates the conventional software considerations for competition, etc., and simplifies the software.

[Conventional technology]

Conventionally, in a data communication system consisting of a data storage/exchange device and multiple data transmitting/receiving terminals branch-connected to it by a full-duplex line, in order to adapt to high-speed data transmission, any The HDLC procedure is often used as a procedure for efficiently performing synchronous data transmission without being subject to coding restrictions.

This) IDLC procedure uses a bit string starting with a start flag sequence and ending with an end flag sequence as a frame structure, and is controlled in detail by software.

[Problem that the invention seeks to solve]

In a data communication system having data transmitting/receiving terminals controlled by the above-mentioned IDLc procedure, in the downlink, the exchange side recognizes the terminals currently communicating on the same line, or the terminal side recognizes the data transmitting/receiving terminals for its own station. In the uplink, the switch side has to take into account the contention when transmitting data from the terminal, and the load on the software is lower than that of a system without branch connections. It was getting bigger.

For this reason, the conventional technology has the disadvantage of increasing the number of software steps and resulting risks.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a branch line multiplexing system that eliminates the above-mentioned drawbacks, thereby reducing the number of software steps and preventing the risks associated therewith.

[Means for solving problems]

The branch line multiplexing method of the present invention is a branch line multiplexing system for a data communication system consisting of a data storage/exchange device and a plurality of data transmitting/receiving terminals that are branch-connected to the data storage/exchange device by a full-duplex line and controlled by a high-level data link control means. In the data storage/exchange device and the data transmitting/receiving terminal, a transmitter including a multiplexer that multiplexes data on multiple lines onto one line using a time division multiplexing method; It is characterized in that a line multiplexing device including a receiving unit including a demultiplexer that divides data into data of a plurality of lines is connected to each line.

[Effect]

The present invention provides a multiplexer that multiplexes data on multiple lines onto a single line using a time division multiplexing method, and a demultiplexer that divides data on one line into data on multiple lines on the exchange side and By connecting each terminal side, it is possible to communicate with branch-connected data terminals without putting a load on the software.

Furthermore, even when a data communication system that has already been constructed without using branch lines is changed to a branch line network, the present invention eliminates the need to change communication procedures or software by adding this device. , useful.

[Example] □ Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system diagram showing a facsimile storage and forwarding method as an embodiment of the present invention.

For simplicity, this embodiment has a configuration in which only three terminals are connected to one branch line.

First, three lines (L
O3, LOR), (LIS, LIR), (L2S,
L2R) is connected to the exchange side line multiplexer 200, and the exchange side line multiplexer 200 concentrates these three lines into one, transmitting circuit line SND, receiving section, and %1RC.
The terminal side line multiplexing equipment (0), (1), (
2) , 300a, 300b, and 300c (hereinafter, these are collectively referred to as the terminal-side line multiplexing device 300, except in special cases). Furthermore, terminal side line multiplexing devices (0), (1), (2), 300a
, 300b, 300c are facsimile transmission/reception terminals (0), (1), (2), 400a, 400b,
400c (hereinafter referred to collectively as facsimile transmitting/receiving terminal 400 except in special cases), communication between storage and forwarding device 100 and facsimile transmitting/receiving terminal 400 is finally possible.

Next, the flow of data when data is transmitted from the data storage/exchange device 100 to the facsimile transmitting/receiving terminal 400 will be explained step by step based on partial detailed block diagrams shown in FIGS. 2 to 5.

FIG. 2 is a block diagram of the transmitter of the exchange side line multiplexer 200. First, transmission data from the data storage and exchange device 100 to line (0), LOS to line (2), and L2S are sent to reception buffers (0), (1), and (2), respectively.
), 201.202.203. The transmission data of each line is in the reception buffer (0), (1), (2)
, 201.202.203, and are temporarily stored after ink face alignment. Next, the clock generation circuit 204 generates a clock for serial/parallel conversion based on the bit synchronization clock CLK from the data storage/exchange device 100, and serial/parallel conversion circuits (0), (1), (2),
205.206.207 is the previous receive buffer (0),
Controls the conversion of data (1), (2), 201, 202, and 203 into parallel data of every 8 bits. In addition, in the frequency dividing circuit 208, the clock generation circuit 204
Divide the clock output by 4, and use the divided clock to convert the parallel to serial conversion circuits (0), (1), (2), 209
．． 210 and 211 control the conversion of the 8-bit parallel data just converted into serial data.

A non-F data detection circuit 212 that detects data other than flag F generates a pulse when data other than pufferfish F is received from a state in which flag F is being received, and this pulse and the clock output of clock generation circuit 204 generate a pulse. Therefore, the parallel-to-serial conversion circuits (0), (1), (2), 209.210.2 are generated by the timing signal of the timing signal generation circuit 213 that generates a signal to control the multiplexer 214.
The outputs of 11 are time-division multiplexed. The transmission buffer 215 temporarily stores this multiplexed data, performs ink face matching with the modulation device 216, and transmits the data to the transmission line SND via the modulation device 216.

FIG. 5 is a block diagram of the receiving section of the terminal-side line multiplexing device 300 that receives the above data. First, data received from the line is converted into digital data by the demodulator 421, and the data is temporarily stored in the reception buffer 422 and subjected to interface conversion. The non-F data detection circuit 423 and the timing signal generation circuit 424 have the same function as the previously described circuit, and the counting circuit 425, triggered by the output pulse of the timing signal generation circuit 424, also has the same function as the previously described circuit. Clock generation circuit 4
The counting process of 26 clock outputs is started. On the other hand, the terminal information holding unit 427 consisting of non-volatile memory holds,
The verification circuit 428 verifies the output of the counting circuit 425 with the information indicating the number of the terminal on the branch line. And the decoder 429 is the collation circuit 4
A control signal for the demultiplexer 430 is generated based on the output of the demultiplexer 28. The data in the reception buffer 422 is separated by a demultiplexer 430 into only the data addressed to the terminal, and then sent through a serial/parallel conversion circuit 431 and a parallel/serial conversion circuit 432 before being multiplexed by the exchange side line multiplexer 200. data rate. Finally, a transmission buffer 433 performs bumpering and interface matching.
The received data is sent to the facsimile transmitting/receiving terminal 4 through
Passed to 00.

The case of transmitting data from the facsimile transmitting/receiving terminal 400 to the data storage/exchange device 100 will be described below with reference to FIGS. 3 and 4.

FIG. 4 is a block diagram of the transmitter of the terminal-side line multiplexer 300. First, data SD sent to the line from the own facsimile transmitting/receiving terminal 400 to which the digital signal line is directly connected is received by the receiving buffer (D) 402, and subjected to ink face conversion and temporary storage. Next, the serial/parallel conversion circuit 406 converts the bit synchronization clock CIJ from the facsimile transmitting/receiving terminal 400 into the frequency dividing circuit 406.
Serial data is converted into 8-bit parallel data using the frequency divided by 4 at step 07 as a control signal. Furthermore, the parallel-to-serial conversion circuit 410 converts the 8-bit parallel data output from the serial-to-parallel conversion circuit 406 into serial data again using a control signal generated from the clock CLK from the facsimile transmission/reception terminal 400 by the clock generation circuit 411. . The speed-converted data as described above becomes the input to the multiplexer 414 described below. On the other hand, the terminal receiving line LR
As shown in FIG. 1, the CV is connected to a transmission line from one terminal among a group of terminals connected to the same branch line. Therefore, the analog data transmitted from the connected facsimile transmitting/receiving terminal is converted into digital data by the demodulator 401, ink face conversion and temporary storage processing is performed by the receiving buffer (A) 403, and becomes the input signal of the multiplexer 414. . Independently from the above data flow, a data other than F detection circuit 405 monitors the data in the reception buffer (D) 402 and reception buffer (A) 403, and detects data other than flag F from the flag F data reception state. When transitioning to the receiving state, the timing signal generation circuit 404 is notified of this and generates a timing pulse. Using the timing pulse as a trigger, the counting circuit 409 starts counting the output of the clock generating circuit 411. Also, in the terminal information holding device 408, among the terminals connected to the branch line, the terminal closest to the exchange (Hookjimiri transmitting/receiving terminal (0) 4 in FIG. 1) is stored.
00a and the farthest terminal (facsimile transmitting/receiving terminal (2) in FIG. A decoder 413 performs decoding and further decodes the output of the matching circuit 412.
The output of is used as a control signal for multiplexer 414. The output of the multiplexer 414 is buffered and ink-face converted in a transmission buffer 415, converted into analog in a modulation device 416, and transmitted to the transmission line LNSD, that is, the data storage and exchange device 100.

The receiving section of the exchange side line multiplexing device 200 shown in FIG. 3 receives the above-mentioned transmission data. In Figure 3,
A demodulator 221 receives and demodulates the data transmitted from the facsimile transmitting/receiving terminal 400 via the receiving line RCV, and transfers it to the receiving buffer 222 . The reception buffer 222 performs interface matching and temporary storage of the digital data, and then transfers the data to the demultiplexer 227. Non-F data detection circuit 224 and timing signal generation circuit 22
The function of No. 5 is the same as the previously described one, and the output direction of the reception buffer 222 is controlled by the demultiplexer 227, which is controlled by the output direction of the decoder 226 that decodes the output direction of the timing signal generated by the timing signal generation circuit 225. distributed to lines. The distributed signals are sent to the clock generation circuit 223, serial/parallel conversion circuits (0), (1), (
2), 228.229.230, frequency dividing circuit 234,
Parallel-serial conversion circuit (0), (1), (2), 231
．． Transmission buffer (0) that is speed-converted by H.232.233 and performs buffering and ink face matching;
(1), (2), and 235.236.237 to the data storage and exchange device 100.

In addition, in this example, since the maximum number of terminals branch-connected to the - line is 3, all frequency divider circuits in the text output signals with a period four times that of the input signal, resulting in Although the data rate conversion was set at a ratio of 1:4, this value varies depending on the maximum number of terminals that can be accommodated on the -branch line. That is, when the maximum number of terminals to be accommodated is M, when the frequency dividing circuit attempts to perform frequency division by n, the relationship between M and n satisfies the relationship n > M.

〔Effect of the invention〕

As explained above, in a data communication system having branch lines, if the branch line multiplexing device according to the present invention is loaded on the exchange side and the terminal side, the software of the exchange and terminals can build up the system without being aware of the branch lines. This has the effect of reducing software man-hours and eliminating risks associated with it.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing a facsimile storage and forwarding system as an embodiment of the present invention. 2 and 3 are block diagrams showing a transmitting section and a receiving section of the line multiplexing device on the exchange side of FIG. 1. FIG. FIG. 4 and FIG. 5 are block diagrams showing a terminal-side line multiplexing device transmitter and receiver, respectively. 100... Data storage and exchange device, 200... Exchange side line multiplexing device, 201... Reception buffer (0)
, 202...Reception buffer (1), 203...Reception buffer (2), 204.223.411, 426
...Clock generation circuit, 205.228...Serial to parallel conversion circuit (0), 206.229...Serial to parallel conversion circuit (1), 207.230...Serial to parallel conversion circuit (2
), 208.234.407.434... frequency divider circuit,
209.231...Parallel-serial conversion circuit (0), 210
．． 232...Parallel-serial conversion circuit (1), 211.233
...Parallel-serial conversion circuit (2), 212.224.40
5.423...data detection circuit other than F, 213.22
5.404.424...timing signal generation circuit, 2
14.414...Multiplexer, 215.415.
433... Transmission buffer, 216.416... Modulation device, 221.401.421... Demodulation device, 222
．． 422...Reception buffer, 226.413.429
...Decoder, 227.430...Demultiplexer, 235...Transmission buffer (0), 236...
Transmission buffer (1), 237... Transmission buffer (2
), 300a...terminal side line multiplexer, (0),
300b...terminal side line multiplexing device (1), 300c
. . . terminal side line multiplexing device (2), 400a . . . facsimile transmission/reception terminal (0), 400b . Receive buffer (D), 403...Receive buffer (A), 406
．． 431...Serial-to-parallel conversion circuit, 408.427...
Terminal information holding device, 409.425... Counting circuit, 4
10.432...Parallel-serial conversion circuit, 412.428.
... Verification circuit, CLK... Clock, CRCV...
Receiving line to exchange, LO5-L2S... line (sending side), LOR-L2R... line (receiving side), SN
D, LSND...transmission line, LRCν...terminal receiving line, RCV...reception line, RD...reception data, SD...transmission data.

Claims (1)

[Claims] (1) In a branch line multiplexing method of a data communication system consisting of a data storage and exchange device and a plurality of data transmission/reception terminals that are branch-connected to the data storage and exchange device by full-duplex lines and controlled by a high-level data link control means, the data storage The switching device and the data transmitting/receiving terminal include a transmitter including a multiplexer that multiplexes data on multiple lines onto one line using a time division multiplexing method; A branching line multiplexing system characterized in that line multiplexing devices each including a receiving section including a demultiplexer for dividing are connected to each other.