JPS6125105Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an automatic music selection device for a tape recorder.

Recently, an automatic song selection system that automatically selects and plays a desired song by detecting the no-signal portion between the signals of music recorded on magnetic tape, that is, the song interval in fast forward or rewind mode. Devices have begun to be added to tape recorders.

In general, this automatic music selection device performs an automatic music selection operation that shifts to the right when operating a program to set which song to automatically select, detects the gap between songs, and automatically plays the desired song. Sometimes, a shift register that can shift left and right is used, and in order to operate this shift register, a left and right shift direction switching signal that switches the left and right shift direction of this shift register and a flip-flop that constitutes the shift register are used. A timing generation circuit is required that generates a clock pulse input to a clock terminal in response to an input signal from a music selection switch and an inter-music detection signal.

Incidentally, the shift register is composed of a plurality of flip-flops, and therefore has a time interval longer than the delay time called the setup time (A period) and hold time (B period) as shown in FIG. , the timing generation circuit must output the left/right shift direction switching signal R/L and the clock pulse CLK.

Generally, in an IC, it is possible to create such a delay time using a time constant circuit made up of a resistor and a capacitor inside the IC, and a timing generation circuit can be configured using this time constant circuit. However, this type of timing generation circuit has many variations, voltage dependence and temperature dependence, and has the disadvantage that it requires a large area to create a capacitor inside the IC.

Therefore, if the timing generation circuit is configured with an oscillator and a flip-flop, the above drawbacks can be overcome, but the timing circuit for automatic music selection is similar to the previous one, and the timing circuit receives both the input signal from the music selection switch and the inter-music detection signal. It must respond to signals asynchronously, which increases the number of elements and tends to make the circuit complex.

Furthermore, since the input signal from the music selection switch and the inter-music detection signal are completely asynchronous signals in the timing generation circuit, so-called racing trouble may occur.

The present invention provides a new automatic music selection timing generation circuit that eliminates these drawbacks.

Embodiments of the present invention will be described below with reference to the drawings.

Fig. 2 shows an example of a sequential program method in which a desired song is set by pressing a music selection switch several times, and Fig. 3 shows an example in which a desired song is set by pressing one of a plurality of music selection switches. An example of a switch compatible program method will be shown.

First, an embodiment using a sequential program method will be described.

In FIG. 2, 1 is a song selection switch, and 2 is an inter-song detection signal from a song-interval detection circuit (not shown) that detects a no-signal portion between signals of music recorded on a magnetic tape, that is, an interval between songs. a timing generation circuit that inputs K and the input signal So from the music selection switch;
3 is a clock pulse from timing generation circuit 2
This is a shift register for between songs that can be shifted in both left and right directions to which CLK ₂ and shift direction switching signal R/L are input.

The music selection shift register 3 includes flip-flops 4 to 7 and a multiplexer 8 for controlling the shift direction.
-11 and an AND gate 12, and flip-flops 5, 6, and 7 correspond to the selected songs, ie, the first to third songs, respectively. The output terminals of these flip-flops 5, 6, and 7 have LEDs 13 and 1, respectively.
4 and 15 are connected, and the flip-flop to which logic "1" is shifted is indicated by lighting. In other words, it displays how many songs will be automatically selected. Further, a plunger is connected to the output end of the flip-flop 4 to cancel the fast forward or rewind state and to bring the tape recorder into the playback state.

Incidentally, multiplexers 8 to 11 are connected to analog gates 16 and 17 and inverter 1 as shown in FIG.
The signal R/L consists of 8 and is input to the E terminal.
When is "H", the analog gates 16 and 17 are turned on and off, respectively, thereby connecting the A terminal and the C terminal, so that the output terminal Q of the flip-flop in the previous stage is connected to the input terminal D of the flip-flop in the subsequent stage.
, the shift register 3 enters the rightward shift mode. Also, the signal R/L input to the E terminal
When is "L", the analog gates 16 and 17 are turned off and on, respectively, and the B and C terminals are connected, so that the output terminal Q of the flip-flop in the subsequent stage is connected to the input terminal D of the flip-flop in the previous stage.
, the shift register 3 enters the leftward shift mode.

Furthermore, the configuration of the timing circuit 2 will be explained in detail as follows.
19 is a flip-flop to which the input signal So is applied to the clock terminal; 20 is a flip-flop to which the inter-track detection signal K is applied to the clock terminal;
An oscillation circuit 22 and 23 including a resistor R and a capacitor C to which the IC is externally connected are flip-flops forming a register, and a clock pulse CLK ₁ outputted from the oscillation circuit 21 is input to a clock terminal. Further, 24 is a NOR gate that generates an output only when the outputs Q ₅ and Q ₆ of flip-flops 22 and 23 are in a predetermined state, and 25 is an input of the output of flip-flop 19 and the output of NOR gate 24 via an inverter 26. 20 is a NAND gate that receives the output of the flip-flop 19 and the output of the NOR gate 24 via an inverter 28 and resets the flip-flop 19 with its output.
This is a NOR gate which inputs the Q outputs of Flip-flops 19 and 20 and resets flip-flops 22 and 23 by the output.The output _Q4 of flip-flop 19 is used as the left/right shift direction switching signal R/L, and the output _Q6 of flip-flop 23 is used as a clock pulse.
It is input to the music selection shift register 3 as CLK2.

Here, the oscillation circuit 21 is configured to start oscillating when the "L" output of the flip-flop 19 or 20 is applied to the NAND gate 30.

Next, the operation of this embodiment will be explained with reference to FIG.

When you press song selection switch 1, flip-flop 1
An input signal So of "H" is applied to the clock terminal CL of 9, and the output _Q4 becomes "H" as shown in FIG. 5(b). Therefore, the reset of the flip-flops 22 and 23 is canceled by the output of the NOR gate 29, and the left/right shift direction switching signal R/
When L becomes "H", the music selection shift register 3 is set to rightward shift mode. Also, the output of the flip-flop 19 becomes "L", and the P channel MOS,
Since the FET 32 is turned on, the potential at point P changes from "L" to "H". However, P
When the potential at the point becomes "H", the inputs of the NANP gate 31 both become "L" and the P channel MOS,
Since the FET 32 is turned off, the potential at point P gradually decreases according to the time constant determined by the resistor R and capacitor C, as shown in FIG. 5A. Then, when the potential at point P becomes "L", the NAND gate 31
An “H” signal is applied to the P channel again.
Turn on MOS and FET32. This operation is repeated, and a clock pulse _CLK1 as shown in FIG. 5C is output.

When this clock pulse CLK ₁ is input to the clock terminals CL of the flip-flops 22 and 23, since the output of the flip-flop 23 is input to the input terminal D of the flip-flop 22, the clock pulse CLK ₁ is applied and the output is output.
Q ₅ becomes "H" as shown in Figure 5 D. Then, with the next clock pulse CLK ₁ , the output Q ₆ also becomes "H", and when further clock pulse CLK ₁ is applied, the output Q ₅ becomes "L" and the output Q ₆ becomes "H". Then,
Both inputs to the NOR gate 24 become "L", and the output Go becomes "H". This “H” output
Go is applied to flip-flop 19 through NAND gate 27 to reset flip-flop 19.

Therefore, the output _Q4 changes to "L" and the signal R/L
becomes "L" and switches the music selection shift register 3 to leftward shift mode, and the output _Q4 becomes "L".
Flip-flop 22 via NOR gate 29
The outputs _Q5 and _Q6 for resetting the music selection shift register 23 both become "L", and the application of the clock pulse CLK2 to the music selection shift register is stopped. Furthermore, when the flip-flop 19 is reset, the output applied to the NAND gate 30 becomes "H", so that the generation of the clock pulse CLK1 is also stopped.

In this way, only one clock pulse CLK2 is applied from the timing generation circuit 2 to the music selection shift register 3 in response to the depression of the music selection switch. Therefore, if the first song is currently programmed, in order to change it to the third song, the song selection switch 1 only has to be pressed twice.

The flip-flop 20 is reset by the output of the NAND gate 25 which inputs the output of the flip-flop 19, so while the input signal from the music selection switch 1 is applied to the flip-flop 19 and a right shift operation is performed, the flip-flop is reset. 20 will never work. Therefore,
There is no racing trouble when the completely asynchronous song detection signal and song selection switch input are input at the same timing.

Next, automatic music selection operation will be explained.

Now, the third song is programmed and LED1
Assume that 5 is lit. In this state, when the fast forward or rewind button is pressed, detection between songs is started.
Then, when the first song interval is detected, the song interval detection signal K is applied to the clock terminal of the flip-flop 20, and therefore the "L" output is applied to the NAND gate 30, and the oscillation circuit 21 generates the clock pulse CLK1. At the same time, NOR gate 29
This releases the reset of flip-flops 22 and 23, and the output states of both flip-flops sequentially change. Then, when the outputs Q ₅ and Q ₆ become "L" and "H", respectively, the NOR gate 24 outputs the "H" output Go, and the flip-flop 20 is reset by this Go signal. That is, when an interval between songs is detected, one clock pulse CLK2 is output.

Here, the inter-track detection signal K is applied to the flip-flop 2.
When input to 0, the output of "H" is input to flip-flop 19 through NAND gate 27, so flip-flop 19 remains reset. Therefore, the _Q4 output is always "L" in the automatic music selection operation state, and the music selection shift register 3 is set to the leftward shift mode. In other words, when the first song interval is detected, a logic "1" is shifted from flip-flop 7 to flip-flop 6, and the LED
15 goes out and LED 14 lights up. Similarly, when the next song interval is detected, logic "1" is shifted from flip-flop 6 to flip-flop 5, LED 14 goes out, and LED
13 lights up. Furthermore, when the next song interval is detected,
Logic "1" is shifted from flip-flop 5 to flip-flop 4, all LEDs 13, 14, and 15 are turned off, and the output Q4 of flip-flop ₄ drives the plunger connected to the output terminal, and the fast forward or rewind state is released. The tape recorder enters playback mode. In other words, the third song will be played.

Next, an embodiment using a switch compatible program method will be described with reference to FIGS. 3 and 6.

The difference between the two programming methods in terms of the structure of the timing circuit is that in the sequential programming method shown in FIG.
7, an inverter 28 is provided between the NOR gate 24 and the NAND gate 27, whereas in the switch compatible programming method shown in FIG. The only difference is that a NAND gate 36 for inputting the output and the input is provided.

Therefore, the operation of the embodiment shown in FIG. 3 will be explained by taking as an example the case where the first song is programmed and it is changed to the third song.

When the music selection switch 39 is pressed, an "H" signal is applied to the clock terminal of the flip-flop 19, and from then on, similarly to the sequential program method, the music selection shift register 3 is placed in the rightward shift mode, and the flip-flops 22 and 23 are driven by clock pulses. The state changes sequentially by CLK1,
Output _Q5 becomes "L" and output _Q6 becomes "H". Therefore, the NOR gate 24 outputs an "H" Go signal. However, since the music selection switch 39 remains pressed and the input signal So is "H" as shown in FIG. , the output of the NAND gate 27 becomes "L" unlike in the sequential programming method. For this reason, flip-flop 19 is not reset, and therefore flip-flops 22 and 23 are not reset either, and the output of flip-flop 19 remains in the "L" state, so that the clock pulse
CLK1 also occurs without stopping. That is, flip-flops 22 and 23 are
As shown in Figures E and F, clock pulse CLK1
The status changes accordingly.

Then, the first clock pulse CLK2 causes flip-flop 5 to flip-flop 6 to be switched from flip-flop 5 to flip-flop 6.
Logic “1” is shifted to , and LED13 turns off.
LED14 lights up. Next clock pulse CLK
2, the logic "1" is further shifted from flip-flop 6 to flip-flop 7, LED14 goes out, and LED
15 lights up. That is, the third song is programmed.

In this way, when the logic "1" is shifted to the flip-flop 7 and its output _Q3 becomes "H", the input signal So is changed by the inverter 41 even though the music selection switch 15 remains pressed. It changes from "H" to "L" as shown in "B". Therefore, an "H" signal is applied to the NAND gate 36, and the circuit configuration becomes exactly the same as that in the sequential programming method.

Therefore, when the outputs Q ₅ and Q ₆ of the flip-flops 22 and 23 become "L" and "H" respectively, the flip-flops 19, 22, and 23 are all reset, and therefore the music selection shift register 3 is shifted to the left. At the same time as changing to the mode for the first time, the application of the clock pulse CLK2 to the music selection shift register 3 is stopped.

In this way, in the switch compatible program method, in response to the press of the music selection switches 37 to 39, the clock pulse CLK2 is continuously sent from the timing generation circuit 2 to the music selection shift register as shown in FIG.
3 will be applied.

The automatic music selection operation is exactly the same as the sequential program method.

Although the automatic music selection timing generation circuit of the present invention can respond to both the input signal from the music selection switch and the song interval detection signal as described above, it is possible to reduce the number of elements and simplify the circuit. can. Furthermore, since operation by one of the two signals is prohibited while operating by the other signal, racing troubles can be prevented, and the practical value of the present invention is extremely high. It is something.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the relationship between the left/right shift direction switching signal R/L and the clock pulse CLK, Figs. 2 and 3 are circuit diagrams showing an embodiment of the present invention, and Fig. 4 is a specific circuit diagram of a multiplexer. , FIGS. 4A to 4E are timing charts for explaining the operation of the sequential program method, and FIGS. 6A to 6F are timing charts for explaining the operation of the switch compatible program method. Explanation of main figure numbers, 1... Music selection switch, 2 ...
Timing generation circuit, 3 ...shift register for music selection, 13-15...LED, 21 ...oscillation circuit,
37-39...Track selection switch.

Claims (1)

[Scope of utility model registration request] An inter-song detection circuit detects no-signal sections between signals of music recorded on a magnetic tape during fast forwarding or rewinding, and a song selection switch shifts the number of no-signal sections to the left or right as set. In an automatic song selection device, the automatic song selection device has a shift register capable of canceling a fast forward or rewind state and switches the tape recorder to a playback state when the song interval detection circuit detects a number of no-signal portions set in the shift register. , a first input signal from the music selection switch;
a second flip-flop to which the output signal of the song interval detection circuit is input; an oscillation circuit that starts oscillation by the output of the first or second flip-flop; and a plurality of stages of flip-flops. a counter or register that inputs output pulses; a first gate circuit that generates an output when the contents of the counter or register reach a predetermined state; and an output of the first gate circuit and the first gate circuit. a second gate circuit which inputs the output of the flip-flop and resets the second flip-flop by the output;
A third gate circuit inputs the output of the first gate circuit and the output of the second flip-flop and resets the first flip-flop by the output, or a third gate circuit that receives the output of the first gate circuit and the output of the music selection switch. a fourth gate circuit inputting the signal; and an output of the fourth gate circuit and the second gate circuit.
a fifth flip-flop whose output resets the first flip-flop;
The gate circuit is configured to apply the output of a specific stage of the flip-flop constituting the counter or register as a clock pulse and the output of the first or second flip-flop as a left/right shift direction switching signal to the shift register. A timing generation circuit for automatic music selection, characterized in that: