JPS61248136A - Data flow processing device - Google Patents

Abstract

PURPOSE:To reduce vacancy of an arithmetic section and heighten efficiency of processing by inputting data from an outside bus utilizing intervals of output of a data memory. CONSTITUTION:When making ring bus connection, data are inputted from an outside bus utilizing intervals of output of a data memory at the time of waiting of data for dyadic operation which can be expected to occur fairly frequently. By inputting data outputted from the data memory through a link table memory and a function table memory to the second cue memory, disturbance of pipe line processing due to data inputting from an outside bus is eliminated. Thus, by improving efficiency of processing and eliminating complicated control between bus interface and a processor unit and making the scale of hardware, a data flow processing device smaller and cheaper than conventional one is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data flow processing device that connects a memory section and an arithmetic circuit section through a pipeline bus, and controls the order of arithmetic operations in a data flow manner.

(Prior art and its problems) Conventionally, when connecting multiple arithmetic circuits,
There is a data flow processing device as described in No. 169152. As shown in FIG. 4, this device integrates arithmetic circuits into a multi-functional processor unit 7, and connects a link table memory 2, a function table memory 3, a data memory 4, and a queue using a pipelined ring bus. It has a configuration in which a memory 5 and a processor unit 7 are combined. This data flow processing device performs data flow one-way control for binary operations using initially set function table memory 3 and data memory 4. Furthermore, it is provided with a bus interface 7/8 1 that performs input/output with an external bus, and data from the external bus is sent to the link table memory 2 and to the queue memory 5.
The output data from 1 is sent to an external bus.
It is a data flow processing device that is modular and has the characteristic that performance improves according to the number of connections by simply connecting multiple identical modules in series. However, since the configuration shown in FIG. 4 is adopted, when data is input from the external bus, processing of the processor unit 7 must be stopped and data from the external bus must be input preferentially. That is, data input from the external bus does not disturb the pipeline cycle on the internal pipeline bus, which complicates the control between the bus interface l and the processor unit 7. There was a problem in that the scale of the software was large and the price was high.

(Object of the Invention) The object of the present invention is to have a feature that the arithmetic unit having multiple functions can be changed according to the processing, and to prevent frequent occurrence of short circuits when connecting with a ring bus. The data input from the external bus is inputted from the external bus, passed through the link table memory and the function table memory, and outputted from the data memory by using the interval between data memory outputs when waiting for data for a binary operation that can be expected. By eliminating disturbances in pipeline processing caused by inputting data from the external bus, processing efficiency is improved, and complex control between the bus interface and processor unit is eliminated. By reducing the size of the hardware, it is possible to provide a data flow processing device that is smaller and cheaper than conventional ones.

(Structure of the Invention) According to the present invention, there are two input ports for data input from an external bus and data input from a processor unit, and two output ports corresponding to the respective inputs. A link table memory for storing destination addresses, and a function that each has two input and output ports, is accessed individually by the destination addresses of the two outputs of the link table memory, and stores instructions indicating processing contents for input data. a table memory, a data memory each having two input and output ports and temporarily storing input data and constants for one side of a binary operation; a first queue memory that outputs data when there is no output; a second queue memory that waits for output from the data memory and output data from the first queue memory; and the second queue memory. Data input/output between a processor unit that performs a binary operation or a unary operation on the output of and outputs it to the link table memory, a ring-shaped pipeline bus that connects these units, and the pipeline bus external bus. operates the processor unit according to instructions arbitrarily set in the function table memory at the time of initial setting, outputs from the link table memory according to input data from an external bus, and further controls the destination of this data. Data flow processing characterized in that data output from the data memory by data accessed by an address and output from the function table memory is input using a gap between outputs from the other data memory. A device is obtained.

(Example) The present invention will now be described in detail with reference to one drawing.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 is a bus interface, 2 is a link table memory, 3 is a function table memory, 4 is a data memory, 5 is a first middle knee memory, 6 is a second queue memory, and 7 is a processor unit.

Link table memory 2, function table memory 3, data memory 4, first queue memory 5. The queue memory 6 and processor unit 7 of Wg2 are connected in this order in a ring shape by a pipeline bus, as shown in the figure. Further, the link table memory 2, function table memory 3, and data memory 4 are two-port memories each having two input ports and two output ports.

First, various data flowing on the pipeline bus will be explained. Input/output data with the external bus includes module number set data, template set data, template read data, data memory set data, data memory read data, reset data, invalid data, passing data, execution data, error status data,
There is processing data.

The module number set data is composed of only the module number, and is data for setting the module number in the modular number register inside the bus interface 1 at the time of reset. After being set at reset,
The contents of the seven joule number register cannot be changed unless the reset signal is then activated. The contents of the module number register are used for comparison with the module number of data taken into the processing module of this embodiment after reset.

The template data includes a module number, an address of the link table memory 2, a data value written to the link table memory 2, an address of the function table memory 3, and a data value written to the function table memory 3.

Template set data is stored in link table memory 2.
and sets the template data in the function table memory 3. Template data is data that indicates the contents and procedures of processing, and is normally sent from an external host processor to the inside of the processing module of this embodiment, that is, to the link table memory 2 and function table memory 3 as described above, from an external host processor at the start of a series of processing. be transferred.

The template read data is composed of a module number, a link table memory 2 address, and a function table memory 3 address. The template read data is for reading the template data set in the link table memory 2 and function table memory 3, and the module number of the module from which the template data is to be read is entered in the data module number. Furthermore, the template read data can be used to check the contents of the template data in the event that an error occurs. In the template read data, after reading the template data, the read data value is output to the external bus, but the module number at this time is replaced with a specific module number (for example, 1) to distinguish it from other data.

Data memory set data consists of a module number and a data value. Data memory set data is for writing data values into the data memory 4. Addresses used when writing data values to the data memory 4 are those sequentially generated one by one from O within the function table memory 3. The data memory read data consists of a module number and an address of the data memory 4. The data memory read data accesses the data memory using the address of the data memory 4 contained in the data, and outputs the read data value to the external bus.The reset data consists only of the module number, and the processing module of this embodiment If an error condition occurs internally, this is data for canceling this condition.

The error condition includes an overflow error of the first and second queue memories 5.6. When this error occurs,
The data input to the bus interface IK is not taken into the processing module of this embodiment, but is erased. However, when reset data is input to the bus interface 1, the error state is canceled and normal processing is performed from then on. In addition to resetting the error state, the reset data also has the function of initializing the inside of this processing module, and clears the internal counter and memory. The reset data disappears inside the bus interface 1.

Invalid data consists only of a specific module number (for example, 0), and even if this data is input into the processing module of this embodiment, it disappears inside the bus interface 1.

Passing data is data whose module number does not match the contents of the module number register set at reset, is not invalid data, is not module number set data, and is not external data. Data input from the bus passes through the bus interface 1 as is and is output to the external bus.

Execution data is module number, link table memory 2
It consists of the address, control bits, sign bits, and data value. The control bit is set when the calculation result in the processor unit 7 matches a specified condition.

When a branch command is specified in the processor unit 7, the data for which the control bit is set changes the address that refers to the link table memory 2, and is processed differently from the data for which the control bit is not set. Ru. If a diversion instruction is not specified, no processing changes occur, so control bits are normally used with diversion instructions and bare. The branch command is used when it is desired to change the flow of processing depending on the calculation result. The error status data consists of a module number and an error status. The error status data is data for notifying the external bus of the occurrence of an error when an overflow error occurs in the first and second queue memories 5.6 within the processing module of this embodiment. The module number included in the error status data is the read content of the module number register set inside the module in which the error has occurred.

The processing data consists of a module number, an address of the link table memory 2, a control bit, a sign bit, and a data value. The processing data refers to the link table memory 2 and the function table memory 3, and as a result, when it is an output command, the link table memory 2
Then, the module number obtained by referring to the function table memory 3 and the address of the link table memory 2 are added and output to the external bus.

Next, the data flow in the pipeline bus will be explained in detail. The execution data consists of a module number, an address of the link table memory 2, a control bit, a code bit, and a data value, and is taken from the external bus through the bus interface 1 into the pipelined ring bus. Data input from the external bus to the bus interface 1 is added with a use pit inside the bus interface 1 and sent to the M side of the link table memory 2. Also, link table memory 2
Data from the processor unit 7 is input to the IB side of the processor unit 7. The data input to the link table memory 2 is composed of a data value, a reference address of the link table memory 2, a use flag, and a template flag. The use flag is a flag indicating whether data is valid or invalid. If the use flag has a value of 10'', it becomes invalid data. This invalid data passes through the link table memory 2 and is stored in the function table memory 3, It passes through the data memory 4 and the first and second queue memories 5 and 6.
In g-link table memory 2, which disappears before , the ace flag is 11'' and the template flag is 10.
If it is 1, it is regarded as normal processing data, the link table 2 is accessed using the link table memory 2 address included in the processing data, and the read data is sent to the function table memory 3. The input data to the M side of the link table memory 2, that is, the data read out by the data input from the external bus, is output to the 0M side of the S/Q multiple memory 2, and is similarly input to the IB side. The read data (that is, the data output from the processor unit 7) is output to the OB side.

Nice flag is ``1'' and template flag is ``1''
IM", data is written to and read from the link cheap memory 2 using the control pit. The data written in the link table memory 2 is information that distinguishes the processing after referring to the link table memory 2. , an address when referring to the link table memory 2 after data processing in the processor unit 7, an address when referring to the function table memory 3, and data sent to the function table memory 3 are two pairs. It consists of information for distinguishing between each of them when they operate in different ways.

- The function table memory 3 is read by the reference address of the function table memory 3 included in the data read from the link table memory 2. The function table memory 3 mainly stores instruction codes, information for controlling 0 data exchange when two data pairs are operated, the number of output data, and data going out to an external bus. The module number to be assigned, the code information that instructs the processing content in the processor unit 7, the reading and writing of the data memory 4,
Contains information for state management such as data binary queue control and flow rate control. 7 Writing data to the function table memory 3 1 is performed when the template flag is on, and during normal sensing, permanent information whose contents do not change and temporary address information in the data memory 4 are used. It is divided into information.

The function table memory 3 inputs the use flag, template flag, control bit, instruction code, and data exchange signal from the link table memory 2.
A write enable signal is output to the data memory 4. The OA side ratio output data of the link table memory 2 is input to the M side of the function table memory 3, and the OB side small output data of the link table memory is input to the IB side. Also, completely similar processing is performed on both input data.

The data memory 4 includes a queue for temporarily holding the data that arrived first until both data for a binary operation (an operation that uses two types of data as input) is available, and a constant for constant operations. , a lookup table, a transition table for state transition processing, and used to store output data. A write enable signal for the data memory 4 is input from the function table memory 3. When a binary operation instruction is specified and both data are available, input data from function table memory 3 and read data from data memory 4 are output simultaneously. Similarly to the function table memory 2, the data memory 4 also outputs data to the 0M side in response to an input on the M side, and to the OB side in response to an input on the rB side.

The output data on the OA side of the data memory 4 is input to the first queue memory 5, and the output of the first queue memory 5 and the OB side lateral force of the data memory 4 are combined and sent to the second queue memory 6. is input. The first queue memory 5 is used to wait for outputting 1, ie, 0m side output data onto the bus when the OB side is not being outputted, between the OB side small output data of the data memory 4. The state in which the data memory 4 is not outputting means that data disappears in the data memory 4. This is when a write instruction to the data memory 4 is executed, or when one side of a binary operation is made to wait. happen. Therefore, in a normal program, it can be expected that short bursts occur frequently, and by utilizing this disappearance of data in the data memory 4, it is possible to efficiently input data from the outside.

The second cue queue 6 is composed of a data cue and a generator cue. The data queue is a memory for temporarily holding data since the processor unit 7 becomes busy and cannot input data when the number of output data from the processor unit 7 is plural. The generator queue is the startup data for generating numerical values,
The number of data occurrences and control information are input from the data memory to the processor unit 7, and the information is output based on whether the data queue has more than a certain value (half of the data queue in this example) or not. The processor unit 7 is an arithmetic circuit having the functions of arithmetic operations, logical operations, shifting, comparison, bit inversion, prioritization, shunting, numerical value generation, and copying. Bit inversion is a process in which the bit position of an input data value is inverted and the result is an output data value. Priority encoding examines the value of each bit of the input data value in order from the higher priority bit to the lower priority bit, and only when the bit value is
When a bit having a value of 1" appears, the bit position is expressed as a binary integer and is used as an output data value.

The shunt checks the control bit, and if the value is hO'''', outputs the address of the link table memory 2 in the input data as the address of the link table memory 2 in the it output data, and controls it. If the value of the bit is "1", the process is to add 1 to the address of the link table memory 2 in the input data and output it as the address of the link table memory 2 in the output data.

Numerical generation looks at the increment value between the data value in the input data and the number of occurrences, and sequentially adds the increment value for the number of occurrences to the data value in the input data, and generates output data for the number of occurrences. Due to the process that causes this. This function is used when performing repetitive processing or when generating memory addresses. At this time, the address of the link table memory 2 in the output data does not change, and the address t of the link table memory 2 in the input data is output as is.

Copying is a process of looking at the data value in the input data and the number of copies, and then copying the data value in the input data as is to the data value in the output data by the number of copies, and outputting the same. At this time, the address of the link table memory 2 in the output data becomes a value obtained by adding 1 to the address of the link table memory 2 in the input data in the order of output.

The number of input data to the processor unit 7 can be one or two, and the number of output data can be specified from 1 to 16. Processing when the number of input data is one is called a unary operation, and processing when the number of input data is two is called a binary operation. In the case of a unary operation, there is no need to wait because the number of input data is one, but in the case of a binary operation, the operation cannot be executed until two pieces of data are available, so the data that arrives first is stored in the data memory. The data is stored in a binary queue provided in data memory 4, and when data that arrives later arrives, it is stored in the second queue memory together with the data read from the binary queue in data memory 4. 6 starts the calculation in the processor unit 7. That is,
For binary operations, data flow one-way execution control is performed.

When the number of output data from the processor unit 7 is two or more, a busy flag is set while the processor unit 7 is outputting, and input from the second queue memory 6 is prohibited.

FIG. 2 is a block diagram showing in detail the bus interface 1 in FIG. 1. In the figure, 11 is an input latch, 12 is an input buffer memory, 13 is an output buffer memory, 14 is an output latch, 15 is a bus controller, 16 is a reset signal, 17 is a clock signal, 18 is an input request signal, 19 is an input authorization signal, and 20 21 is an output request signal, 21 is an output authorization signal, 22 is an input bus, and 23 is an output bus. When the reset signal 16 is active, the data on the input bus 22 is transferred to the input latch of the bus interface inside the processing module of this embodiment at the rising edge of the reset signal 16 which initializes the inside of the module of this embodiment. Enter the module number register (KMRF) located in the module number register (KMRF). When the reset signal 16 is not active, normal data input/output occurs. Input latch 11 receives data on input bus 22 when input request signal 18 is active. If the module number included in the data latched by the input latch 11 matches the contents of the module number register, the data is stored in the input buffer memory 12, and if they do not match, the data is stored in the input buffer memory 12. passes its data through output latch 14 to the external bus. Certain modules are treated as invalid data. That is, if the module number included in the data latched by the input latch IIK matches the specific module number, the data is considered invalid and is erased inside the input latch 11. A use flag is attached to the data transferred from the input latch 11 to the input buffer memory 12.

When it is desired to input data into the processing module of this embodiment from the external bus, the input request signal 18 is activated and the input data is placed on the input bus 22. Inside the module, input request signal 18 is converted to clock signal 1.
7, latches the input latch IIK, and activates the manual approval signal 19 to notify the external bus that the data on the input bus 22 has been taken over. The input buffer memory 12 is for inputting data from an input latch and temporarily storing it.

The output buffer memory 13 receives data from the data queue inside the second queue memory 6 shown in FIG. 1 and stores the data to be output to the external bus via the output latch 14.
The output latch 14 gives priority to the data to be outputted through the processing module of the present invention, and latches the data from the data queue when there is no data to be passed through as the processed output data. . If there is neither the data to be latched nor the processed output data, the module number assigned to the invalid data is added to the invalid data and output as invalid data to the external bus.

FIG. 3 is a block diagram showing an example in which a plurality of modules are connected by a pipeline-controlled ring-shaped bus when the data flow processing device of FIG. 1 is taken as one module. In the figure, 31 is a host processor;
2 is the main memory, 33 to 36 are modules φ1 to ÷4
shows. Each of the modules 1 to 4 is a module having the configuration shown in the block diagram shown in FIG. 1, and is a host processor. 31 functions as an auxiliary processing device. Loads the module number into the module number register within each module on reset. Among the data flowing on the ring bus, only the data that matches this module number is taken into the module, and other data is controlled so that it passes through without any problem.

First, the initial set data is input to the host processor 31.
It is then sent to each module 33-36. This will now be explained with reference to FIG. This initial set data is
This data is used to initially set data such as commands and control information necessary for processing in the function table memory 3, data memory 4, and link table memory 2. In particular, the data set in the function table memory 3/chipple memory 2 is called a template. The following processing is performed according to this template. Referring again to FIG. It is assumed that data such as image information is input in advance to the main memory 32, the data is read from the main memory 32, processed by each module 33 to 36, and the results are written to the main memory 32. Each of the modules 33 to 36 is connected by a pipeline-controlled bus, and in order to efficiently execute processing, it is necessary to divide and allocate processing to each module according to the processing. Each module has a complex processing function, and since templates can be set from the host and are programmable, the functions can be set according to the processing. If there is no free processing time for all modules and the pipeline is able to be clogged, the most efficient processing can be performed and the processing speed will be faster. Each module has multiple functions, rather than a fixed single function.
Since functions can be set using initial set data, functions can be allocated without waste, and high-speed processing becomes possible. Therefore, with the above configuration, high-speed processing can be easily achieved by simply connecting multiple identical modules in series, making full use of the high-speed performance of the pipeline and the parallel execution controllability of the data flow.

(Effects of the Invention) As explained above, the present invention has the feature that the arithmetic unit having multiple functions can be changed according to the processing, and this problem occurs quite frequently when connecting a ring bus. By inputting data from the external bus using the intervals between data memory outputs where the expected performance can be expected, the pipeline is not disturbed, and by reducing the empty space in the calculation section, processing efficiency is improved compared to conventional methods. A good data flow processing device can be realized. Also, Shihad which is easier to control
'The hardware scale can be reduced, and a data flow processing device that is smaller and cheaper than the conventional one can be realized. Furthermore, only one type of module is required, and T
This is advantageous in JSI. Since it can be configured into nine modules to suit the data flow, it is easy to reduce data collisions on the bus and improve performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a partial block diagram of the bus interface 1 in FIG. 1, and FIG. 3 shows a plurality of FIG. 4 is a block diagram of an example in which multiple modules are connected to a pipeline-controlled ring bus. FIG. 4 is a block diagram showing a conventional embodiment. In the figure, 1 is a bus interface, 2 is a link table memory, 3 is a function table memory, 4 is a data memory, 5 is a first queue memory, 6 is a second queue memory, 7 is a processor unit, and 11 is an input latch. , 12 is an input buffer memory, 13 is an output buffer memory, 14 is an output latch, 15 is a bus controller, 1
6 is a reset signal, 17 is a clock signal, 18 is an input request signal, 19 is an input authorization signal, 20 is an output request signal, 2
11I'i output bus, 31 a host processor, 32 main memories, 33-36 modules φ1-4.

Claims (1)

[Claims] a link table memory having two input ports for data input from an external bus and data input from the processor unit and two output ports corresponding to each input, and storing a destination address of input data; a function table memory each having two input and output ports, which is accessed individually by the destination address of the two outputs of the link table memory, and storing instructions indicating processing contents for input data; and a function table memory each having two input and output ports; a data memory that temporarily stores input data and constants for one side of a binary operation; and a first data memory that waits for data from one side of the data memory and outputs the data when the other side of the data memory does not have an output. a second queue memory for queuing output data from the data memory and output data from the first queue memory; and a binary operation or a unary operation on the output of the second queue memory. a processor unit that performs the processing and outputs the data to the link table memory; a ring-shaped pipeline bus that connects these; and a bus interface that controls data input/output between the pipeline bus and an external bus; operating the processor unit according to instructions arbitrarily set in the function table memory at the time of setting;
data output from the link table memory in response to input data from the external bus, and further output from the data memory in response to data accessed by the destination address of this data and output from the function table memory; A data flow processing device characterized in that input is performed using a gap between outputs from the other data memory.