JPS61245579A - Semiconductor device and making thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD This invention relates to phosphorus and high phosphorus polyphosphate barriers for quantum well devices. More particularly, the invention relates to heterojunction devices, field effect transistors, MESFETs, ring oscillators, two-dimensional electron gas transistors, photodetectors, and lasers that use such barriers.

[Background technology]

Various phosphorus allotropes and high-phosphorus polyphosphate allotropes have larger bandgaps than the binary, ternary, and quaternary claw semiconductors, including pnictides, currently used in quantum well heterojunction devices. Such allotropes can be grown as thin films with good adhesion and interfacial properties to semiconductors such as those mentioned above. U.S. Patent Application No. 4,581,115, filed February 17, 1984.”
Pa5sivationides, Partic
nlarly Amorp'house Pnict
ides Havi-ng a Layer-Lik
e 5tvuctare''.

[Disclosure of the invention]

Phosphorus barrier layers and high-phosphorus polyphosphate barrier layers are a pair of barrier layers that are continuous on top of an intermetallic semiconductor containing a pnictide, such as TnP, when these barrier layers have a band camp larger than the intermetallic semiconductor. can be used in quantum well (heterojunction) devices by depositing . One of the barrier layers is doped, for example with nickel, and the other is undoped. A pair of such layers can be formed on both sides of a semiconductor layer containing pnictide. This structure can be repeated to form a heterojunction device. The barrier layer adjacent to the pnictide-containing semiconductor is undoped, and the next barrier layer is doped to supply electrons to the semiconductor layer. The present invention is applicable to all semiconductors having a bandgap smaller than a typical barrier layer.

OBJECTS OF THE INVENTION One object of the present invention is to provide a quantum well device.

Another object of the present invention is to provide such a barrier to phosphorus and high phosphorus polyphosphates.

Another object of the invention is to provide such a barrier for quantum well devices in which the well semiconductor material includes pnictides, particularly m-v type semiconductors.

Other objects of the invention are partly obvious and partly set forth below.

Accordingly, the invention comprises the features of the elements illustrated in the following figures:
It includes a number of processes having characteristics and relationships, the interrelationship of one or more of such processes, and equipment. The scope of the invention is defined in the claims.

In order to better understand the nature and purpose of the present invention, reference will now be made to the drawings.

BEST MODE FOR CARRYING OUT THE INVENTION Referring to FIG. 1, a single heterojunction device according to the present invention is designated generally at 20. This is 3 layers 22,
It consists of 23.24. Layer 22 is a typical intermetallic semiconductor utilized in such devices, and can be binary, ternary, or quaternary, and preferably comprises a pnictide. Layers 23 and 24 are phosphorus or high phosphorus phosphide barrier layers deposited on semiconductor layer 22. Barrier layer 24 is doped with nickel, for example. This increases its conductivity over that of undoped layer 23 and provides a source of free electrons for layer 22.

Layers 23 , 24 have a larger bandgap than semiconductor layer 22 .

This structure provides a quantum well. According to the band diagram shown in FIG. 2, layers A and B form a barrier generally designated 25. The interface between layers 22 and 23 forms a quantum well as shown at 27 near this interface.

Electron gas can be trapped in this quantum well 27, providing a desired quantum well effect.

In a multiple heterojunction device, such as the device designated at 30 in FIG. 3, the layers are repeated multiple times. namely, intermetallic semiconductor layer 22 and barrier layers 23,24. Furthermore, a similar barrier layer 31 , 32 is arranged on the other side of the semiconductor layer 22 . The other semiconductor layer 33 has on one side a barrier layer 34.32, which layers are equivalent to the barrier layer 23, 24 on the left side of the semiconductor layer 22. semiconductor layer 33
The right-hand barrier layer 35 , 36 has the same composition as the right-hand barrier layer 31 , 32 of the semiconductor layer 22 . Another barrier layer 37 is similar to barrier layer 23 and can be followed by another semiconductor layer (not shown). Similarly, the barrier layer 38 to the left of the layers 23, 24 can be flanked by another semiconductor layer (not shown). This device 30 can thus be repeated in both directions.

The barrier layer labeled "A" is doped to provide a source of electrons. Barrier layers labeled "B" are undoped. Intermetallic or compound semiconductor layers are labeled "C".

Typical thicknesses of the layers are as follows.

A: 100-500 people B: 50-100 people C: 100-500 people These structures can work in fast field effect transistors like MESFETs, ring oscillators, two-dimensional electron gas transistors, photodetectors and lasers.

Preferably, the semiconductor layer "C" includes pnictide so that the barrier layer "B" achieves atomic matching with the pnictide atoms on the surface of the semiconductor layer "C".

In particular, the semiconductor 22 is made of GaAs+TnP, GaP, I
The barrier layer can be made of phosphorus, e.g., monoclinic phosphorus (bandgap about 1.9-2.0 eV), red phosphorus (bandgap about 2.0 eV), etc. .0eV), or the aforementioned U.S. Patent Application No. 5
No. 81.115, a novel form of layered, wrinkled, sheet-like topographical regularity
r-like, puckered sheet-1
ike 1 local order) with a band gap of about 1.7 eV, or the barrier layer can be an alkali metal phosphide (with a band gap of about 1.7 eV) having the formula MPx, where P is phosphorus and 1.7 to 1.8 eV) is preferable.

KP, 5 is a preferred polyphosphate.

The pnictide-containing semiconductor used in our invention is usually
It is called an intermetallic semiconductor or compound semiconductor. Compound,
The m-v group semiconductor, which is an intermetallic semiconductor, is located in the periodic table.
and column 5, such as gallium phosphide, gallium arsenide, gallium antimonide, indium phosphide, indium arsenide, indium antimonide, indium gallium arsenide, indium gallium phosphide, indium aluminum arsenide. , indium gallium arsenide phosphide,
There is indium gallium aluminum arsenide (which has a smaller bandgap than the barrier layer used).

Pnictide means the elements of column V of the periodic table, namely nitrogen, phosphorus, arsenic, antimony, and bismuth.

The helium layer used in the present invention must have good interfacial properties with the intermetallic semiconductor containing pnictide, and must have a larger bandgap than the semiconductor used. Both elemental phosphorus and high phosphorus polyphosphates (MPx, where M is an alkali metal and X is 15 or greater) have these properties. Thus, in one aspect of the invention the barrier layer consists essentially of phosphorus.

It thus appears that the objects set out above, especially those which become apparent from the foregoing description, are advantageously achieved. Additionally, since the methods and apparatus described above may be modified without departing from the scope of the invention, all matter contained in the foregoing description and accompanying drawings should be interpreted as illustrative only and not as restrictive. Should.

Additionally, the claims are intended to cover all of the general and specific features of the invention as described above, and the language of the claims should be construed accordingly.

In particular, it is to be understood that the components or compounds recited in the claims are to be understood not only as individual components, but also as mixtures, to the extent permissible.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view of the quantum well device of the present invention, FIG. 2 is a band diagram of the device shown in FIG.
The figure is a band diagram of the device of FIG. 3. (C) 22.23-Semiconductor layer, CA) 24.32.36--Electron supply layer (barrier layer), CB) 23.3L 34.35.37.3B--Barrier layer. Margin below FIG, I BC Procedural Amendment (Method) June 19, 1985

Claims (1)

[Claims] 1. A) a semiconductor layer made of an intermetallic semiconductor; B) contacting one surface of the semiconductor layer and containing phosphorus and MP_x [in the formula,
M is an alkali metal, and x is 15 or more. a first barrier layer consisting essentially of a material selected from the group consisting of: 2, and C) adjacent to the surface of the first barrier layer far from the semiconductor layer, and having phosphorus and MP_x [wherein M is an alkali metal and x is 15 or more]; 2. A semiconductor device according to claim 1, further comprising a second barrier layer consisting essentially of a material selected from the group consisting of: 3. The semiconductor device according to claim 2, wherein the second barrier layer and the first barrier layer have different conductivities. 4. The semiconductor device according to claim 2, wherein one of the barrier layers is doped. 5. The semiconductor device according to claim 4, wherein the other one of the barrier layers is non-doped. 6. The semiconductor device according to claim 5, wherein the first barrier layer is non-doped. 7, further D) adjacent to the other surface of the semiconductor layer, and containing phosphorus and MP
_x [where M is an alkali metal and x is 15 or more]. 3. A semiconductor device according to claim 2, further comprising a third barrier layer made of a material selected from the group consisting of: 8. The semiconductor device according to claim 7, wherein the conductivity of the first barrier layer and the third barrier layer is different from the conductivity of the second barrier layer. 9. The semiconductor device according to claim 8, wherein doping of the first barrier layer and the third barrier layer is different from doping of the second barrier layer. 10. The semiconductor device according to claim 9, wherein the first barrier layer and the third barrier layer are undoped, and the second barrier layer is doped. 11. The semiconductor device according to claim 7, further comprising: E) a fourth barrier layer adjacent to the other surface of the third barrier layer. 12. The semiconductor device according to claim 11, wherein the first barrier layer and the third barrier layer have different conductivities from the second barrier layer and the fourth barrier layer. 13. The semiconductor device according to claim 12, wherein the doping of the first barrier layer and the third barrier layer is different from the doping of the second barrier layer and the fourth barrier layer. 14, the first barrier layer and the third barrier layer are non-doped, and the second barrier layer and the fourth barrier layer are non-doped;
14. A semiconductor device according to claim 13, wherein the barrier layer is doped. 15. The semiconductor device according to claim 1 or 2, wherein the intermetallic semiconductor contains pnictide. 16. The semiconductor device according to claim 15, wherein the intermetallic semiconductor is a III-V group semiconductor. 17. At least one of the barrier layers has layer-like, wrinkled, sheet-like local regularity.
-kered,sheet-likelocalalord
17. The semiconductor device according to claim 16, wherein the semiconductor device is amorphous phosphorus having er). 18. The semiconductor device according to claim 16, wherein at least one layer of the barrier layer is monoclinic phosphorus. 19. The semiconductor device according to claim 16, wherein at least one layer of the barrier layer is red phosphorus. 20, on an intermetallic semiconductor containing pnictide consisting essentially of phosphorus or MP_x [where M is an alkali metal and x is 15 or more]. ] A method for manufacturing a quantum well semiconductor device, comprising the step of depositing a barrier layer comprising: