JPS61239497A - Method for writing of semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To prevent a damage produced in a thin insulating film and increase the number of rewriting by lowering an electric field impressed on the thin insulating film during writing by impressing plural pulses. CONSTITUTION:Firstly, at a time tw1, VCG1 is impressed and at the next time tw2, VCG2 of voltage is impressed. For instance, if tw1=2msec, VCG1=8v, tw2= Imsec, and VCG1=10V, by initially impressing 8v, an electron is poured into a floating gate electrode 7, so that even when in next 10V is impressed, an electric potential of the floating gate electrode is not enhanced. Accordingly, a high electric field is not impressed to a floating gate oxide film 6 but the damage can be prevented. Such a pulse wave form can be made by providing a pulse wave form forming circuit in a semiconductor nonvolatile memory integrated circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a writing method for a semiconductor non-volatile memory,
In particular, the present invention relates to a method of writing to a semiconductor nonvolatile memory in which deterioration of memory characteristics is reduced by applying a plurality of write voltage pulses.

[Summary of the invention]

This invention relates to a semiconductor nonvolatile memory write method in which hot electrons of a channel current generated by an electric field impressed between a source region and a drain region are injected into a floating gate electrode, and the present invention provides a control method for controlling the potential of a floating gate electrode. By applying a plurality of voltage pulses to the gate electrode with a low pulse height, the deterioration of rewriting characteristics is reduced.

[Conventional technology]

Generally, channel hot electrons are injected into a floating gate nonvolatile memory by applying a high voltage to a floating gate pole. Since this write operation is desirably fast, the voltage pulses on the floating gate pole are always at the same level.

[Problem that the invention seeks to solve]

In a floating gate semiconductor memory, some channel hot electrons are captured by the gate isolation film during writing.
Ru. As a result, if rewriting is performed repeatedly, it becomes impossible to maintain a constant written state.

[Means to solve the problem]

The present invention was devised to solve the above-mentioned problems, and its means are to sequentially change the voltage level from low to high voltage pulses in order to avoid suddenly applying a high voltage to the potential of the floating gate electrode. It is something to be stamped.

[Effect]

During writing, since there is little variation in the floating gate electrode before and after writing, the rewriting characteristics can be improved by widening the injection region and reducing trapping of channel hot electrons in the gate insulating film.

〔Example〕

FIG. 1 shows a cross-sectional view of a floating gate type semiconductor nonvolatile memory. A medium-sized N source region 2 and a drain region 8t are formed on the surface of a P-type substrate 1.
A selection gate electrode 5 and a floating gate electrode 7 are formed in series on the semiconductor substrate between the selection gate oxide film 6t and the selection gate oxide film 6t, respectively. A control gate electrode 9 is formed on the floating gate electrode 7 via a control gate oxide film. floating gate electrode 7
is the floating gate electrode 7 depending on the voltage of the control gate electrode 9.
The potential of is controlled. The memory is a device that stores two states, one in which the channel region under the selection gate electrode is inverted, one in which the channel under the floating gate electrode 7 is inverted, and one in which it is not inverted.

If there are a large number of electrons in the floating gate electrode 7, there will be no inversion. Conversely, when there are not many electrons in the floating gate electrode 7, the state is reversed. A method for injecting electrons into the floating gate electrode 7 will be explained.

When a power supply voltage of 6 mm is applied to the drain region 8 with reference to the potential of the substrate and the source region 2, the channel under the selection gate electrode 5 is weakly inverted, and the channel under the floating gate electrode is strongly inverted. Apply a voltage like this. for example,
When the impurity concentration of the substrate is I x 10", the select gate oxide film thickness is 200 μm, and the floating gate oxide film thickness is 120 μm, the select gate electrode 5 has a threshold voltage of about 27 μm.
A high voltage 107 is applied to the control gate electrode 9 so that the floating gate electrode 7 is sufficiently positively charged and the channel under the floating gate electrode is inverted. The channel potential under selection gate oxide film 4 becomes equal to the potential of the source region, and the channel potential under floating gate oxide film 6 becomes equal to the potential of drain region 8. That is, the potential of the channel region where the selection gate oxide film and the floating gate oxide film intersect is
There is a sudden change from the potential of the source region to the potential of the drain region. High-energy channel electrons are generated in the region and a part of them is injected into the floating gate electrode 7.

According to the writing method for a semiconductor nonvolatile memory as described above, when electrons are injected into the floating gate electrode 7, the floating gate oxidizes 1 g! Since a high electric field is applied to the floating gate oxide film 6, the hot electron injection region is concentrated in a narrow region of the floating gate oxide film 6. The present invention is a method of writing in a state in which the Machihara electric field applied to the floating gate oxide film 6 is weakened by slowing down the rise of the write voltage pulse.

A specific example is shown in the second factor. 2g2 is a waveform diagram of the control gate voltage pulse during writing. First, time tw1
Then vcGlt- is applied and the next time tw! Then V6 e
Apply a voltage of 1. For example, twl=2sage
, vcol = 8 v, twz = engineering #
6. When va o, = 107, electrons are injected into the floating gate electrode 7 by first applying 87 V, so even if 10 V is applied next, the potential of the floating gate electrode does not become very high. A high electric field is not applied to the floating gate oxide film 6, and therefore damage can be prevented. The pulse waveform as shown in FIG. 2 is made possible by providing a pulse waveform forming circuit inside the semiconductor nonvolatile memory integrated circuit. In the case of FIG. 1, the control gate voltage pulse is made up of two pulses with different heights, but damage can be reduced by providing a plurality of pulses.

FIG. 8 is a diagram showing the effects of the present invention. The horizontal axis represents the voltage of the drain region during writing, and the vertical axis represents the threshold voltage of the memory after writing. If the drain voltage during writing is low, high-energy electrons cannot be generated and electron injection into the writing C floating gate electrode cannot be performed, so the threshold voltage is low. When rewriting is performed using the conventional one-pulse control gate voltage, the rewriting characteristics deteriorate as shown in the figure. That is, writing cannot be performed unless a high drain voltage is applied.

However, by rewriting using a plurality of pulses of control gate voltage according to the present invention, the deterioration is extremely reduced. The reason for this is
This is because by applying a plurality of pulses, a high electric field is applied to the thin insulating film and the implantation is injected into the thin insulating film.

The writing method shown in FIG. 2 can be applied not only to the conductive nonvolatile memory shown in FIG. 1 but also to the semiconductor nonvolatile memory shown in FIG. A y+H source region 12 and an M+fiO drain region 13 are formed on the optical surface of the P-type substrate 11, a floating gate electrode 17 is formed on the channel region via a floating gate oxide film 16, and a floating gate electrode 17 is formed on the floating gate electrode. A control gate electrode 19 is formed through a control gate oxide film. Even in such a memory, 57 is applied to the drain region and approximately 1 is applied to the control gate electrode.
27 is applied to inject some electrons of the channel current into the floating gate electrode. Even in such a memory, by applying a pulse waveform of the annual pulse "f:ii" to the control gate electrode as shown in the figure, it is possible to reduce floating gate oxidation and damage due to wear and improve the rewriting characteristics.

The writing method of the present invention as described above can be applied to a semiconductor non-volatile memory in which a part of the electrons of the channel current are injected into the floating gate electrode through a thin insulator to which a high electric field is applied.

〔Effect of the invention〕

The present invention applies multiple pulses on the electric field applied to a thin insulating film during writing in a semiconductor non-volatile memory in which a high electric field is applied to a thin insulating layer to inject some electrons of a channel current into a floating gate electrode. By lowering the voltage applied, damage to the thin insulating film can be prevented and the number of rewrites can be increased.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a memory to which the semiconductor non-volatile memory write method of the present invention is applied, and FIG. 2 is a write control voltage pulse waveform diagram that is the semiconductor non-volatile memory write method of the present invention. . FIG. 8 is a diagram showing write characteristics of a semiconductor nonvolatile memory, and FIG. 4 is a sectional view of another semiconductor nonvolatile memory to which the present invention can be applied. 1, 11, , P-type semiconductor substrate 2, L2. , N+ type source region 8.13. , N+ regular drain region 7.17°, floating gate electrodes 9 , 19 ,. Control gate electrode and above Applicant: Seiko Electronics Co., Ltd. Semiconductor Ihon SennI Tosha Metso Tsuyoshi 1 Figure 1 Genj Wholesale Gate TMNI Leather Carving 1ri No. 212) Ushifu Ihon FR- Volatization Figure 3 of the sex memory book S and the birth chart of the sex memory Figure 4

Claims (1)

[Claims] A source region and a drain region of a second conductivity type different from the first conductivity type provided at intervals on the surface portion of the semiconductor substrate of the first conductivity type, and floating gate insulation in the surface portion of the semiconductor substrate between the source and drain regions. It consists of a floating gate electrode provided through a film, and a control gate electrode provided through the floating gate electrode and a control gate insulating film, and a drain write voltage is applied to the drain region with respect to the source region. , a semiconductor in which a part of the channel current flowing from the source region is injected into the floating gate electrode by applying a control gate write voltage that strongly inverts the surface of the semiconductor substrate under the floating gate insulating film to the control gate electrode. In the non-volatile memory, the control gate write voltage pulse is a first control voltage pulse and a second control gate write voltage pulse.
and a second control voltage pulse having a voltage level higher than that of the control pulse.