JPS61237137A - Interruption controlling system - Google Patents

Abstract

PURPOSE:To realize the flexibility of a degree of a priority by selecting an interruption factor from a group which can be interrupted by the second interruption control mask, in case there is no interruption factor belonging to a group which can be interrupted by the first interruption control mask. CONSTITUTION:The titled system is constituted so than an interruption can be received, if an interruption control mask 11 is '1' even if an interruption control mask 10 is '0', by using the mask 11 and AND gates 20-23, 28-31, and its result is inputted to a priority order determining circuit 40. In this way, even an interruption group which cannot be interrupted by the mask 10 can be interrupted by the mask 11, and also unless an interruption which can be interrupted by the mask 10 is generated, an operation by which an interruption can be recognized is executed through the circuit 40. Also, a number correspond ing to the interruption which is selected by the circuit 40 is sent to an interrup tion address determining circuit 50, and a specified address of a corresponding memory 60 is generated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an interrupt control method used in information processing devices, etc., and more specifically, the present invention relates to an interrupt control method that is provided corresponding to a group of interrupt factors. It controls the acceptance of interrupts and determines the priority order using the interrupt control mask and means for determining the priority order and interrupt address, and has the function of associating a specific address in memory for each group of interrupts. This relates to interrupt control methods.

[Conventional technology]

Conventionally, interrupt control has been realized by hardware, firmware, software, or a combination of these, but the control methods have one thing in common. In other words, interrupt factors are grouped and prioritized, and each group is marked as ``interruptible'' or ``interruptible.''
An interrupt control mask that indicates "interruptible" is provided, and among the generated interrupt factors, the interrupt control mask corresponding to the group to which they belong is given the highest priority among those that are "interruptible". They all have one thing in common: select only the interrupt factor that exists, and associate this factor with a specific predetermined address in memory.

FIG. 2 shows a conventional example in which the above-mentioned functions are realized by hardware. In the figure, 10 is an interrupt control mask indicating "interruptible" or "interruptible", and 32 to
35 is an AND gate, 41 is a priority determining means, 51 is an interrupt address determining means, 60 is a memory, and 70 is an interrupt signal of a plurality of interrupt groups.

In this example, the interrupt control mask 10 includes four interrupt groups INTO, INT1, INT2 .
Four masks corresponding to the INT3 interrupt signal 70,
MO, Ml, M2. M3, and a logic value of "1°" indicates "interruptible" and a logic "0°" indicates "interruptible".

Next, the operation of the conventional system will be explained using the same figure. Four interrupt groups INTO, lNT1. INT
2. The interrupt signals 70 grouped into INT3 are:
Interrupt control mask 10 and respective AND gates 32~
35, and only the interrupt signals of the interrupt groups whose interrupt control mask is logical "1" are valid, and interrupt acceptance is controlled.

A group with a priority of is selected, and a number (0, 1, 2, or 3) corresponding to this group is output.

Note that if no interrupt has occurred, the signal No INT indicating this is activated and no subsequent interrupt operation is performed.

If there is an interrupt that has been accepted, the one with the highest priority is determined by the priority determining means 41 as described above, and its number is input to the interrupt address determining means 51, which is a predetermined number. Specific memory address (INTAO).

INTAL, INTA2. INTA3) is generated.

Thereafter, interrupt processing is performed using the information stored at this specific address.

[Problem that the invention seeks to solve]

Although the interrupt control method described above is widely used, it may not have sufficient functionality in a specific system or in a specific application field.

In other words, in conventional methods, it is impossible to dynamically change the priority once determined, and the period or phase of regular input data may change due to a failure or other cause. However, conventional methods cannot cope with this problem. This is because in conventional methods, processing is performed regularly in response to regular input data, and interrupts are normally not accepted during this time. This is because it cannot cope with changes in phase. In this sense, it can be said that the conventional system had poor responsiveness to change.

This is often a big problem in real-time systems.

Furthermore, when there are many interrupt groups with different priorities, or when interrupt groups with different priorities are added, the conventional system has problems such as the need to increase the number of interrupt signal lines.

The present invention has been made to solve these problems, and improves the flexibility of interrupt priorities, the ability to respond to regular changes in input data, and the feasibility and expandability for increasing the number of interrupt groups. The purpose of this invention is to provide an interrupt control method that can

[Means for solving problems]

The interrupt control method according to the present invention includes a first interrupt control mask and a second interrupt control mask, each of which differs in whether or not an interrupt is allowed for each interrupt group, as interrupt control masks that indicate whether or not an interrupt is allowed, and determines priorities. If there is no interrupt factor that belongs to a group that is enabled for interrupts using the first interrupt control mask, the means belongs to a group that has a higher priority from among the groups that are enabled for interrupts based on the second interrupt control mask. An interrupt factor is selected, and the interrupt determining means associates this interrupt factor with a memory address different from that in the case where interrupts are enabled by the first interrupt control mask.

[Effect]

In the present invention, if there is no interrupt factor that belongs to a group that is enabled for interrupts using the first interrupt control mask, a high-priority interrupt source is selected from among the groups that are enabled for interrupts using the second interrupt control mask. An interrupt factor belonging to the group is selected by the priority order determining means, and the interrupt address determining means associates this interrupt factor with a different memory address than when the interrupt factor is enabled by the first interrupt control mask.

〔Example〕

The present invention will be explained below based on the embodiment shown in FIG. Note that the interrupt control system is also implemented in hardware here, and the same reference numerals are used for the same or equivalent parts as in the conventional example shown in FIG.

In FIG. 1, 10 is a first interrupt control mask;
1 is the second interrupt control mask, 20 to 23 are AND gates that invert the logical value of one input, and 24 to 31 are AN
D gate, 40 is priority determining means, 50 is interrupt address determining means, 60 is memory, 70 is four interrupt groups INTo, 1NT1. INT2. The interrupt signal corresponding to INT3 is shown. The first interrupt control mask 10 includes four masks corresponding to four interrupt signals.
MO, Ml, N2. N3, and the second interrupt control mask 11 similarly has four masks: No, Nl, N2 .
N3, and each of these eight masks has a logic “
A value of 1 indicates "interruptible" and a logic "0" indicates "non-interruptible."

The difference in configuration from the prior art shown in FIG. 2 is that the second interrupt control mask 11 and the associated gates 20 to
3 and 28 to 31, and the number of inputs to the priority determining means 50 has been doubled (from 4 to 8).

Next, the operation of this system will be explained using the same figure.

The first interrupt control mask 10 has four masks corresponding to the four interrupt groups 70, and controls the acceptance of interrupts via the AND gates 24 to 27, and the priority determining means 40. Inputting the results is the same as in the prior art.

In one embodiment of the present invention, in addition to the above-described operation, the second interrupt control mask 11 and the AND gates 20 to 23
and 28 to 31, even if the first interrupt control mask 10 is logic "0", that is, "interruptible", the mask of the second interrupt control mask 11 is logic "1", That is, if the interrupt is "interruptible", the interrupt is accepted, these results are input to the lower part (lower priority part) of the priority determining means 40, and the first interrupt control mask 10 is used. Even in an interrupt group that is marked as "non-interruptible," there are interrupts that are marked as "interruptible" in the second interrupt control mask 11 and "interruptible" in the first interrupt control mask 10. If it has not occurred, the priority determining means 40
Performs an operation in which interrupts are accepted via . The number corresponding to the interrupt selected by the priority determining means 40 is sent to the interrupt address determining means 50, where a corresponding memory specific address is generated. In addition,
If there is no input indicating the occurrence of an interrupt among the inputs of the priority determining means 40, as in the prior art, a signal NOINT indicating this is generated and no further interrupt operation is performed.

In the conventional technology, four special areas were provided in memory for four interrupt groups.
In one embodiment of the invention, eight special areas are provided in memory for the same four interrupt groups. In Figure 2, the address of this special area is INT
Indicated by AO to INTA7. INTAO and I
NTA4 corresponds to interrupt group INTO and
TAL and INTA5 correspond to interrupt group INT1, INTA2 and INTA6 correspond to interrupt group INT2, and INTA3 and INTA7 correspond to interrupt group INT3. As described above, the present invention is characterized in that two memory areas are associated with one interrupt.

If the above embodiment of the present invention is used, two memory areas are associated with one interrupt, so for an interrupt whose priority changes depending on the situation, two
Flexibility is increased because two memory areas can be used differently.

In addition, even if the period or phase of regular input data changes due to a failure or other cause, two memory areas can be used for interrupts corresponding to the regular input data, so one can be used for normal data input. If one is used for interrupts, and the other is used for interrupts that are currently being processed, changes in the cycle or phase can be detected before the process ends, the current process can be interrupted, and the process can be performed in accordance with the new cycle or phase. Therefore, responsiveness to change is improved.

Furthermore, since one interrupt corresponds to two memory areas, one interrupt can handle two different interrupts, and even if the number of interrupts is constant, up to twice the number of different interrupts can be handled. Since this is possible, the problems in the feasibility and scalability of the conventional technology are solved.

In the above embodiment, the number of interrupt groups is limited to four, but there is no particular requirement that this number be used, and the essence of the present invention will not be lost even if the number is arbitrary.

Further, in the above embodiment, implementation is shown in hardware, but this is not limited to this, and as long as an equivalent function is achieved, it may be implemented in firmware, software, or a combination of these. I don't mind.

'Furthermore, the memory areas associated with interrupts do not need to be contiguous, and any association may be used as long as the gist of the present invention is utilized.

〔Effect of the invention〕

As explained above, the interrupt control method according to the present invention is
A first interrupt control mask and a second interrupt control mask are provided as interrupt control masks indicating whether interrupts are allowed or not, and the first interrupt control mask and the second interrupt control mask are different in terms of whether interrupts are allowed or not allowed for each J separate interrupt group, and the priority determining means is configured to select the first interrupt. If there is no interrupt factor that belongs to a group that is enabled for interrupts in the control mask, select an interrupt factor that belongs to a group with a high priority from among the groups that are enabled for interrupts in the second interrupt control mask, and select this interrupt factor. The interrupt determining means associates a memory address different from the case where interrupts are enabled by the first interrupt control mask with respect to the interrupt cause, allowing flexibility in the priority of interrupts and regular changes in input data. This has the effect of significantly improving the adaptability to interrupt groups, the feasibility and expandability for increasing the number of interrupt groups.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 10...First interrupt control mask, 11...
...Second interrupt control mask, 40...
Priority determining means, 50...Interrupt address determining means, 60...Memory. Note that the same reference numerals are used for the middle part of the figure or corresponding parts.

Claims (1)

[Claims] An interrupt control mask that indicates whether or not an interrupt is allowed for each group of interrupt factors that are grouped according to priority, and selects an interrupt factor that belongs to a group with a high priority from among the groups for which this interrupt control mask allows interrupts. and interrupt address determining means for associating the interrupt factor selected by the priority determining means with a specific address set in advance for each group in the memory, and the information stored in the specific address. In the interrupt control method in which interrupt processing is performed using a first interrupt control method, the interrupt control mask includes a first interrupt control mask and a second interrupt control mask, each of which differs in whether or not an interrupt can be allowed for each group, When there is no interrupt factor belonging to a group that is enabled for interrupts using the first interrupt control mask, the priority determining means selects a higher priority one from among the groups that are enabled for interrupts using the second interrupt control mask. Interrupt control characterized in that an interrupt factor belonging to a group is selected, and the interrupt address determining means is configured to associate an address different from that in a case where an interrupt is enabled by a first interrupt control mask to this interrupt factor. method.