JPS6123668B2 - - Google Patents

Info

Publication number
JPS6123668B2
JPS6123668B2 JP54055973A JP5597379A JPS6123668B2 JP S6123668 B2 JPS6123668 B2 JP S6123668B2 JP 54055973 A JP54055973 A JP 54055973A JP 5597379 A JP5597379 A JP 5597379A JP S6123668 B2 JPS6123668 B2 JP S6123668B2
Authority
JP
Japan
Prior art keywords
wafers
wafer
type
thyristor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54055973A
Other languages
Japanese (ja)
Other versions
JPS55148459A (en
Inventor
Kimihiro Muraoka
Makoto Iguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Electric Manufacturing Ltd
Original Assignee
Toyo Electric Manufacturing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Electric Manufacturing Ltd filed Critical Toyo Electric Manufacturing Ltd
Priority to JP5597379A priority Critical patent/JPS55148459A/en
Publication of JPS55148459A publication Critical patent/JPS55148459A/en
Publication of JPS6123668B2 publication Critical patent/JPS6123668B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/74Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7404Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
    • H01L29/7412Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a diode
    • H01L29/7416Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a diode the device being an antiparallel diode, e.g. RCT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10156Shape being other than a cuboid at the periphery

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Thyristors (AREA)

Description

【発明の詳細な説明】 近年の可変電圧可変周波制御技術の進歩に伴
い、その制御装置は大容量化し車輛駆動誘導電動
機にまで応用範囲が拡大しつつある。これに伴い
可変電圧・可変周波制御装置に使用される半導体
素子も大容量化し、かつ特殊定格の素子が必要と
なつて来た。一例として車輛駆動誘導電動機用可
変電圧・可変周波制御装置に使用される半導体素
子でも前記装置の転流用サイリスタは2.5KVの逆
阻止能力を有し、そのターンオフタイムは30μ
secで平均オン電流は200Aであるが、パルス電流
は2000A、通電期間60μsecdi/dtは300A/μsecを
有する特殊サイリスタが要求されている。前記サ
イリスタを通常構造のサイリスタで実現すること
はサイリスタの点弧特性の悪化を招き実使用に耐
えない。
DETAILED DESCRIPTION OF THE INVENTION With the recent progress in variable voltage variable frequency control technology, the capacity of control devices thereof has increased and the range of application is expanding to include vehicle drive induction motors. Along with this, the capacity of semiconductor elements used in variable voltage/variable frequency control devices has also increased, and elements with special ratings have become necessary. For example, in a semiconductor device used in a variable voltage/variable frequency control device for a vehicle drive induction motor, the commutation thyristor of the device has a reverse blocking capacity of 2.5KV and its turn-off time is 30μ.
A special thyristor is required that has an average on-current of 200A in seconds, a pulse current of 2000A, and a conduction period of 60μsec di/dt of 300A/μsec. If the thyristor is implemented as a thyristor with a normal structure, the ignition characteristics of the thyristor will deteriorate and it will not be suitable for practical use.

本発明は前述したような要求を実現するために
なされたものである。本発明は現在車輛用電機子
チヨツパーに使用されている逆導通サイリスタの
サイリスタ部(逆導電形サイリスタ)の特性は、
前述のサイリスタの順方向特性を備えているの
で、この部分を利用すること、即ち2.5KVの高速
逆導電形サイリスタの逆阻止能力を補う方向に
2.5KVの高速ダイオードを直列に一体化すること
により、2.5KVの逆阻止能力を有し、かつサイリ
スタとして点弧特性の優れた前記要求の素子を実
現することが可能となる。
The present invention has been made to fulfill the above-mentioned requirements. The characteristics of the thyristor portion (reverse conduction type thyristor) of the reverse conduction thyristor currently used in vehicle armature choppers are as follows:
Since it has the forward characteristic of the thyristor mentioned above, this part can be used to supplement the reverse blocking ability of the 2.5KV high speed reverse conduction type thyristor.
By integrating a 2.5KV high-speed diode in series, it becomes possible to realize the above-required element that has a 2.5KV reverse blocking ability and has excellent firing characteristics as a thyristor.

本発明の特長とするところは、逆導電形サイリ
スタウエフアの逆阻止能力を補う方向にダイオー
ドウエフアを直列に固着一体化するに際して、同
ウエフアの電圧阻止接合に負ベベルを与えたこと
である。この理由の一つは素子構造面に起因する
機械的な信頼性の向上にあり、他の一つは2.5KV
級高速ダイオードでは正ベベルよりも負ベベルの
方が高温時におけるもれ電流が小さいと言う実験
事実に基き素子の信頼性向上を計つた点である。
A feature of the present invention is that when diode wafers are fixedly integrated in series in a direction that compensates for the reverse blocking ability of the reverse conduction type thyristaulic wafer, a negative bevel is given to the voltage blocking junction of the wafer. . One of the reasons for this is improved mechanical reliability due to the element structure, and the other is 2.5KV
This is based on the experimental fact that leakage current at high temperatures is smaller with a negative bevel than with a positive bevel in class high-speed diodes, in order to improve device reliability.

以下図面により本発明の一実施例について詳細
に説明する。
An embodiment of the present invention will be described in detail below with reference to the drawings.

第1図は本発明の半導体装置の一実施例の縦断
面図であり、本半導体装置1はPNIPN接合を有
する逆導電形サイリスタウエフア2、1つのPN
接合を有するダイオードウエフア3、アノード電
極24およびカソード電極24′が一体化された
ものである。サイリスタウエフア2は高比抵抗の
N形シリコンを母材として、これにP形およびN
形の不純物をそれぞれ選択的に拡散することによ
り、図示のような5つの層が形成される。すなわ
ち、5は高比抵抗のN形母材層、6なN形母材層
より低比抵抗のN形ベース層、7はN形ベース層
6より低比抵抗のP形エミツタ層、8はN形母材
層5より低比抵抗のP形ベース層、9はP形ベー
ス層8より低比抵抗のN形エミツタ層であり、1
0はN形ベース層6とP形エミツタ層7によつて
形成されたアノードエミツタ接合、11はN形母
材層5とP形ベース層8によつて形成された中央
PN接合、12はP形ベース層8とN形エミツタ
層9によつて形成されたカソードエミツタ接合で
ある。サイリスタウエフア2はP形エミツタ層7
および低比抵抗のNベース層6の表面より、サイ
リスタウエフア2のターンオフタイムを短縮する
ため使用目的に応じた金拡散が実施される。P形
エミツタ層7および低比抵抗のN形ベース層6の
表面は、中央支持板22へ金属ろう層23′を介
して低抵抗接触すると共に、さらに金属ろう層2
3を介してダイオードウエフア3と固着してい
る。N形エミツタ層9および低比抵抗のP形ベー
ス層8の表面にはカソード電極24′とゲート電
極21が低抵抗接触で設けられる。ダイオードウ
エフア3はサイリスタウエフア2の逆方向阻止能
力を補うために、その順方向阻止能力と同等もし
くはそれ以上の逆耐圧をもつPN接合18が形成
されており、N形の高比抵抗をもつシリコンウエ
フアの片面よりN形不純物のリンを拡散してN形
母材層15より低比抵抗のN+形層17が、他面
よりP形不純物のボロンを拡散してN形母材層1
5より低比抵抗のP形層16が形成される。ダイ
オードウエフア3の低比抵抗のP形層16よりダ
イオードウエフア3の逆回復電荷を小さくするた
め使用目的に応じた金拡散が実施される。N+
層17はその表面が中間支持板22へ金属ろう層
23により低抵抗接触で固着される。中間支持板
22は薄いP形低比抵抗シリコン板が望ましく、
金属ろう23,23′はアルミニウムを主成分と
した薄い箔が好ましい。
FIG. 1 is a longitudinal cross-sectional view of one embodiment of a semiconductor device according to the present invention.
A diode wafer 3 having a junction, an anode electrode 24 and a cathode electrode 24' are integrated. Thyristauer Fura 2 uses high resistivity N-type silicon as a base material, and P-type and N-type silicon is used as the base material.
By selectively diffusing each type of impurity, five layers as shown are formed. That is, 5 is an N-type base layer with a high resistivity, 6 is an N-type base layer with a lower resistivity than the N-type base layer, 7 is a P-type emitter layer with a lower resistivity than the N-type base layer 6, and 8 is a P-type emitter layer with a lower resistivity than the N-type base layer. 9 is an N-type emitter layer having a lower resistivity than the P-type base layer 8;
0 is an anode emitter junction formed by the N type base layer 6 and the P type emitter layer 7, and 11 is the center formed by the N type base material layer 5 and the P type base layer 8.
A PN junction 12 is a cathode emitter junction formed by a P type base layer 8 and an N type emitter layer 9. The thyristor air 2 is a P-type emitter layer 7
Gold is diffused from the surface of the low resistivity N base layer 6 in accordance with the purpose of use in order to shorten the turn-off time of the thyristor air 2. The surfaces of the P-type emitter layer 7 and the low-resistivity N-type base layer 6 are in low-resistance contact with the central support plate 22 via the metal solder layer 23', and are further in contact with the metal solder layer 2.
It is firmly fixed to the diode wafer 3 via 3. A cathode electrode 24' and a gate electrode 21 are provided on the surfaces of the N-type emitter layer 9 and the low-resistivity P-type base layer 8 in low-resistance contact. The diode wafer 3 is formed with a PN junction 18 having a reverse breakdown voltage equal to or higher than the forward blocking ability of the thyristor wafer 2 in order to supplement its reverse blocking ability. Phosphorus, an N-type impurity, is diffused from one side of the silicon wafer to form an N + type layer 17, which has a lower resistivity than the N-type base material layer 15, and boron, a P-type impurity, is diffused from the other side to form an N-type base material. layer 1
5, a P-type layer 16 having a lower resistivity is formed. In order to make the reverse recovery charge of the diode wafer 3 smaller than the low resistivity P-type layer 16 of the diode wafer 3, gold diffusion is performed depending on the purpose of use. The surface of the N + type layer 17 is fixed to the intermediate support plate 22 by a metal solder layer 23 in low resistance contact. The intermediate support plate 22 is preferably a thin P-type low resistivity silicon plate.
The metal solder 23, 23' is preferably a thin foil mainly composed of aluminum.

サイリスタウエフア2、中間支持板22、ダイ
オードウエフア3は、製造過程で金属ろう23,
23′を上記詳細に説明した図示の順序で重ね合
わせて加熱することにより、それぞれを接着し一
体化される。その後サイリスタウエフア2のカソ
ード電極24′とゲート電極21とは金属マスク
を利用したアルミニウム蒸着により、またダイオ
ードウエフア3のアノード電極24もアルミニウ
ム蒸着により形成される。
The thyristaulic wafer 2, the intermediate support plate 22, and the diode wafer 3 are made of metal solder 23,
23' are stacked in the illustrated order described in detail above and heated to adhere and integrate them. Thereafter, the cathode electrode 24' and gate electrode 21 of the thyristor wafer 2 are formed by aluminum evaporation using a metal mask, and the anode electrode 24 of the diode wafer 3 is also formed by aluminum evaporation.

しかる後、サイリスタウエフア2とダイオード
ウエフア3のそれぞれの周縁部において、それぞ
れのPN接合を斜めに切る端面整形(ベベル)を
行う。サイリスタウエフア2のベベル19はその
中央PN接合(順方向阻止接合)11に対し、表
面電界強度を低減するために設けられる。そのベ
ベル19の傾斜角は、図示されるように不純物濃
度の高いP形ベース層8からN形母材層5の方向
に、その中央PN接合11に対し鈍角をなしてい
るので負ベベルとなつている。ダイオードウエフ
ア3のベベル20はそのPN接合18に対して、
表面電界強度を低減するように設けられる。ベベ
ル20の傾斜角は図示されるように、不純物濃度
の高いP形層16からN形母材層15の方向にそ
のPN接合18に対して鈍角をなす負ベベルとな
つている。
Thereafter, end face shaping (bevel) is performed to diagonally cut each PN junction at the peripheral edge of each of the thyristor wafer fabric 2 and the diode wafer fabric 3. The bevel 19 of the thyristor air 2 is provided with respect to its central PN junction (forward blocking junction) 11 in order to reduce the surface electric field strength. As shown in the figure, the inclination angle of the bevel 19 is obtuse with respect to the central PN junction 11 in the direction from the P-type base layer 8 with a high impurity concentration to the N-type base material layer 5, so it becomes a negative bevel. ing. The bevel 20 of the diode wafer 3 is connected to its PN junction 18,
Provided to reduce surface electric field strength. As shown in the figure, the inclination angle of the bevel 20 is a negative bevel that forms an obtuse angle with respect to the PN junction 18 in the direction from the P-type layer 16 with a high impurity concentration to the N-type base material layer 15.

このようにして形成された本発明の半導体装置
の特徴を次に列記する。
The features of the semiconductor device of the present invention thus formed are listed below.

(1) アノード、カソード両外側面の端面整形部分
を保護するための補強用部材を一切必要としな
いので、簡単な構造となり信頼性が向上する。
(1) Since there is no need for any reinforcing members to protect the end face shaping portions on both the outer surfaces of the anode and cathode, the structure is simple and reliability is improved.

(2) アノード、カソード両外側面の端面整形部分
を保護するための補強用部材が不要のため、補
強用部材を固着するに際して発生するエレメン
トウエフアに対する残留ストレスがなく、耐圧
特性が安定である。
(2) Since there is no need for reinforcing members to protect the end face shaping portions of both the anode and cathode outer surfaces, there is no residual stress on the element wafer that occurs when the reinforcing members are fixed, and the pressure resistance is stable. .

(3) 構成部品がシリコンと薄いアルミニウム層の
みなので、熱ストレス面で安定であり、信頼性
が高い。
(3) Since the components are only silicon and a thin aluminum layer, it is stable in terms of thermal stress and has high reliability.

(4) 構成部品がシリコンとアルミニウムのみなの
で、化学研磨による表面処理が安定しているた
めに、高歩留りで製作が可能である。
(4) Since the component parts are only silicon and aluminum, the surface treatment by chemical polishing is stable, so it can be manufactured at a high yield.

(5) 中間支持板に薄いP形低比抵抗シリコンを使
用することにより、アルミニウムとシリコンの
共晶温度(577℃)近くでダイオードウエフア
のN+形層にアルミニウムを固着できるので、
良好なオーミツクコンタクトが得られる。
(5) By using thin P-type low resistivity silicon for the intermediate support plate, aluminum can be fixed to the N + type layer of the diode wafer near the eutectic temperature of aluminum and silicon (577°C).
Good ohmic contact can be obtained.

(6) ダイオードウエフア、サイリスタウエフアと
も負ベベルを形成するため、高温時においても
れ電流の小さい半導体装置を容易に実現でき
る。高温時におけるもれ電流の差を負ベベルと
正ベベルについて具体的な例で示すならば次の
ようになる。
(6) Since both the diode wafer and the thyristor wafer form a negative bevel, a semiconductor device with low leakage current at high temperatures can be easily realized. A specific example of the difference in leakage current at high temperatures for negative and positive bevels is as follows.

本発明の目的とする特殊転流用サイリスタを
実現するためには、直径50mmのウエフアを必要
とする。用いたサイリスタおよびダイオードウ
エフアの厚みは高速サイリスタであるが故に
2.5KV耐圧が得られる範囲内で極力薄いことが
必要であり、具体的には350μm程度である。
両ウエフアの高比抵抗のN形母材層の厚みはた
かだか250μm程度である。
In order to realize the special commutation thyristor that is the object of the present invention, a wafer with a diameter of 50 mm is required. The thickness of the thyristor and diode wafer used is because it is a high-speed thyristor.
It needs to be as thin as possible within the range that can provide a withstand voltage of 2.5 KV, specifically about 350 μm.
The thickness of the high resistivity N-type base material layer of both wafers is approximately 250 μm at most.

このようにN形母材層の薄い設計の素子で高
温時のもれ電流を少なくするには、例えばダイ
オードウエフアについて説明するならばPN接
合18からN+層17に至る表面路長を大きく
することが極めて有効であることを実験的に見
出したものである。この表面路長を大きくする
ためには正ベベル(一般的にはPN接合18の
整形角度50〜60゜)よりも負ベベル(一般的に
はPN接合18の整形角度3〜5゜)の方が極
めて有利である。
In order to reduce leakage current at high temperatures in a device designed with a thin N-type base material layer, for example, in the case of a diode wafer, it is necessary to increase the surface path length from the PN junction 18 to the N + layer 17. We have experimentally discovered that it is extremely effective to do so. In order to increase this surface path length, it is better to use a negative bevel (generally, the shaping angle of the PN junction 18 is 3 to 5 degrees) rather than a positive bevel (generally, the shaping angle of the PN junction 18 is 50 to 60 degrees). is extremely advantageous.

具体例で比較するならば125℃の温度で25KV
印加時のもれ電流は 負ベベルで整形した素子……40〜60mA 正ベベルで整形した素子……60〜90mA であつた。
To compare with a specific example, it is 25KV at a temperature of 125℃.
The leakage current during application was 40 to 60 mA for the element shaped with a negative bevel, and 60 to 90 mA for the element shaped with a positive bevel.

(7) 本サイリスタは逆導電形サイリスタウエフア
とNエミツタ間にゲート信号を入れて制御する
ので、リモートゲート形のサイリスタよりもゲ
ート信号に対する応答速度が早い。
(7) Since this thyristor is controlled by inserting a gate signal between the reverse conductivity type thyristor air and the N emitter, the response speed to the gate signal is faster than that of a remote gate type thyristor.

ゲート信号に対する応答速度の差を具体的な
例で説明するならば、非リモートゲートを有す
る本半導体装置においては、素子の印加電圧
1.25KVにてゲート信号を入れ、ターンオン動
作を行うと2〜3μsecの時間でターンオンが
終了する。これによつてdi/dt耐量は300A/
μsec以上が確保でき、本発明の目的である逆
阻止能力を有した2.5KV素子でターンオフタイ
ム30μsec、パルス電流2000Aを400Hzで通電で
きる特殊転流用サイリスタを実現することがで
きる。
To explain the difference in response speed to gate signals using a specific example, in this semiconductor device with a non-remote gate, the applied voltage of the element
When a gate signal is applied at 1.25KV and a turn-on operation is performed, the turn-on is completed in 2 to 3 μsec. As a result, the di/dt capacity is 300A/
It is possible to realize a special commutation thyristor with a turn-off time of 30 μsec and a pulse current of 2000 A at 400 Hz using a 2.5 KV element having reverse blocking ability, which is the object of the present invention.

これに対してリモートゲートを採用した実験
例によれば前述と同一試験条件下でターンオン
動作を行うと、ターンオン終了までに7〜15μ
secの時間を必要とした。このためdi/dt耐量
は100〜60A/μsecしか確保できなかつたの
で、本発明の目的である特殊転流用サイリスタ
を実験することは不可能であつた。
On the other hand, according to an experimental example using a remote gate, when turn-on operation is performed under the same test conditions as mentioned above, it takes 7 to 15μ to complete turn-on.
It took sec. As a result, the di/dt withstand capacity could only be secured at 100 to 60 A/μsec, making it impossible to experiment with the special commutation thyristor that is the object of the present invention.

以上詳細に説明したごとく、本発明によつて逆
阻止能力を有する2.5KV級高速度サイリスタにお
いて、優れた特性を備えた半導体装置を提供する
ことが可能となつた。
As explained in detail above, the present invention makes it possible to provide a semiconductor device with excellent characteristics in a 2.5KV class high-speed thyristor having reverse blocking capability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体装置の一実施例の縦断
面図である。 1……半導体装置、2……サイリスタウエフ
ア、3……ダイオードウエフア、24……アノー
ド電極、24′……カソード電極、23,23′…
…金属ろう層、21……ゲート電極、22……中
間支持板。
FIG. 1 is a longitudinal sectional view of one embodiment of the semiconductor device of the present invention. DESCRIPTION OF SYMBOLS 1...Semiconductor device, 2...Thyrist wafer, 3...Diode wafer, 24...Anode electrode, 24'...Cathode electrode, 23, 23'...
...Metal brazing layer, 21...Gate electrode, 22...Intermediate support plate.

Claims (1)

【特許請求の範囲】 1 逆導電形サイリスタウエフアの逆阻止能力を
補う方向にダイオードウエフアを直列に接続し一
体化するに際して、両ウエフアを固着一体化する
ための中間支持板から遠ざかるに従つて両ウエフ
アの外径が減少するような台形構造を有し、且つ
前記逆導電形サイリスタウエフアの電圧阻止接合
と前記ダイオードウエフアの電圧阻止接合とを高
比抵抗層から低比抵抗層に向つてウエフアの外径
が減少するように共に負ベベルに整形したことを
特徴とする半導体装置。 2 逆導電形サイリスタウエフアの逆阻止能力を
補う方向にダイオードウエフアを固着一体化する
に際して、両ウエフアの間に中央支持板として薄
いP形低比抵抗シリコンを使用した特許請求の範
囲第1項記載の半導体装置。
[Claims] 1. When connecting and integrating diode wafers in series in a direction that complements the reverse blocking ability of the reverse conductivity type thyristorue fabric, the distance between the diode wafers and the intermediate support plate for fixing and integrating both wafers increases. The wafers have a trapezoidal structure in which the outer diameters of both wafers are reduced, and the voltage blocking junction of the reverse conductivity type thyristor wafer and the voltage blocking junction of the diode wafer are changed from a high resistivity layer to a low resistivity layer. 1. A semiconductor device characterized in that both wafers are shaped to have a negative bevel so that the outer diameter of the wafer decreases in the direction of the wafer. 2. Claim 1, in which a thin P-type low resistivity silicon is used as a central support plate between both wafers when the diode wafers are fixedly integrated in a direction that supplements the reverse blocking ability of the reverse conductivity type thyristaulic wafers. 1. Semiconductor device described in Section 1.
JP5597379A 1979-05-08 1979-05-08 Semiconductor device Granted JPS55148459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5597379A JPS55148459A (en) 1979-05-08 1979-05-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5597379A JPS55148459A (en) 1979-05-08 1979-05-08 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS55148459A JPS55148459A (en) 1980-11-19
JPS6123668B2 true JPS6123668B2 (en) 1986-06-06

Family

ID=13014012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5597379A Granted JPS55148459A (en) 1979-05-08 1979-05-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS55148459A (en)

Also Published As

Publication number Publication date
JPS55148459A (en) 1980-11-19

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