JPS61236163A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent mask alignment from being displaced and to prevent an oxide film from being side-etched, by forming a polysilicon coating on a hole having a diffusion layer formed therein. CONSTITUTION:A base region 3 is formed on the collector region 2 of the silicon wafer 1 and an oxide film 4 is adhered thereon. Next, three holes 9 are opened at regular intervals, a thinner oxide film 4 is formed, a photo resist 10 is coated thereon and is then photo-etched on the central hole 9 to open a little wide, and the oxide film lying on this section is etched. Next, the photo resist 10 is removed, a polysilicon coating 11 is formed, a photo resist 10 is again adhered thereon, photo etching opens the photo resist 10 only on the central hole 9 a little wide, impurities are ion-implanted, and then thermal diffusion forms an emitter region 6. Thereafter, with being left only on the central hole 9, the other polysilicon coating 11 is removed. Using the coating 11 as a mask, the oxide film 4 is etched and electrodes 12 are formed on the respective holes 9 to finish a high frequency transistor.

Description

Detailed Description of the Invention (a) Technical field The present invention relates to a semiconductor device in which a diffusion layer is formed in a semiconductor substrate such as a silicon wafer, and contact holes are formed in an oxide film on this substrate to form electrodes. Regarding the manufacturing method.

(b) Conventional technology general npn planar, monolithic, bipolar,
An example of a method for manufacturing a transistor is shown in FIGS. 2(a)-(d) and (d)'.

First, as shown in FIG. 2 (81), a base region 3 made of p-type silicon is diffused into the central upper layer of a collector region 2 made of n-type silicon in a silicon wafer 1, and the base region 3 made of p-type silicon is covered with a silicon oxide film 4. Next, as shown in FIG. 2(b), an emitter forming hole 5 having a width S1 sufficiently narrower than the upper surface of the base region 3 is opened in the center of the silicon oxide film 4 by photoetching. Figure 2 (
As shown in C), impurities such as phosphorus are diffused into the silicon wafer l from this emitter forming hole 5, and an emitter region 6 made of n-type silicon is formed below the emitter forming hole 5.
is formed and covered with a silicon oxide film 4. and,
As shown in FIG. 2 (dl), contact holes 7.8 are opened on the emitter region 6 of this silicon oxide film 4 and on the base regions 3 on both sides thereof by photoetching, and electrodes (not shown) are formed therein. However, in this manufacturing method, the emitter formation hole 5 and the contact hole 7.8 must be opened separately using two photomasks, so the transistor is completed as shown in FIG. 2(d). As shown, when a large misalignment occurs in the mask alignment (displacement: d in Figure 2(d)'), the contact hole 7 for forming the emitter electrode opens above the base region 3, causing a short circuit between the base and the emitter. Therefore, in order to prevent such short circuits,
It was necessary to set in advance a mask margin (width=1 shown in FIG. 2(d)) with a sufficient width to compensate for the mask alignment deviation d. Therefore, in this general transistor manufacturing method, a sufficient width mask margin l
In order to provide this, the stripe width of the emitter region 6 (i.e., the width of the emitter forming hole 5 shown in FIG. 2(b):
S+) had to be widened. however,
The stripe width SI of the emitter region 6 influences the high frequency characteristics of the transistor.

High frequency transistors have F as a guideline for high frequency characteristics.
, M, (Figure of Merit) is used, and the larger this value, the better the characteristics. This F
.

M is expressed as follows, where the base collector time constant is rbb'·Cc and the maximum interruption wave number is f.

f? Therefore, in order to obtain a high-frequency transistor with good characteristics,
If the maximum interruption wave number fT is considered constant, the base collector time constant rbb'·Cc must be made small.

Further, if the stripe width of the emitter region 6 is S, the collector capacitance per unit area is Cal, and the base resistance is ro, then F, M.

is expressed as follows.

f? That is, in order to improve the high frequency characteristics of a high frequency transistor, it is necessary to make the emitter stripe width S as narrow as possible and to make the base resistance r1)+collector capacitance C0 as small as possible.

However, in the general method for manufacturing transistors shown in FIGS. 2(a) to 2(d), the emitter stripe width SI must be widened as described above, and as 1) the distance including the mask margin β must be increased. In order to provide the mask margin E, the base resistance r0 also increases, and in addition, in order to provide the mask margin E,
Since the base area increases as a result of the increase in 22, the collector capacitance C0 also increases, making this method unsuitable for manufacturing high-frequency transistors. Therefore, the conventional method for manufacturing high-frequency transistors is shown in Figs. 3(a) to (d).
The washed emitter type shown in (d)′ was adopted.

The manufacturing method for this washed emitter type is as follows:
As shown in FIG. 3(a), a base region 3 made of p-type silicon is diffused and formed in the central upper layer of a collector region 2 made of n-type silicon in a silicon wafer 1, and the base region 3 made of p-type silicon is covered with a silicon oxide film 4. Next, as shown in FIG. 3(b), an emitter forming hole 5 having a width St is opened in the center of this silicon oxide film 4 by photoetching. Next, as shown in FIG. 3C, impurities such as phosphorus are diffused into the silicon wafer 1 through the emitter formation hole 5 to form an emitter region 6 made of n-type silicon under the emitter formation hole 5. . Then, as shown in FIG. 3(d), contact holes 8, 8 are formed by photoetching on the base region 3 on both sides of the silicon oxide film 4, and finally, electrodes (not shown) are formed in each hole 5.8. By forming a high frequency transistor, a high frequency transistor is completed. In this case, the emitter formation hole 5 will also be used as a contact hole for forming the emitter electrode, but the emitter region 6 will be formed not only below the emitter formation hole 5 but also in the lateral direction to some extent during diffusion formation. Actually, the stripe width S of the emitter region 6 is smaller than the width S2 of the emitter forming hole 5! Since this is slightly wider, there is no risk of short circuiting with the base region 3 even if an electrode is formed in this emitter forming hole 5.

In this washed emink type manufacturing method, the emitter formation hole 5 can also be used as a contact hole for forming an emitter electrode, so it is possible to use a large mask such as when opening the contact hole 7 by overlapping the emitter formation hole 5. The margin β becomes unnecessary, and even if there is some misalignment in the mask alignment when opening the contact hole 8 for forming the base electrode, short circuits between the base and the emitter will hardly occur. Therefore, since the width S2 of the emitter hole 5 does not need to be as wide as the width SI of the emitter forming hole 5 shown in FIG. 2(b), the stripe width S2 of the emitter region 6 can also be made narrower. However, even when such a manufacturing method is adopted, when a mask alignment shift d as shown in FIG. Therefore, the base resistance r0 per unit area of the transistor increases. Furthermore, as shown in Fig. 3c)', even if a mask alignment error occurs for opening the base contact hole 8.8, it is necessary to provide at least a margin Il to prevent short circuit with the emitter region. , it was still insufficient to reduce the base resistance r0. For this reason,
Although the conventional method for manufacturing a washed emink type high-frequency transistor can reduce the stripe width St of the emitter region 6 to some extent, it is not possible to sufficiently reduce the base resistance r0 per unit area. There was a limit to the improvement of characteristics.

(C1 Purpose of the Invention The present invention has been made in view of the above circumstances, and it is possible to simultaneously open a hole for forming a diffusion layer and a contact hole for forming an electrode using one photomask. Provided is a method for manufacturing a semiconductor device that can improve high frequency characteristics by eliminating misalignment of mask alignment and preventing side etching of an oxide film by forming a polysilicon film in a hole in which a diffusion layer is formed. The purpose is to

(d) Structure and Effects of the Invention The method for manufacturing a semiconductor device of the present invention includes a hole forming step of opening a plurality of holes in an oxide film on a semiconductor substrate, and an oxide film formation step of forming a thin oxide film on the semiconductor substrate. A photo-etching process in which the semiconductor substrate is covered with a photoresist and the photoresist is opened above some of the holes opened in the oxide film, and a thin oxide film is formed in the hole portions where the photoresist is opened. oxide film etching process to remove the photoresist; polysilicon film forming process to form a polysilicon film on the semiconductor substrate after photoresist removal; An impurity diffusion process to form a diffusion layer in the substrate, a polysilicon etching process to remove unnecessary polysilicon film other than the periphery of the hole from which this thin oxide film has been removed, and a polysilicon film used as a mask for oxide film etching. , removing the thin oxide film in the area covered with the photoresist;
The method is characterized by comprising an electrode forming step of forming an electrode in each hole.

When the method for manufacturing a semiconductor device of the present invention is configured as described above, holes for forming impurity diffusion layers and electrodes can be simultaneously opened in each of the p-type and n-type regions using one photomask. , it is not necessary to set a mass margin, and not only can the stripe width of the impurity diffusion region be sufficiently narrowed, but also the distance between the base and emitter electrodes can be reduced, and the base resistance r0 can be reduced. Furthermore, since the electrode positions do not become unbalanced due to misalignment of the mask, it is possible to prevent the inter-electrode resistance from increasing. In addition, since side etching of the Al film in the holes where the diffusion layer is formed by the polysilicon film can be prevented, the stripe width of the impurity diffusion region can be further narrowed without the risk of short circuits occurring between different regions. Can be done. Therefore, this semiconductor device manufacturing method prevents a decrease in product yield and contributes to improving the high frequency characteristics of transistors, making it an extremely effective invention particularly in manufacturing high frequency transistors.

In addition, since this invention does not cause misalignment of the mask alignment when forming holes, the oxide film does not shift and the semiconductor surface of the semiconductor substrate remains exposed.
A reliable element can be obtained. Furthermore, since mask alignment is not required when removing a thin oxide film and accuracy is relaxed, it is possible to save labor and increase efficiency in the manufacturing process.

(Example 1) Hereinafter, an example in which the present invention is applied to a method for manufacturing a high frequency transistor will be described.

FIGS. 1(a) to (J) each show the present invention as an NPN
This is an embodiment applied to a type transistor, and is a cross-sectional view of a silicon wafer at each step in a method for manufacturing a high-frequency transistor, and shows an actual Brainer transistor in a simplified and schematic manner. It goes without saying that the present invention can be applied to the manufacture of PNP transistors.

First, as shown in FIG. 1(a), a base region 3 made of p-type silicon is diffused into the center upper layer of a collector region 2 made of n-type silicon in a silicon wafer 1, and a silicon oxide film 4 is formed on the base region 3. cover. This base area 3 is
A silicon oxide film 4 having a thickness of about 1000 nm is formed on the collector region 2 made of n-type silicon, and an opening is made in the center of the silicon oxide film 4 by photoetching.
It is formed by diffusing impurities such as boron into the silicon wafer 1 through this opening by vapor phase diffusion or thermal diffusion after ion implantation. Figure 1 (al is after this)
A state in which the opening is covered and closed with a silicon oxide film 4 having a thickness of about 6000 is shown. Next, as shown in FIG. 1(b), holes 9, for example, three in this embodiment, are opened at equal intervals in the center of this silicon oxide film 4 and on both sides thereof. This hole 9 is opened by photoetching, and the figure shows the state after the photoresist is removed. This step corresponds to the hole forming step recited in claim 1. Subsequently, as shown in FIG. 1 (TC), a thin silicon oxide film 4 is formed on the silicon wafer 1. This thin silicon oxide film 4 is formed by chemical vapor deposition or thermal oxidation so that it has a thickness of about 2000 at each hole 9 portion. This step corresponds to the oxide film forming step recited in claim 1. Subsequently, as shown in FIG. 1(d), the silicon wafer 1 is covered with a photoresist 10, and only the photoresist 10 above the central hole 9 is opened slightly wider by photoetching. At this time, the mask alignment of the photomask performed for opening the photoresist 10 is performed so that the opening does not extend to the holes 9 and 9 on both sides, so the width of this opening is set to be smaller than the width of the center hole 9. If the size is sufficiently wide and appropriate, there is no need for particularly high precision, and no inconvenience will occur even in normal work. This step corresponds to the photoetching step recited in claim 1. Subsequently, as shown in FIG. 1(e), the silicon oxide film 4 in the open portion of the photoresist 10 is etched. At this time, by shifting the etching amount by about 3,000 layers, the surface of the silicon wafer 1 is exposed only at the hole 9 portion, and the silicon oxide film 4 still remains by about 3,000 layers around it. This step corresponds to the oxide film etching step described in claim 1. Continuing, Figure 1 (f
), after removing the remaining photoresist 1o, a polysilicon film 1) is formed on the silicon wafer l. This step corresponds to the polysilicon film forming step described in claim 1.

Next, as shown in FIG. 1(g), the silicon wafer 1 is covered with a photoresist 10, and only the photoresist 10 above the central hole 9 is opened slightly wider by photoetching to remove impurities such as phosphorus. This hole 9 is formed by performing thermal diffusion after ion implantation into the silicon wafer 1.
An emitter region 6 is formed below. If there is a risk that the photoresist 10 will harden and become impossible to remove during ion implantation, the process shown in FIG. 1(g) may be omitted and the ion implantation conditions may be set without the photoresist 10. Perform ion implantation. Alternatively, after depositing Sin on the entire surface by chemical vapor deposition between FIG.
0 may be set to 340□. Further, as the polysilicon film 1) formed on the silicon wafer 1, doped polysilicon to which impurities have been added in advance is used, as shown in FIG. 1(f).
By performing direct thermal diffusion from the state shown in Figure 1 (
The emitter region 6 may be formed by omitting the step g). This process of forming emitter region 6 corresponds to the impurity diffusion process described in claim 1. Continuing,
As shown in FIG. 1 (hl), only the polysilicon film 1) on the central hole 9 is left and the other polysilicon film 1) is removed by photoetching. At this time, the mask alignment of the photomask performed for removing the polysilicon film 1) is performed so that the width of the remaining polysilicon film 1) does not extend to the center hole 9. It is sufficient to set the mask to an appropriate size that is sufficiently wider than the width of the mask, and there is no need for particularly high mask alignment accuracy, and no inconvenience will occur even if the mask alignment is performed with normal precision. In addition, in the embodiment, the polysilicon film 1) is formed not only on the central hole 9 but also on the surrounding silicon oxide film 4.
They are also left with sufficient space between them. This is done by leaving as much distance as possible between the wiring part and the silicon surface.
This is to reduce the MO3 capacity. This step corresponds to the polysilicon etching step described in claim 1. Subsequently, as shown in FIG. 1(1), the silicon oxide film 4 other than the remaining portion of the polysilicon film 1) is etched using the polysilicon film 1) as an oxide film etching mask. At this time, the etching amount is 30
By performing a shift roll of about 0.000, the silicon surface is exposed only in the holes 9 on both sides, and the silicon oxide film 4 of about 3000 remains around it. It should be noted that when etching the silicon oxide film 4, a mask is not required during polysiliconing, and a base contact hole is automatically formed without going through a max alignment process. This etching step corresponds to the oxide film etching step using polysilicon as a mask as described in claim 1. Then, as shown in FIG. 1U), an electrode 12 is formed in each hole 9 to complete a high frequency transistor. Note that since the polysilicon film 1) doped with impurities has conductivity, the emitter region 6
Electricity can be passed between the electrode 12 and the polysilicon film 1). This electrode 12 is connected to the silicon wafer 1
It is formed by patterning a photoresist thereon, vacuum-depositing, for example, aluminum thereon, and then removing the photoresist. Note that this electrode 12 is
In addition to the embodiment, it may be formed by partially removing aluminum vacuum-deposited on the entire silicon wafer l by photo-etching. The steps shown in FIG. 1 (1) and U) correspond to the electrode forming step recited in claim 1.

In the manufacturing method of the high frequency transistor of this embodiment configured as described above, the central hole 9 serves as both the emitter formation hole and the contact hole for forming the emitter electrode, and the contact holes for forming the base electrode are also formed on both sides. Since the central hole 9 is formed simultaneously with one photomask, there is no need to set a mask margin, and the polysilicon film 1)
Since the side etching of the emitter region 6 can be prevented, the stripe width of the emitter region 6 can be made narrower than the stripe width 82 of the emitter region 6 in the case of the method of manufacturing a washed emitter type high frequency transistor.

Further, since there is no need to provide a margin for mask alignment deviation when designing the mask, the distance between the base and emitter electrodes can be shortened, and the base resistance r0 can be reduced. Furthermore, since the position of the base electrode does not become unbalanced with respect to the emitter region 6 due to misalignment of the mask, it is possible to prevent the base resistance r0 per unit area from increasing. For this reason, the above F and M. The expression f.

In this case, since the stripe width S of the emitter region 6 can be narrowed and the base resistance r0 per unit can be made small, the values of F and M can be increased and the high frequency characteristics can be improved. Further, in this method of manufacturing a high-frequency transistor, the accuracy of mask alignment is relaxed, so that it is possible to save labor and increase efficiency in the manufacturing process. Furthermore, when forming the electrode 12 in the central hole 9, vapor deposition is performed through the polysilicon film 1), so the electrode material penetrates the emitter region 6 and reaches the base region 3 due to the spike phenomenon. There is no fear of a short circuit between emitters, and a decrease in product yield can be prevented.

[Brief explanation of the drawing]

FIGS. 1(a) to (J) are cross-sectional views of a silicon wafer at each step in the method for manufacturing a high-frequency transistor according to an embodiment of the present invention, and FIGS. 2<8) to (d) are, respectively, A cross-sectional view of a silicon wafer at each step in a general transistor manufacturing method, FIG. 2(d)' shows a silicon wafer when the mask alignment in the step of FIG. Figures 3(a) to 3(d) are cross-sectional views of a silicon wafer at each step in the conventional high-frequency transistor manufacturing method, and Figure 3(d)' is a cross-sectional view of the same high-frequency transistor manufacturing method. FIG. 3 is a cross-sectional view of a silicon wafer when the mask alignment in the step of FIG. 3(d) is misaligned. 1-Silicon wafer (semiconductor substrate), 4-Silicon oxide film (oxide film), 6-Emitter region (diffusion layer), 9-Hole, 10-Photoresist, 1)-Polysilicon film, 12-Electrode.

Claims (1)

[Claims] (1) A hole forming process in which multiple holes are opened in an oxide film on a semiconductor substrate, an oxide film forming process in which a thin oxide film is formed on this semiconductor substrate, and a photoresist is covered on this semiconductor substrate to form an oxide film. A photo-etching process to open the photoresist above some of the holes opened in the hole, an oxide film etching process to remove the thin oxide film in the hole portion of the photoresist, and after removing the photoresist, A polysilicon film formation process in which a polysilicon film is formed on the semiconductor substrate, an impurity diffusion process in which a diffusion layer is formed in the semiconductor substrate below the hole where the thin oxide film has been removed from the hole opened in the oxide film, and A polysilicon etching process to remove unnecessary polysilicon film other than the periphery of the hole from which the oxide film has been removed, and etching the oxide film in areas not covered with the polysilicon film using the polysilicon film as a mask for oxide film etching. 1. A method for manufacturing a semiconductor device, comprising: a step of forming an electrode in each hole; and an electrode forming step of forming an electrode in each hole.