JPS61236150A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a required high resistance resulting from large intrinsic resistance amorphous silicon irrespective of making a device minute, and to fabricate the high resistance element easily in the same way as a planar structure resistance, by constituting the high resistance element employing amorphous silicon. CONSTITUTION:In a contact hole, an amorphous silicon layer 17 with a thickness of several hundred Angstrom and about the same planar dimensions as the hole is formed, being connected with an N-type region 11. This amorphous silicon layer 17 constitutes a high load resistance 5 on which an inter-layer insulating film 18 such as PSG is formed, and is connected with a wiring layer 20 such as aluminum via the through hole 19 bored through the insulating film 18. The amorphous silicon layer 17 is as high as 1X10<10>OMEGAcm in intrinsic resistance, in order to attain a required high resistance only by the thickness. Thus, only by putting the amorphous silicon layer 17 vertically between the N-type region 11 and aluminum wiring layer 20, a high resistance 5 can be constituted.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device having a high-resistance element in a part of a circuit, and particularly to a semiconductor device in which the high-resistance element is miniaturized to improve the degree of integration. be.

[Background technology]

2. Description of the Related Art In a semiconductor device having a high resistance element in a part of a circuit, such as a static RAM (SRAM), intrinsic polycrystalline silicon to which no impurity is introduced is used for the high resistance element as a load resistance. This intrinsic polycrystalline silicon has a fixed resistance (specific resistance) of about 4 x 10' [Ωcm], and when the polycrystalline silicon layer is formed to have a length of 5 μm, a width of 2 μm, and a thickness of 0.2 μm, it is approximately 5 μm.
A resistance of x l Q l lΩ can be obtained.

However, with the miniaturization and high integration of semiconductor devices in recent years, there has been a demand for miniaturization of resistive elements, and the dimensions such as length, width, and thickness mentioned above are also constrained, and the required high resistance It becomes difficult to obtain a value, and it becomes impossible to keep up with the increase in the degree of integration of semiconductor devices.

For this reason, the present applicant first formed a deep narrow groove in a semiconductor substrate, buried polycrystalline silicon in this groove, and utilized the depth of the polycrystalline silicon groove to create a semiconductor with high resistance. We are proposing a device (Patent Application No. 113003/1989)
. According to this resistor element structure, the depth can be made sufficiently large compared to the planar area of the groove, so that the necessary high resistance can be obtained while miniaturizing the semiconductor element.

However, in this structure, the process of forming a deep narrow groove, the process of burying polycrystalline silicon in this groove, etc. are relatively complicated and involve a large number of processes.

[Purpose of the invention]

The purpose of the present invention is to obtain a necessary high resistance value while configuring a high resistance element with a conventional planar structure, thereby simplifying the manufacturing method, and achieving miniaturization and high integration of the element. The object of the present invention is to provide a semiconductor device that can perform the following functions.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by constructing a high-resistance element using amorphous silicon, it is possible to obtain the necessary high resistance value due to the large specific resistance of amorphous silicon regardless of the miniaturization of the element, and it is possible to obtain the required high resistance value due to the large specific resistance of amorphous silicon, and also to manufacture it without using conventional methods. It can be easily manufactured like a planar structure resistor.

〔Example〕

1 and 2 show an embodiment in which the present invention is applied to a static RAM, and in particular, four MO5 field effect transistors 1,
2.3.4 and a pair of high resistances 5 and 6 for the load, MO
FIG. 1 shows the cross-sectional structure of the 3-type field effect transistor 1 and the high resistance portion 5. As shown in FIG.

In these figures, N shadow regions 11°11 doped with N-type impurities are formed on the main surface of a P-type silicon substrate 10 as source/drain regions, and a gate insulating film 12 made of silicon oxide provided on the upper surface thereof is formed. A polycrystalline silicon gate 13 is formed on the MO3 field effect transistor 1.
It consists of

A glabellar insulating film 14 made of thermally oxidized silicon or the like is formed on the MO3 type field effect transistor 1, and this glabellar insulating film 1
4, a contact hole 15 is formed in the N shadow area 1.
Part of 1 is exposed. Then, a polycrystalline silicon layer 16 introduced with impurities to lower the resistance is extended into the contact hole 15 and connected to the N shadow region 11, and used as a wiring layer to form another MO5 shown in FIG. It is connected to the type field effect transistors 2 and 3 by wiring.

Further, an amorphous silicon layer 17 having approximately the same planar dimensions as the contact hole 15 and several hundred layers thick is formed over the contact hole 15 and connected to the N shadow region 11 . This amorphous silicon layer 17 constitutes the high resistance 5 for the load, and a glabella insulating film 18 made of PSG (phosphosilicate glass) or the like is provided on it, and aluminum or the like is passed through a through hole 19 made in this. It is connected to the wiring layer 20 of.

The amorphous silicon layer 17 is formed by CVD, for example, which decomposes monosilane (S i Ha ) by glow discharge.
It can be deposited by a method. The amorphous silicon layer 17 thus formed has a specific resistance of lXl01o (9 cm), which is extremely high compared to polycrystalline silicon, and is formed to a thickness of several hundred to several thousand layers as in this example. In the amorphous silicon layer 17, the necessary high resistance value can be obtained only in the thickness direction. As a result, in FIG. 1, the N shadow region 11 and the aluminum wiring layer 20
By simply sandwiching the amorphous silicon layer 17 between the upper and lower sides, a high resistance 5 having the same resistance value (5 x 10''Ω) as the conventional one can be constructed.

Note that heating amorphous silicon to a temperature of 500° C. or higher is not preferable due to its amorphous nature, so it is important to avoid heat treatment at temperatures higher than this in subsequent steps as well.

According to the above structure, since the high resistance of the memory cell of the static RAM is formed by the amorphous silicon layer 17, the necessary high resistance value can be obtained simply by utilizing the thickness of the amorphous silicon layer 17. . That is, by sandwiching the amorphous silicon layer 17 between the N shadow region 11 and the aluminum wiring layer 20', a resistance value corresponding to the thickness of the amorphous silicon layer 17 can be obtained between the two. This resistance value is the amorphous silicon layer 1
By setting the thickness of 7, it is possible to take an arbitrary value, and by setting the plane area, the withstand voltage, etc. can be set. For this reason,
The high resistance 5 can be sufficiently used even in a fine shape, and the plane area for constructing the high resistance 5 can be reduced to keep up with the miniaturization and high integration of elements.

On the other hand, amorphous silicon has a larger band gap than polycrystalline silicon (amorphous silicon 1.5-1.8eV, polycrystalline silicon 1°2eV).
, the dark current passing through this high resistance 5 can be reduced,
It can be advantageous in terms of power consumption and memory retention.

Further, when manufacturing the high resistance 5, it is only necessary to deposit an amorphous silicon layer and pattern it, so there is no need to form deep narrow grooves, and the manufacturing can be performed extremely easily.

Note that after forming the amorphous silicon layer 17, high-temperature heat treatment is avoided, so that the amorphous silicon layer 1
There is no need to consider the influence of autodoping on 7 due to phosphorus (phosphorus emitted from PSG, etc.) and other impurities.

〔effect〕

(1) Since the high resistance that makes up part of the circuit is formed using amorphous silicon, its specific resistance is higher than that of polycrystalline silicon, making it possible to achieve the necessary high resistance value even in a small plane area. This makes it possible to cope with miniaturization and high integration of semiconductor devices.

(2) Since the required resistance value can be obtained only by the thickness of the amorphous silicon layer (in the vertical direction), the resistance value can be set to any value simply by controlling the thickness, and the resistance value can be set to any value by simply controlling the thickness. It is also possible to reduce the occupied plane area and increase the degree of freedom in layout of other wiring layers, other elements, etc.

(3) Since the withstand voltage of the resistor can be set depending on the planar area of the amorphous silicon layer, a resistor with an arbitrary withstand voltage can be configured even with a fine shape.

(4) Since amorphous silicon has a larger band gap than polycrystalline silicon, it has less dark current and is advantageous in terms of power consumption and memory retention.

(5) Since high-temperature heat treatment is avoided after forming a high-resistance amorphous silicon layer, there is no need to consider autodoping into the amorphous silicon (and the resistance value can be stabilized).

(6) Since high resistance can be formed by the same amorphous silicon layer deposition and patterning process as in the past, there is no need to form deep narrow grooves, and manufacturing is extremely easy.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, high resistance can of course be achieved by utilizing the resistance in the planar direction of the amorphous silicon layer, as in the case of conventional polycrystalline silicon. In addition to the methods described above, various methods that have been proposed so far can be used to manufacture amorphous silicon.

[Application field]

The above explanation will mainly focus on the static RAM, which is the field of application for which the invention was made by the present inventor.
Although the present invention has been described with reference to the case where the present invention is applied to memory cells, particularly those with high resistance, the present invention is not limited thereto, and can be applied to all semiconductor devices having high resistance in a part of the circuit.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a memory cell thereof. 1.2, 3.4...MO3 type field effect transistor,
5, 6...High resistance, 10...Silicon substrate, 11.
...N shadow region, 13...gate, 14...interlayer insulating film (silicon oxide), 15...contact hole, 16...polycrystalline silicon wiring layer, 17...amorphous silicon layer, 18 ...Interlayer insulation film (PSG),
19...Through hole, 20:...Aluminum wiring layer.

Claims (1)

[Scope of Claims] 1. A semiconductor device having a high resistance element in a part of the circuit, characterized in that amorphous silicon is used for the high resistance element. 2. The semiconductor device according to claim 1, wherein the high resistance element is a load resistance of a static RAM. 3. The semiconductor device according to claim 1 or 2, wherein the high resistance element is a resistance in the thickness direction of amorphous silicon formed in the form of a film.