JPS61236139A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To secure the thickness needed for the P-type well and to contrive to actuate an N-type MOS transistor at a higher-speed by a method wherein N-type and P-type buried layers are formed on the semiconductor substrate, and after that, the treatment to lower the impurity concentration of the surface part of each P-type buried layer is performed before the epitaxial growth is performed. CONSTITUTION:Ion-implanted layers 6 are formed at the sites other than N-type buried layers 4. These layers 6 are activated and are formed as P-type buried layers 8. When an epitaxial growth is performed thereon at about 970 deg.C using SiH4 gas, an epitaxial layer 9 is formed. With the growth of this epitaxial layer 9, the impurity of each N-type and P-type buried layer 4 and 8 is diffused upward, the swell-up of each buried layer 4 and 8 is generated and the thickness thereof is augmented. At this time, each P-type buried layer 8 is suppressed its swell-up amount by a lowering in the impurity concentration of its surface part and the swell-up amount is suppressed to nearly the same degree as that of each N-type buried layer 4.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a method for improving semiconductor devices, particularly for Bi-CM
The present invention relates to a method of manufacturing an O8 type (bipolar/MOS mixed type) semiconductor device, which aims to increase the speed of MOS transistor operation and miniaturize the elements.

[Background technology]

Bipolar transistor and MO on one semiconductor substrate
The so-called 13i, which is an integrally formed 8-type transistor.
- A CMO8 type semiconductor device was proposed by the applicant of the present application (Japanese Patent Application Laid-Open No. 59-94861), and progress is being made in Jishu Kita. Figure 5 is an example of this, with one P-type silicon substrate]
An Nff1 buried layer 4A and a P type buried layer (isolation layer) 8A'Y type are formed on top, and an epitaxial layer 9A is grown on these layers.
A W well 14A is formed, and a bipolar transistor Qn is placed therein.

P-type MO8) transistor Qp, N-type MO8) transistor QN! Form each... Bipolar transistor Q
B consists of an N-type collector layer 18A, a P-type base layer 19A, and an N-type emitter layer 20A. It is composed of drain regions 21A and 22A.

By the way, Bi-MOS (B i −
0MO8) In the semiconductor device, antimony (Sb) and arsenic (As) are used as impurity species in the four N-type buried layers, and P
Boron (B) is used as an impurity in the mold buried layer 8A.

Therefore, when forming the epitaxial layer 9A' by monolithic growth on each of the buried layers 4A and 8A, N, Pli
fj Impurities in the buried layers 4A and 8A are diffused (autodoping) onto the epitaxial layer 9A during epitaxial growth, resulting in a phenomenon in which the thickness of each buried layer 4A and 8A increases upward by 1lIc, a so-called "rise". known to occur. However, when this "wakiari" occurs,
The diffusion rate of the N-type impurity and the P-type impurity described above is significantly different, and the diffusion rate of boron is much higher than that of antimony and arsenic. 4A, and as a result, the thickness of the P-type well 14A formed on the P-type buried layer 8A becomes smaller as shown in the figure.

For this reason, Nff1M formed in Paquel 14A
08) The junction capacitance of transistor QN increases, and this M
OS) A problem arises in that the operating speed of the transistor QN is reduced. In order to ensure that the thickness of the Pal well 14A is the required thickness, it is possible to adjust the epitaxial growth conditions, but this adjustment is extremely difficult, and this makes it possible to reduce the thickness of the N-type well 14A. becomes large, and particularly the high frequency characteristics and breakdown voltage of the bipolar transistor QB are degraded. In addition, the epitaxial layer 9
Increasing the thickness of A itself is disadvantageous in terms of miniaturization of isolation.

Note that it is not preferable in terms of device characteristics to change the impurity concentration by changing the amount of impurity doped into the buried layers 4A and 8A.

Furthermore, the buried layer between the N-type and P-type is an essential and important layer because it has the role of lowering the soil resistance value in that part and preventing the latch-up phenomenon peculiar to 0MO8.

As mentioned above, the reduction in the operating speed of the MOS transistor QN occurs when the MOS transistor Qs'y' is used as a transistor for holding information in the memory cell.Memory 1. The speed of C itself is reduced.0 The applicants of this application have developed a static random access memory (Static R) using Bi-CMO8 technology.
andom Access Memory SRAM
) is being developed. This SRAM is the memory part'k
It is formed of NMOS transistors (high resistance load type NMOS memory cells), and its peripheral circuits, such as the ing. This Bi-CMO8 technology uses a bipolar output transistor with a large drive capacity to drive an output transistor that needs to drive wiring with a large load capacity or an output transistor with a large fan-out, so the load capacity v can be charged and discharged at high speed. On the other hand, since the logic function uses CMO8V, it is possible to reduce power consumption.

By adopting this technology, high speed and low power consumption SRA
M can be provided, but the present invention provides a memory cell section and
The aim is also to improve the speed of the NMOS transistor in the M08 section.

[Purpose of the invention]

The purpose of the present invention is to make the thickness of the N-type buried layer and the Pfi buried layer approximately equal in a Bi-MQS type semiconductor device, thereby ensuring the thickness of the Pffiff mirael, so that the operation of the N-type MO8) transistor is achieved. In addition to improving the high-frequency characteristics of bipolar transistors by preventing an increase in the thickness of the N-type well, it also aims to improve the speed and miniaturize the isolation by preventing the epitaxial layer from becoming thicker than necessary. It is an object of the present invention to provide a backdoor method for semiconductor devices that can achieve the following.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

Summary of the Invention] A brief summary of representative inventions disclosed in this application is as follows.

That is, after forming N-type and P-type buried layers on a semiconductor substrate and before performing epitaxial growth, a process is performed to reduce the impurity concentration at the surface of the P-type buried layer, thereby increasing the epitaxial growth time. The rise of the P-type buried layer can be suppressed to the same level as the N-type buried layer, making the thickness of the P-type buried layer approximately the same as that of the N-type buried layer, and ensuring the required thickness t of the P-type well. In order to speed up the operation of N-type MOS transistors.

and improvement of high frequency characteristics of bipolar transistors.

It is possible to achieve finer isolation and prevention of latch-up.

The process for reducing the impurity concentration on the surface of the P-type buried layer can be performed by forming an oxide film on the surface and removing it, or by subjecting the surface to hydrogen reduction treatment.

〔Example〕

1A to 10 show an embodiment in which the present invention is applied to a manufacturing process of an 8-fold MO8 (bipolar/complementary MO8 mixed) type semiconductor device.

First, as shown in the figure, on the surface of the P-type silicon substrate 1,
EL a (S i Ot Ml ) 2 nitride film (Si, N.

After forming film) 3, a mask for N-type buried layer (not shown) is applied.
Patterning is done using photolithography technology. Then, this SiQ, film 2 and Si3N, film 3
S b on the surface with a t mask! By depositing the Os film and heat-treating it for about 45 minutes, an N-type buried layer 4 can be formed, and a 5iQ1 thick film 5 is formed on its surface.
(See the same figure) can be formed.

Said Si3N4 film 3'lj! : After removal, same figure 03)
Boron'% on the entire surface like: 50 Kev, I
Ion implantation is performed at a rate of X 10 ''/c to form an ion implantation layer 6 in a region other than the N-type buried layer 4. Then,
Said Sin.

After removing the film 5, the entire ftrI1. After heat treatment in an elementary atmosphere, a thick Sin film 7Y is applied to the entire surface of the process 5 of
Form. At this time, the ion implantation layer 6 is activated and formed as a P-type buried layer 8. Also, at this time, as will be described later, the boron implanted into the substrate 1 as the ion implantation layer 6 is sucked out from the surface by Si□, $7,
As a result, the impurity concentration at the surface of P-type buried layer 8 is reduced.

If epitaxial growth is then performed at about 970° C. using SiH4 gas, an epitaxial layer 9 of about 1.5 μm is formed on the substrate 1 as shown in ) in the same figure. Along with the growth of this epitaxial layer 9, N-type and P-type buried layers 4
, 8 are diffused upward, causing each buried layer 4.8 to bulge and its float to increase. At this time, the amount of rise of the P-type buried layer 8 is suppressed due to the reduction in the impurity concentration in the surface portion, and is suppressed to approximately the same level as that of the N-type buried layer 4.

Next, as shown in ■ in the same figure, SiQ, film 10 and S
An i, N, film 11 is formed and patterned using a mask for forming an N well (not shown).

And this t mask is Rin (P) 5'125Ke
The N-type well 12 is formed by implanting ions with V, 3 x 10''/c and heat treatment at 1000°C for about 200 minutes in an oxygen atmosphere.At the same time, the N-type well 12 is formed as shown in [F] in the same figure. , SiQ on the N-type well 12
, the storage space 13 can be formed, and the S r 3 Na film 11
Boron 60 Key after removal, 8 x 10”
/C- by ion implantation and heat treatment.
A mold well 14 can be formed.

Hereinafter, in the same figure (as shown in O), the element isolation S
iQ, film 15, gate electrode 16, 17, N-type collector layer 18, P-type base Jii 19, N-type emitter layer 20, P
By forming the N type and N type source/drain regions 21 and 22, the interlayer insulating film 23, and the AJ wiring 24, the N type
Bipolar transistor QmlP type M in type well 12
O8) A transistor Qp is placed in an N-type MO in the P-type well 14.
8) Langista QN! B I -CMO8 formed respectively
type semiconductor device can be constructed.

According to the above, after forming the boron ion implantation layer 6 to form the P-type buried layer 8, the surface KSiQ of the substrate 1! Membrane 7
When 5iQ1 film 7 is formed and heat treated during or after the formation, impurities (holo y) kt from the surface
The concentration distribution of boron in the P-type buried layer 8 becomes busy as shown in FIG. The concentration on the surface area is the conventional value (4X 1
0” cm-3) lower than the bottom (4X 10”
cm7"). At this time, in the N-type buried layer 4, there is little suction of antimony as an impurity.
), the concentration of st is diffused from the surface into the epitaxial layer 9, causing so-called "swelling." However, although the impurity in the P-type buried layer 8 is boron, which has a high diffusion rate, the concentration at the surface is low. ℃, the amount of rise is suppressed, and as mentioned above, the amount of rise is suppressed to approximately 8B, which is the same as the amount of the N-type buried layer 4.

As a result, the thickness and depth of the P-type well 14 formed in the epitaxial layer 9 can be made thicker than before, and the junction capacitance ta' of the N-type MOS transistor QN formed in the P-type well 14 can be reduced. On the other hand, even if the thickness of the P-type well 14 is increased, the thickness of the epitaxial layer 9 remains the same as before, and the thickness of the N-type well 12 is <<m<>. Therefore, good high frequency characteristics of the bipolar transistor QB can be ensured.

l! In some cases, the epitaxial layer 9 can be made thinner than before, and the bipolar transistor Q
! It is possible to improve the high frequency characteristics of +, and it is also effective in miniaturizing isolation errors.

On the other hand, when forming the N-type buried layer 4 and the N-type well 12, the mask M4 for the N-type buried layer is formed larger than the mask MIm for the N-type well as shown in FIG. Even if an error occurs in the alignment of each mask M4 m M, , the N-type well 12 is connected to the N-type buried layer 4 as shown in the figure [F]).
It never goes outside. In this respect, as shown in FIG. 4, the N-type buried layer mask M4 and the N-type well mask 2M1. Because they were formed to have approximately the same dimensions, the N-type well 12 may protrude from the N-type buried layer 4 and protrude onto the P-type buried layer 8 due to alignment error, as shown in the same figure. easy. In such a state, bunch-through flu occurs due to autodoping between the P-type impurity layer 25 formed in the N-type well 12 and the P-type buried layer 8, and for example, the base-substrate breakdown voltage of a bipolar transistor is reduced. Problems such as a decrease in the voltage and a decrease in the withstand voltage between the drain and the substrate in the P-type MO8 transistor will occur. In contrast,
Such a problem does not occur in this example. Note that on the opposite side of the mask, a state in which the P-type well 14 protrudes above the N-type buried layer 4 occurs as shown in FIG. Impurities (sb.

As and P) are difficult to cause autodoping, so there is no problem of reduced breakdown voltage.

〔effect〕

(1) When forming an epitaxial layer on the P-type and N-type buried layers, treatment is performed to reduce the impurity concentration at the surface of the P-type buried layer before epitaxial growth. Is it possible to suppress the rise of the mold buried layer and the need for a P-type well? ! By securing @saya1', the junction capacitance of the N-type MOS transistor formed within this P-type transistor can be reduced, and the operating speed can be improved.

(By oxidizing the surface of the 21P type buried layer, the concentration of impurities on the surface portion is reduced, so the objective can be easily achieved without increasing the number of steps.

(3) Since the rise of the P-type buried layer is effectively suppressed, the N-type well above the N-type buried layer does not become deep, and the high frequency of the bipolar transistor formed in the N-type well Characteristics can be improved.

(Even if the 41 epitaxial layer is made thinner, the required depth of the P-type reel can be ensured, so that @ during isolation can be made smaller to achieve finer isolation.

(5) Since the mask for the N-type buried layer is larger than the mask for the N-type well, it is possible to prevent the N-type well from protruding even due to alignment errors, improving the device's breakdown voltage and improving reliability. It is possible to achieve improvement in retention.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, as a method of reducing the impurity concentration at the surface of the P-type buried layer, a method of reducing the surface of the buried layer in a hydrogen atmosphere may be considered.

[Application field]

In the above explanation, the invention made by the present inventor was mainly applied to a Bi-CMO8 type semiconductor device, which is the background field of application. can also be applied.

[Brief explanation of the drawing]

The first factor ~ (G is a process cross-sectional view for explaining the method of the present invention, Figure 2, CB) is a diagram showing the impurity concentration distribution of the P-type buried layer and the N-type buried layer, respectively. Figure 4, β) is the mask plan view and cross-sectional view of the N-type buried layer and N-type well in this example, and Figure 4, ■ is the mask plan view of the conventional N-type buried layer and N-type well. Cross-sectional view FIG. 5 is a cross-sectional view of a conventional Bi-CMO8 type semiconductor device. l...Silicon substrate, 4...N-type buried layer, 7...
Thick SiN2 film, 8...P type buried layer, 9...Epitaxial layer, 12...Nff1 well, 14...P
type well, 16° 17...gate, 18...N type collector layer, 19...P type source layer, 20...Nm emitter layer, 21...P type source/drain layer, 22・
...Nm, source/drain layer, 25...P type impurity layer, 26...Nfm impurity layer, M4...N type buried layer mask, MI! ...Mask for N type Tsuniru %QB...
- Bipolar transistor, Qp-P type MO8) transistor, QN...N type MOS transistor. Agent: Patent Attorney Masaru Ogawa - No. 1
Diagram (D) To ＼ To ＼ To ＼ To Kanji

Claims (1)

[Claims] 1. An N-type and P-type impurity physical layer is formed on a semiconductor substrate, an epitaxial layer is grown on this layer, and elements such as transistors are formed on this epitaxial layer. 1. A method for manufacturing a semiconductor device, the method comprising: performing a process to reduce the impurity concentration of at least a surface portion of the P-type impurity buried layer before growing the epitaxial layer. 2. The semiconductor according to claim 1, wherein the method for reducing the impurity concentration in the surface portion is to oxidize the surface of the buried layer to form an oxide film, and then remove this oxide film. Method of manufacturing the device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the method for reducing the impurity concentration in the surface portion is a method of reducing the surface of the buried layer with hydrogen. 4. After ion-implanting P-type impurities to form a P-type buried layer, the impurity concentration in the surface portion is lowered, and then annealing is performed to form a P-type buried layer. A method for manufacturing a semiconductor device according to any one of Items 1 to 3. 5. Claim 1, wherein the dimensions of the mask for forming the N-type buried layer are larger than the dimensions of the mask for forming the N-type well to be formed in the epitaxial layer on the N-type buried layer. A method for manufacturing a semiconductor device according to section 1.