JPS6123558B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a figure erasing method, particularly a figure processing method in which a figure is processed by performing bit-based processing based on a video signal obtained by scanning a figure. In order to do this, the video data of the video signal obtained by scanning the figure is individually scanned using an outline mask made by cutting out an outline pattern shaped like the outline of the target figure to be erased into a window and a clear mask corresponding to the outline mask. The present invention relates to a figure erasing method for erasing a figure by replacing the clear mask data with video data when all the data match the contour mask data.

Conventionally, in figure erasing processing in character recognition, image processing, etc., a method has been used in which a 3×3 to 5×5 mask is repeatedly applied to a target figure to partially erase the figure. Since this method is repeated, the processing time is long, and the number of stages of the circuit for removing the figure is large and complicated, and the processing time and complexity of the circuit configuration are difficult points for erasing a specific figure. On the other hand, if the number of bits corresponding to black areas of the binarized bits corresponding to white areas and black areas based on the video signal scanned on the screen is less than a certain threshold value, these black areas are noise. There is a noise erasing process that recognizes this and erases these noises, but it is not a fixed shape like this, but a predetermined shape to be erased, such as an unnecessary original pattern used on a printed wiring board. When processing graphics, it may be desirable to identify and erase symbols such as + and -, characters, figures, etc.

The present invention is aimed at meeting the above-mentioned problems and demands.A mask of approximately the same size as the figure to be erased (including characters, symbols, and any figures) is prepared, and the mask to be erased is removed. A binary contour mask made by molding the outer shape of the target figure and a clear mask corresponding to the contour mask are created, and the video data of the video signal obtained by scanning the figure on the screen and the data stored in the contour mask are created. By comparing, a specific figure can be erased in a short time in one process, and the eraser circuit configuration can be simplified. Therefore, the figure erasure processing method of the present invention is implemented in a figure processing circuit that processes figures by performing bit corresponding processing corresponding to white areas and black areas based on a video signal obtained by scanning figures on a screen. Prepare a contour pattern modeled after the contour of a certain figure to be erased, and create binarized data of a window by dividing the contour pattern into meshes of m (rows) x n (columns). A contour mask corresponding to the contour mask and a clear mask corresponding to the contour mask are prepared for each column, and the screen containing the target figure to be erased is scanned.
The encoded video data is sequentially input to the video register provided for each column, and the video data is compared with the contour masks prepared for each column, and when the video data matches all the contour masks of each column, the video data is The feature is that the figure to be erased is erased by replacing it with clear mask data and outputting it. This will be explained below with reference to the drawings.

FIG. 1 is an example of a target figure that is desired to be erased, FIG. 2 is a block diagram showing an embodiment of the contour mask and clear mask creation circuit, FIG. 3 is a processing example of the clear mask creation circuit of FIG. 2, and FIG. The figure shows an example of creating a contour mask and a clear mask, FIG. 5 shows an example of a figure processing original, FIG. 6 is a block diagram of an embodiment of the figure erasing method of the present invention, and FIG. 7 shows the figure erasure determining section. A specific circuit configuration diagram is shown.

In FIG. 1, numeral 11 is a target figure that is desired to be erased;
A mask 12 having a size that covers the target figure 11 to be erased is prepared, and the mask 12 is a window having m×n meshes 13, m in the vertical direction and n in the horizontal direction. In the figure, a 5x5 mesh window is shown.
It is said to be wind. FIG. 2 is a block diagram of a circuit for creating an outline mask and a clear mask from the target figure 11 to be erased, and in the figure, 14 represents an outline pattern. The contour pattern 14 is constructed by converting the mask 12 in FIG. 1 into a 5×5 mesh 1.
Binarization obtained by assigning "0" to the target figure 11 that is divided into 3 and desired to be erased, and coding meshes 13 other than figure 11, including meshes adjacent to the target figure 11, as "1". It is a collection of data windows. For x ₁ to x ₅ , mask 12 in Figure 1 is 5 x 5.
Indicates the mesh number of the row line divided into meshes 13, and _y1 to _y5 represent the mesh number of the row in the column. 15 is a counter, 1
6 is a decoder, 19 is a clear mask creation circuit, 1
7-1 to 17-5 represent "contour mask 1" to "contour mask 5", respectively, and 18-1 to 18-5 represent "clear mask 1" to "clear mask 5", respectively. Generally, the number of contour masks and corresponding clear masks corresponds to the number of stages n into which the mask 12 is divided.

Binarized data within the contour pattern 14 is sequentially output from the contour pattern 14 in synchronization with the synchronization signal. These data are processed into contour masks 17-1 to 17-5 and clear mask 1 by signals decoded by the decoder 16 as the counter 15 increments.
They are stored as a pair in any one of 8-1 to 18-5. That is, the data of the first stage y ₁ line of the contour pattern 14 is stored in 17-1 of the contour mask 1 and 18-1 of the clear mask 1 corresponding to this line.
The data of the second stage y ₂ line of the contour pattern 14 is applied to the corresponding contour mask 2 17-2 and the clear mask 2 18-2, and in the same way, the data of the fifth stage y ₅ line of the contour pattern 14 is The data is stored in the corresponding contour mask 5 17-5 and clear mask 5 18-5, but when storing the data of the contour pattern 14 in the clear masks 18-1 to 18-5, clear masks are created. Certain operations take place in circuit 19. That is, in the clear mask creation circuit 19 where a certain operation is performed, the binary data of the target figure 11 to be erased and the mesh 13 adjacent thereto among the binary data of the outline pattern 14 are set to a code of "0", and the other The data of the mesh is all processed to have the value "1". For example, the data for the second stage _y2 line of the contour pattern 14 in FIG. 2 is "11011" as shown in FIG. "10001" is stored in 18-2 of the clear mask ₂ corresponding to the line of the second stage y2 of the contour pattern 14 as described above.

FIG. 4 shows an example in which a mask 12 including a target figure 11 to be erased is made into a mask using the outline mask and clear mask creating circuit configuration shown in FIG. Reference numerals 14, 17-1 to 17- in the figure
5, 18-1 to 18-5 correspond to those in FIG. In the figure, of the contour pattern 14
x ₃ y ₁ , x ₂ y ₂ , x ₄ y ₂ , x ₁ y ₃ , x ₅ y ₃ , x ₂ y ₄ , x ₄ y ₄ , x ₃ y ₅
The data ``1'' in each mesh is the mesh 13 indicating an outline shaped like the outer shape of the target figure 11 to be erased.
The message 13 that corresponds to and surrounded by these "1"
The data "0" corresponds to the target figure 11 that is desired to be erased. In the contour mask 17-1, data "11111" of the first stage y ₁ line of the contour pattern 14 corresponding to this is stored as it is,
Data "11011" is stored in the clear mask 18-1. In the contour mask 17-2, data "11011" of the second stage y ₂ lines of the contour pattern 14 corresponding to this is stored as it is,
Clear mask 18-2 contains target figure 1 to be erased.
Data “10001” corresponding to 1 is stored. In the contour mask 17-3, the data "10001" of the third row y ₃ line of the corresponding contour pattern 14 is stored as is, and in the clear mask 18-3, the data "00000" is stored. Ru. In the contour mask 17-4, the data "11011" of the fourth stage y ₄ line of the corresponding contour pattern 14 is stored as is, and in the clear mask 18-4, the data "10001" is stored. Ru. In the contour mask 17-5, the data "11111" of the 5th line _5th line of the contour pattern 14 corresponding to this is stored as is, and the data "11011" is stored in the clear mask 18-5. Ru.

FIG. 5 is a graphic processing original drawing including a target figure 11 that is desired to be erased, the reference numeral 11 in the figure corresponds to that in FIG. 1, 20 is a graphic processing original drawing, 21 is a - symbol,
2 represents a line. If the number of meshes 13 when the graphic processing original drawing 20 is divided horizontally from the upper left end to the right end into meshes 13 having the size of the mesh in FIG. The number of binary bits corresponding to the white area and black area of the video signal obtained by scanning with the flying spot scanner is l. And in the vertical row A1, A
2, A3, . . . The horizontal rows are numbered B1, B2, . . . .

FIG. 6 shows contour masks 17-1 to 17-5 and clear masks 18-1 to 18 obtained through the contour mask and clear mask creation circuit of FIG.
5 is a block diagram illustrating a configuration of a figure erasing method for erasing the figure to be erased shown in FIG. 1 from the figure scanned from the figure processing original drawing 20 of FIG. In the figure, 23 to 27 are figure erasure determination units, 28
31 is a line delay, 32 is a negative input AND circuit, 33 is a flip-flop circuit that holds the data while being shifted by 5 meshes, 34 is a video register, 35 is a selector circuit, X is a data input terminal, and Y is a data output terminal. .

The figure erasure determination unit uses a number m corresponding to the number of line stages of a window that divides the contour pattern 14 into m×n meshes.
On the other hand, the line delay requires m-1 pieces because each line delay is connected following the figure erasure discriminating unit except for the m-th final stage. For example, in this embodiment, the contour pattern 14 is divided into 5×5 windows, so there are 5 lines, and the corresponding figure erasure discriminator is the discriminator 23 to 27.
Five items are prepared. And line daylay 28
31 to 31 are figure erasure determination units 2 excluding the final stage m
3 to 26 are provided. Each of the line delays 28 to 31 converts the contour pattern 14 into m from the number l of binarized bits of the video signal obtained by scanning the graphic processing original drawing 20 of FIG. 5 for one line.
The shift register is composed of shift registers in which the number l-n, which is the number n of line bits per stage of the mesh divided into ×n meshes, is connected in series. For example, in this embodiment, the contour pattern 14 is divided into five windows per stage, so n=5, and l-5 shift registers are connected in series to form each line delay 28 to 31. There is. As will be seen, the video register 34 of the figure erasure determining sections 23 to 27 is composed of five shift registers. Therefore, the sum of the number of bits of the video register 34 in the figure erasure discriminator 23 and the number of bits of the shift register of the line delay 28 is 1 of the video signal obtained by scanning the figure processing original picture 20 of FIG.
It is equal to the number of bits for the line, l. This means that the video register 3 in the figure erasure determining sections 24 to 26
4 and the line delay 2 connected to each
This also applies to numbers 9 to 31.

The negative input AND circuit 32 includes a figure erasure determination unit 2.
The CPM1 to CPM5 signals from 3 to 27 are input, and a coincidence output indicating that these signals are generated simultaneously is sent to the flip-flop circuit 3 of the next stage.
Control 3. The output of the flip-flop circuit 33 controls a selector circuit 35 in the figure erasure determining sections 23 to 27. X is a data input terminal, into which data of a binary bit signal based on a video signal obtained by scanning the graphic processing original drawing 20 is input;
Y is its output terminal.

FIG. 7 is a diagram showing a specific circuit configuration of the figure erasure determination section 23, in which 17-5 and 18-5 correspond to those in FIG. 2 and 4, and 34 and 35 correspond to those in FIG. correspond to things. 36 is a comparator, 37-1
37-5 to 37-5 are exclusive OR circuits, 38-1 to 38-5 are AND circuits, and 39 is a clear video register.

In FIGS. 6 and 7, the figure erasure determination unit 23
The contour mask 17-5 stores the data "11111" of the ₅ lines in the fifth stage of FIG. 4 obtained by the contour mask and clear mask creation circuit of FIG. 2, and the clear mask 18-5 stores the data "11011". 5 is used. The figure erasure determination unit 24 has a contour mask 17- which stores data "11011" for ₄ lines in the fourth stage.
4 and the clear mask 18-4 that stores the data "10001", and the contour mask 1 that stores the data "10001" of the third stage y ₃ lines in the figure erasure determination unit 25.
7-3 and a clear mask 18-3 storing data "00000" are stored in the second stage in the figure erasure determination unit 26.
The outline mask 17-2 that stores the data "11011" for ₂ lines of y and the clear mask 18-2 that stores the data "10001" send the data "11111" for the first stage y ₁ line to the figure erasure determination unit 27. A contour mask 17-1 for storing and a clear mask 18-1 for storing data "11011" are used, respectively.

For the circuits 37-1 to 37-5, 38-1 to 38-5, and the clear video register 39, circuits and shift registers corresponding to the number of video registers 34 are prepared. That is, in this embodiment, five exclusive OR circuits, an AND circuit, and a five-stage shift register are provided.

A binary video signal is output from a scanner that horizontally scans the graphic processing original drawing 20 including the target figure 11 to be erased shown in FIG. shall be binarized to "0") data will be converted to 1 in synchronization with the basic clock.
Bit by bit is input into the video register 34 from the data input terminal X. For example, when video data "0" of A1B1 enters the video register 34, this data "0" is simultaneously inputted to, for example, circuits 37-1 and 38-1 via line k shown in FIG. Subsequently, when the video data "0" of A1B2, A1B3, A1B4, and A1B5 is sequentially entered into the video register 34, the data is shifted one bit at a time until it becomes full. At the same time, circuits 37-1 to 37-5, 38-
Data corresponding to the contents of the shift register constituting the video register 34 is input to 1 to 38-5, respectively. For example, in the current state, the video register 34 contains data "00000", so the exclusive OR circuits 37-1 to 37-5 and the AND circuits 38-1 to 38-5 contain the shift signals that make up the video register 34. These data are input in the order corresponding to the registers. Also, circuit 37-
Data "11111" of 17-5 of contour mask 5 is input to each of the other input terminals 1 to 37-5. Therefore, the output is "11111" and the data "11111" is compared with all "1" which is the reference data of the comparator 36, and as a result, the input data "00000" of the video register 34 and the data 17-5 of the contour mask 5 are compared. A logic "0" representing a complete mismatch with the data "11111" is output as the output signal CMP1 of the comparator 36. However, at this time, the other output signals CMP2 to CMP5 are outputting logic "1", and the flip-flop 33 shown in FIG. 6 does not issue a select signal.

When video data “0” of A1B5 is introduced into the video register 34 in synchronization with the next basic clock, the first video data “0” of A1B1 is evicted from the full video register 34 and sent through the selector circuit 35. The signal is then transferred to the shift register of the line delay 28. When scanned binary video data is input from the data input terminal X in synchronization with the basic clock in this way, the contents of the video register 34 are shifted bit by bit and transferred to the line delay 28, and The contents transferred to 28 are also shifted one bit at a time. Since the total number of shift registers in the video register 34 and the number of shift registers in the line delay 28 is equal to the number l of bits for one line of the video signal obtained by scanning the graphic processing original drawing 20, the line The video data "0" of the first A1B1 stored in the delay 28 is inputted from the data input terminal X to the video register 34 in the figure discriminator 23. Then, it is transferred to the video register 34 in the second-stage figure discriminator 24 in correspondence with the figure processing original drawing 20. Similarly, the video data "0" of A1B1 is shifted through each video register 34 and line delay 29 to 31 in the figure discriminator 24 to 27 in the order shown in FIG. 6 in synchronization with the basic clock, and the data is output. The data "0" is sent to terminal Y.

Suppose that the video data "0" of the second stage A2B3 in the graphic processing original drawing 20 is shifted to the last part of the shift register constituting the video register 34 of the graphic discriminator 27. The content of video data "00000" of A6B3 to A6B7 of the processing original drawing 20 is stored, and the line delay 28 contains A5B
The video data contents of 8 to A5Bl, A6B1, and A6B2 are stored. Similarly, A5B3 to A5B7, A4 of the graphic processing original drawing 20 are stored in the video register 34 of the figure discriminator 24 to 27.
B3 to A4B7, A3B3 to A3B7,
Video data contents of A2B3 to A2B7 are stored respectively. The data contents stored in the video register 34 of each figure discriminator 23 to 27 and the corresponding contour mask 17-1 to 1
Since the data contents stored in CMP 7-5 are completely inconsistent with each other, the outputs CMP1 to CMP5 of each comparator 36 all generate logic "0" as explained above. The respective signals CMP1 to CMP5 actuate the flip-flop circuit 33 via the input NAND circuit 32, and control the selector circuits 35 in the figure discriminators 23 to 27. As a result, each line delay and video register 34
and connect the line delay and clear video register 39.

At this time, for example, a shift register corresponding to each of the video data "00100" stored in the video register 34 in the figure discrimination section 23 and the video data "11011" stored in 18-5 of "clear mask 5" AND circuit 38-1
38-5, the output of which all "0" information appears, and the clear video register 3
9 stores the data “00000”. Similarly, data of "00000" is stored in each of the clear video registers 39 of the graphic discrimination sections 24 to 27. In this state, as video data is sequentially introduced from the data input terminal
At the same time, the figure discriminator 27 at the final stage
From there, the data contents of the clear video register 39 are transferred to the data output terminal Y. Data contents stored in the video register 34 of each figure discriminator 23 to 27 and the corresponding contour mask 1
The introduction of the next bit of video data whose data content is completely inconsistent with the data stored in bits 7-1 to 17-5 causes the outputs CMP1 to CMP5 of one of the comparators 36 to generate a logic "1". However, the flip-flop circuit 33 holds selector circuits for 5 bits corresponding to the number of shift registers configuring the video register 34, and selects each clear video register 39 and line delay 28.
to 31 and the output terminal Y are maintained.
During this time, input of new data to each clear video register 39 is prohibited.

In this way, the binary value bit signal "1" corresponding to the black area of the window 13 corresponding to the target figure 11 to be erased is transferred to the bit signal "0" corresponding to the white area, so that the target figure 11 to be erased is transferred. can be eliminated from the graphic processing principle. Note that after 5 bits have passed, the line delay 28 to 3 is transmitted via each video register 34 and selector circuit 35.
1 and data output terminal Y, and the data contents of the video register 34 and the data contents of the corresponding contour masters 17-1 to 17-5 are compared and sequentially transferred one bit at a time.
Further, even if the data contents of the video register 34 and the corresponding contour mask 17-1, for example, completely mismatch by chance, the data contents of the other video register 34 and the corresponding contour mask 17-2 Since all of the data from 17-5 to 17-5 do not completely match, the selector circuit 35 does not switch to the clear video register 39, so erroneous erasure cannot occur.

The figure processing original drawing 20 that includes the object figure 11 to be erased is scanned horizontally from the upper left corner and when the scanning point reaches the lower right edge, the figure 11 to be erased standing up from the data output terminal Y is erased in white.
A black binary bit data signal group is obtained.

In the above description, the circuit 37 shown in FIG.
-1 to 37-5 are made to be exclusive OR circuits and the reference data of the comparator 36 are all "1", but the circuits 37-1 to 37-5 are made to be AND circuits and the reference data of the comparator 36 are all "0". ” may be used. If you do this,
Although a detailed explanation will be omitted, it is possible to simultaneously erase a figure included in the target figure 11 that is desired to be erased, such as the figure 21 shown in FIG.

As explained above, according to the present invention, an m×n mesh window is created using an outline pattern shaped like the outline of a predetermined figure to be erased, and the window is divided into two
Create a contour mask that has undergone value conversion bit processing and a clear mask that corresponds to the contour mask, prepare these masks for each line, and scan the screen that includes the figure to be erased. The binary value video data content and the data content of the contour mask are compared, and when a certain condition is met (complete mismatch in the case of the embodiment), the video data content is transferred to the data content of the clear mask. A specific figure can be deleted during processing and time can be shortened. The configuration of the erasing circuit is also simplified.

[Brief explanation of the drawing]

FIG. 1 is an example of a target figure that is desired to be erased, FIG. 2 is a block diagram showing an embodiment of the contour mask and clear mask creation circuit, FIG. 3 is a processing example of the clear mask creation circuit of FIG. 2, and FIG. The figure shows an example of creating a contour mask and a clear mask, FIG. 5 shows an example of a figure processing original drawing, FIG. 6 shows a block diagram of an embodiment of the figure erasing method of the present invention, and FIG. 7 shows a specific example of the figure erasure determining section. The circuit configuration diagram is shown below. In the figure, 11 is a target figure to be erased, 13 is a mesh, 14 is an outline pattern, 17-1 to 17-
5 represents a contour mask, and 18-1 to 18-5 represent clear masks, respectively.

Claims (1)

[Claims] 1 In a graphic processing circuit that performs graphic processing by performing bit-based processing corresponding to white and black areas based on a video signal that scans a graphic on the screen, the external shape of a predetermined figure to be erased is modeled. Prepare a dotsuta contour pattern, and convert the contour pattern into m
Create binarized data of a window divided into (rows) x n (columns) mesh, and separate it into a contour mask and a clear mask corresponding to the contour mask for each column and prepare for each column. Then, the binarized video data obtained by scanning the screen containing the target figure to be erased is sequentially input into the video register provided for each column, and the video data is input to the contour prepared for each column. A figure erasing processing method characterized in that the figure to be erased is erased by replacing the video data with clear mask data and outputting it when it matches all the outline masks in each column compared with the mask. .