JPS61234122A - High-speed logical circuit - Google Patents

Abstract

PURPOSE:To shorten delay time of a bipolar type LSI circuit by lowering the supply voltage and increasing the current of a logical circuit, by constituting an emitter follower of a PNP transistor and fetching the input signal to the base from the emitter and using the input signal for shifting up the signal level only. CONSTITUTION:Since data input D is supplied through PNP emittor followers 201 and 202, the base potential of a transistor (TR) 203 becomes, for instance, about 0V at the high level and about -VA (-0.6V) at the low level and, since an ECL level of input is sufficient to a lower-stage TR 209, a supply voltage VEE can be set at about -3V. Moreover, feedback inputs to TRs 205 and 206 for holding information are directly inputted from the collectors of the TRs 203 and 204. Therefore, delay time at the emitter follower can be shortened, because the supply voltage can be lowered and CK input can be inputted directly in the lower stage TR without passing through the emitter follower.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to high-speed logic circuits, and particularly to bipolar large-scale integrated circuits (hereinafter referred to as LSI), which are suitable for shortening the delay time of logic circuits. Regarding circuits.

[Background of the invention]

Conventionally, emitter-coupled logic gates m (Emi
ter Coupled Logic, hereinafter referred to as EC
(referred to as L) is commonly used. This logic gate consists of a current switch, usually made up of a differential transistor, and an emitter follower. The emitter follower plays a role in increasing the ability to drive the load capacitance added to the logic gate. However, since this emitter follower receives and receives signals from the base and outputs them from the emitter, the signal level is higher than the voltage between the emitters. (Hereafter v
, abbreviated as 1). Therefore, E
The signal level of CL is usually high level approximately -■□ (approximately -0.8V) and low level approximately -V, -V, (V.

is the signal amplitude, V, =0.6 V, then the low level is set to about -1.4 V). For this reason, the power supply voltage, including the constant current source of the current switch, cannot be lowered below approximately 3V (normally, the higher side of the power supply voltage is set to the ground potential, so the lower side supplies, for example, -3V). )
, Also, vertically stacked ECL, so-called series gate EC
For L, for example, if you use a two-stage series gate, the input to the upper stage will be at the same signal level as the normal ECL (ECL that is not a series gate) (the high level is -).
VI1. , the low level is -v1. -■, ) may be sufficient, but the input to the lower stage is approximately V higher than that signal level. only needs to be lowered. Therefore, the level of the input to the lower stage is lowered by the emitter follower, and the high level is approximately 12V□
, the low level is 12v□-vl. Therefore, the power supply voltage is also V. It is necessary to make it as large as possible (in absolute value). For example, when an ECL that is not a series gate is operated at -3V, a two-stage series gate ECL needs to be operated at about -4V. A detailed circuit example is published in Motorola's MECLIOK series data book. In this circuit, the data input is sent to the upper stage, and the clock G
K is put into the lower stage, but at this time GK is level shifted by the emitter follower transistor.

The reason for the above is that when only NPN transistors are used, lowering the signal level is easy and can be done with relatively little delay time using an emitter follower, but conversely, it is relatively difficult to raise the signal level. . N
When only PN transistors are used, the circuit described in Japanese Patent Publication No. 45-32005, for example, is used to increase the signal level. This is input to the base of the transistor and output from the collector. However, in this circuit, the low level of the output is determined by the current flowing through the load resistor, so when the input signal is at a high level, the fluctuations in the power supply voltage v,1' are minimized (by stabilizing V,,'). It is necessary to keep the current flowing through the transistor constant. However, even in this case, the high level of the input signal varies and the current changes. Also, since it is a collector output, the base response and collector response of the transistor are required.

Relatively slow compared to emitter followers. Therefore,
Efforts are being made to increase speed by adding capacitance. However, due to the large number of elements and the difficulty of stabilizing the signal level as mentioned above, in reality, this type of level shift is not used much, and instead it is The method used was to increase the power supply voltage. Therefore, if the power consumption is the same, the current will be smaller.

This was an obstacle to increasing speed.

[Purpose of the invention]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a high-speed logic circuit that has means for easily shifting up signal levels, has desired functions, and can achieve high speed without increasing the power supply voltage.

[Summary of the invention]

Therefore, in the present invention, a PNP transistor is used to easily shift up the signal level. In other words, P
Configure an emitter follower using an NP transistor,
V by taking the input signal to its base from the emitter. only get a higher output signal. In addition, here,
PNP transistors are mainly used only as emitter followers, and their only purpose is level shifting, so in terms of performance, for example, the cutoff frequency can be an order of magnitude lower than that of an NPN transistor, making the manufacturing process difficult. Never.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. The logic circuit 2 operates to output an output signal 5 in response to an input signal 6. If the LSI chip is configured based on the logic circuit 2, the high and low levels of the input signal 4 and output signal 5 must be the same, for example,
Assume that the signal level of output signal 5 is -vS at high level and -Vs, -V at low level as described above (in this case, it can be said that "the signal level of output signal 5 is ECL level") ), and the signal level of input signal 6 is also ECL.
Must be at the level. However, if the input signal 6 can be set to a slightly higher level and there is an advantage that the power supply voltage can be reduced by doing so,
Level shift (shift up) input signal 4 by v,8 using emitter follower 1 made of PNP transistor
By doing so, the input signal 6 to the logic circuit 2 becomes high,
By taking advantage of the advantage of being able to reduce the power supply voltage, it is possible to reduce power consumption, or for the same power consumption, increase current and increase speed. Therefore, in such a case, high speed can be achieved by configuring the logic circuit 2 like the logic circuit 3 and setting the input signal to 4.

Using the same idea, as shown in Figure 1(b).

A configuration in which the PNP emitter follower transistor 7 is brought to the end of the logic circuit 8 is also conceivable. however,
Generally, the characteristics of a PNP transistor (especially the cutoff frequency) are not as good as those of an NPN, so the output terminal 11
can be used when driving a light load with short wiring.

The PNP transistor in the above description is, for example, AQ an B, Grebene, co-translated by Shin et al.
(Alan, B., Breben) "Analog integrated circuit"
As described in PP, No. 60, PNP can be easily manufactured by having a horizontal structure. Even with such a manufacturing method, the present invention exhibits a sufficiently large effect because the PNP is used only as an emitter follower for level shifting. For example, PNP
The cutoff frequency of the PNP may be one order of magnitude lower than that of the NPN. When the NPN is 10 GHz, the PNP is 500 MHz to I GHz, but the delay time caused by the PNP emitter follower is 100 to 200 pg. In usage where this delay time is not a problem,
As will be described later, even such a PNP can be used to great effect.

An embodiment of the present invention will be explained in more detail with reference to FIG. Compared to the conventional example, in this example, the data input is input to the transistor 203 via the PNP emitter followers 201 and 202, and the clock input G
In this embodiment, K is directly input to the transistor 209 without passing through an NPN emitter follower.

The D and CK large inputs can also be at the ECL level, because the upper stage inputs go through a +PNP emitter follower, so the potential at the base of the transistor 203 is, for example, about Ov at high level and about - at low level. VA (-0,6
(hereinafter, this signal level will be compared with the ECL level and will be referred to as the "rCML level"). Since the input to the lower stage transistor 209 may be at the ECL level,
The power supply voltage V□ can be set to about -3V. In the conventional example, it was necessary to increase the voltage to -4V<.

Note that the feedback input to the pair of information holding transistors 205 and 206 is directly input from the collectors of the transistors 204 and 203, respectively, unlike the conventional case. This means that the base input of transistor 203 is CML
This corresponds to the level.

Now, the feature of this embodiment is that in addition to being able to reduce (the absolute value of) the power supply voltage, it is also possible to shorten the propagation delay time. In other words, unlike the conventional example, in this example,
Since the GK input is directly input to the lower stage without passing through the emitter follower, the delay time at the emitter follower is reduced.

This has a great effect on increasing the speed of flip-flops.

The constant current source 211 in this embodiment is simple and common, for example, as shown in FIG. 3, which uses the pentode characteristics of the transistor 301.

FIG. 4 is a modification of the flip-flop of FIG. In contrast to FIG. 2, this figure is characterized in that the feedback input to the pair of transistors 205, 206 is provided via emitter follower transistors 213, 212, respectively. Such a configuration is possible when it is not necessary to reduce the power supply voltage V□ so severely.

FIG. 5 shows an example in which the present invention is applied to a three-stage series gate ECL. Without the present invention, the input to the base of the top-stage transistor 505 is at the ECL level, and the middle-stage transistor 509 , and the inputs to the bottom transistor 511 are approximately Vat and 2v1., respectively, above the ECL level. A low signal level is required.

On the other hand, the fifth [i! ! In I, EC
Since the L level is input to the middle stage and passed through the PNP emitter follower transistor 501 to the top stage, the signal level to the bottom stage may be approximately Vat lower than the ECL level. Therefore, the power supply voltage vo is also lower than that of the conventional example.
, small size.

Series gate ECL can be modified in various ways, such as the number of vertically stacked stages, but for any modified circuit,
It is clear that a similar concept as above can be used for level shifting the input signal.

Next, another embodiment according to the present invention will be described using FIG. 6 and subsequent figures. Figure 6 shows that the input signal with large amplitude is
The high level is a circuit for keeping it almost constant or slightly higher and reducing the amplitude. This circuit is used, for example, as an input buffer for converting a relatively large amplitude signal between LSIs into a relatively small amplitude signal inside the LSI.

The dividing resistors 803 and 604 are for reducing the amplitude, but the output signal v0 is the V of the PNP transistor. It also depends on the V m t of the NPN transistor, so it depends on the required circuit characteristics.

In the one-wire diagram where the resistor 604 is not required, first PN
P) - The input signal V, is shifted up by transistor 01 and then shifted down by NPN transistor 602. The difference between the upshift amount and the downshift amount is adjusted to convert the input signal V to the output signal V. Determine the amount of level shift to .

FIG. 7 is a modification of FIG. 6, in which the order of the PNP and NPN transistors is reversed. First, NP
N)-downshifting of the input signal vl by Langstaff 01 and then upshifting by PNP transistor 702; The circuits shown in FIGS. 6 and 7 have the effect of increasing the degree of freedom in setting subtle level shift amounts.

Figure 8 is a combination of Figures 6 and 7,
In the circuit of FIG. 6, the PNP transistor 804 and the like have the effect of increasing the ability to drive the load connected to vo. Also, it is clear from the previous explanation that depending on the required level shift amount, the resistors 806 and 808 may be zero or may be placed in vertically symmetrical positions.Next, the 911th ! Another embodiment according to the present invention will be described using 1. In this embodiment, as mentioned above, a normal ECL circuit cannot be operated at a power supply voltage of about 3V or less, but Roughly v1. The present invention provides an ECL circuit that operates even with a small voltage.

The circuit 950 interconnects the emitters and collectors of the PNP transistors 901 to 903 and provides an ECL level signal to the base of each transistor. Although the number of transistors may be one, in this embodiment, such a configuration provides an AND logic function. That is, when -inputs A, B, and C are all high, the input to the base of transistor 904 is high. Since the circuit 950 is an emitter follower using a PNP transistor, the input signal to the base of the transistor 904 is at the CML level. Therefore, circuit 951
Since it becomes a current switch for ML level input and CML level output, 71M can be as small as -2V. Since circuit 952 is a normal NPN emitter follower, the outputs taken from the emitters of transistors 907 and 908 are at the ECL level. Logically, NAND is output to the emitter of transistor 907, and AND logic is output to the emitter of transistor 908.

〔Effect of the invention〕

As explained above, according to the present invention, two simple PNP transistors can be mixed together without adding a significant manufacturing process to the normal NPN transistor process, and the PN
P transistors are used only to shift up the signal level, thereby reducing the power supply voltage of the logic circuit,
If the power consumption remains the same, the delay time can be significantly shortened by increasing the current.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram of the present invention, and FIGS. 2 to 9 are diagrams showing one embodiment of the present invention. 1.7,201,501,601,702,801゜8
04.901,902,903-PNP transistor,
2, 8...Logic circuit, 3,9...Logic circuit incorporating PNP emitter follower, vll. ,...PN
P emitter follower transistor collector power supply, 2
11,513...Constant current source, D...Flip-flop data input, Q...Flip-flop positive phase output, Q-...Flip-flop negative phase output, ■,...Input signal, vo...output signal.

Claims (1)

[Claims] 1. A high-speed bipolar integrated circuit configured with NPN transistors, characterized in that a PNP transistor emitter follower circuit is used as a part of the unit logic circuit to shift the signal level in a higher direction. logic circuit. 2. The above unit logic circuit is a series gate emitter-coupled logic circuit composed of NPN transistors, and an emitter follower circuit of a PNP transistor is added to the front stage of the emitter-coupled logic circuit, and the input signal is passed through the emitter follower circuit. Claims characterized in that the level-shifted signal is input to the upper stage of the emitter-coupled logic circuit, and the input signal is input directly to the lower-stage input of the emitter-coupled logic circuit. 1st
High-speed logic circuits described in Section. 3. A configuration comprising a first emitter follower circuit using a PNP transistor and a second emitter follower circuit using an NPN transistor, and inputting the output of the first emitter follower circuit to the second emitter follower circuit;
2. The high-speed logic circuit according to claim 1, wherein the output of the second emitter follower circuit is input to the first emitter follower circuit. 4. The high-speed logic circuit according to claim 1, wherein the output of an emitter follower circuit in which the collectors and emitters of a plurality of PNP transistors are connected to each other is input to an emitter-coupled logic circuit.