JPS61234078A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS61234078A JPS61234078A JP7520185A JP7520185A JPS61234078A JP S61234078 A JPS61234078 A JP S61234078A JP 7520185 A JP7520185 A JP 7520185A JP 7520185 A JP7520185 A JP 7520185A JP S61234078 A JPS61234078 A JP S61234078A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- film
- layer
- photosensitive resin
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000010408 film Substances 0.000 claims description 52
- 229920005989 resin Polymers 0.000 claims description 21
- 239000011347 resin Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 abstract description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 3
- 238000009751 slip forming Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 30
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004090 dissolution Methods 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明は薄膜トランジスタ製造時における電極膜のリフ
トオフ残りの発生を防止するためのもので、２層のレジ
スト膜構成を採用してリフトオフ工程時のレジスト断面
形状を制御し、電極短絡。[Detailed Description of the Invention] [Summary] The present invention is intended to prevent the occurrence of lift-off residue of an electrode film during manufacturing of thin film transistors, and employs a two-layer resist film configuration to change the cross-sectional shape of the resist during the lift-off process. Control and electrode short circuit.
信頼性低下の原因となる電極膜のリフトオフ発生の防止
を可能としている。This makes it possible to prevent lift-off of the electrode film, which causes a decrease in reliability.
本発明は薄膜トランジスタ（ＴＰＴ ）の製造方法に係
シ、特にゲート電極とソース、ドレイン電極の位置整合
を自己整合裏面露光とリフトオフで行うのに適したレジ
スト膜構成に関する。The present invention relates to a method for manufacturing a thin film transistor (TPT), and more particularly to a resist film structure suitable for positionally aligning a gate electrode, source, and drain electrodes by self-aligned back exposure and lift-off.
ＴＰＴ製造時に電極膜リフトオフ残９が発生すると、電
極短絡、信頼性低下の原因となる。従って、この電極膜
リフトオフ残シが発生しない対策をとることが重要な課
題となる。If electrode film lift-off residue 9 occurs during TPT manufacturing, it causes electrode short circuits and reduced reliability. Therefore, it is important to take measures to prevent this electrode film lift-off residue from occurring.
従来の単層レジスト膜を用いたセルフアライメント（自
己整合）裏面露光法による逆スタガード型ＴＰＴの製造
工程を第５図に示す。FIG. 5 shows a manufacturing process of an inverted staggered TPT using a conventional self-alignment back exposure method using a single-layer resist film.
ＴＰＴの製造に際しては、まず第５図（ａ）に示すよう
に、表面にゲート電極１がパターニング形成された基板
２上にＳＩＮの絶縁体層３とａ−８ｉの半導体層４を全
面形成し、その上をポジ型のレジスト５で被覆した後、
基板２の裏面よりゲート電極１をマスクとして矢印線で
示すように露光を行う。In manufacturing TPT, first, as shown in FIG. 5(a), a SIN insulating layer 3 and an A-8i semiconductor layer 4 are formed on the entire surface of a substrate 2 on which a gate electrode 1 is patterned. , after covering it with a positive resist 5,
Exposure is performed from the back surface of the substrate 2 using the gate electrode 1 as a mask as shown by the arrow line.
次にこれを現偉すると、第５図伽）に示すようにゲート
パターン上にのみレジスト５′が残る。この状態でのレ
ジスト５′の断面形状は、現像液による感光されたレジ
ストの除去が上面から進行しかつレジスト内での光の回
折効果もあるために第５図（ｂ）のように端面に傾斜が
つい九ものとなる。従って、次工程で第５図（ｑに示す
ように表面にソース、ドレイン用電極膜６を形成してリ
フトオフを行う際に、レジスト５′の端面に堆積した電
極膜が第５図（ｄ）に示すように一部残される。７はこ
のリフトオフ時に残された電極膜の一部である。When this is then exposed, the resist 5' remains only on the gate pattern, as shown in FIG. In this state, the cross-sectional shape of the resist 5' is as shown in FIG. The slope becomes nine. Therefore, when the source and drain electrode films 6 are formed on the surface as shown in FIG. 5(q) and lift-off is performed in the next step, the electrode films deposited on the end face of the resist 5' are removed as shown in FIG. 5(d). A portion of the electrode film is left as shown in FIG. 7. Reference numeral 7 indicates a portion of the electrode film left behind during this lift-off.
このように、従来の方法では、リフトオフ時にソース、
ドレイン用電極膜の一部が残されてしまい、レジスト５
′の端面の傾斜がさらになだらかになると、レジストが
電極膜で見金に被われるためにリフトオフが行えなくな
る。また、そこまで行かなくとも、電極膜の一部が第５
図（ｄ）に示すように残されると、次の層間絶縁膜やパ
シベーション膜の形成工程で均一な被覆が行われず、眉
間の電極短絡や信頼性低下の原因となる。In this way, in the conventional method, the source,
A part of the drain electrode film is left behind and the resist 5
If the slope of the end face becomes even gentler, lift-off cannot be performed because the resist is covered with the electrode film. Also, even if it does not go that far, part of the electrode film may
If left as shown in Figure (d), uniform coverage will not be achieved in the next step of forming an interlayer insulating film or a passivation film, causing a short circuit between the eyebrows and a decrease in reliability.
本発明は上述の問題点を解決するためのもので、第１図
に例示したように２層のレジスト膜（感光性樹脂）構成
を採用している。第１のレジスト膜は、第１図（ａ）に
示すように形成されて基板表面側からあらかじめ全面露
光され、その後その上に第１図（ｂ）に示すように第２
のレジスト膜が形成されて基板裏面側から露光される。The present invention is intended to solve the above-mentioned problems, and employs a two-layer resist film (photosensitive resin) structure as illustrated in FIG. The first resist film is formed as shown in FIG. 1(a), and the entire surface is exposed in advance from the surface side of the substrate, and then a second resist film is formed on it as shown in FIG. 1(b).
A resist film is formed and exposed from the back side of the substrate.
上部電極形成はこの２層の感光性樹脂膜を用いて行われ
る。The upper electrode is formed using these two layers of photosensitive resin films.
上記工程の採用により、第１のレジスト膜が第２のレジ
スト膜よ勺感光を進行させた状態が実現され、その後現
偉を行う際に第１のレジスト膜の溶解速度が促進される
ので、残った第１のレジスト膜の断面形状が第１図（ｄ
）に示すように逆テーパ状となる。従って、その後ソー
ス、ドレイン用電極膜を形成してり７トオフを行う際に
、第１図（ｅ）に示すように電極膜の残りが発生しない
良好なリフトオツパターニングを行うことが可能になる
。By employing the above process, a state is realized in which the first resist film is more exposed to light than the second resist film, and the dissolution rate of the first resist film is accelerated during subsequent exposure. The cross-sectional shape of the remaining first resist film is shown in Figure 1 (d
), it has a reverse tapered shape. Therefore, when the source and drain electrode films are formed and then removed, it is possible to perform good lift-off patterning without leaving any remaining electrode films, as shown in FIG. 1(e). .
以下、第１図乃至第４図に関連して本発明の詳細な説明
する。The present invention will now be described in detail with reference to FIGS. 1 to 4.
本発明は２層のレジスト膜構成を採用してリフトオ７工
程時のレジスト断面形状を制御することにより、電極短
絡、信頼性低下の原因となる電極膜のリフトオフ残９発
生を防止するもので、次にその各種実施例を説明する。The present invention adopts a two-layer resist film structure and controls the cross-sectional shape of the resist during the lift-off process to prevent lift-off residue 9 of the electrode film, which causes electrode short circuits and reduced reliability. Next, various examples thereof will be explained.
第１図に第１の実施例を示す。A first embodiment is shown in FIG.
第１図（ａ）〜（ｅ）は第１の実施例のＴＦ’ｒ （逆
スタガード型）製造工程図で、ＴＰＴの製造に際しては
、まず第１図（ａ）に示すように、絶縁性基板ｌｌ上に
Ｃｒのゲート電極νを８００Ｘ厚さにバターニング形成
し、ソノ上Ｋ ５ｉＮＣ）絶縁体？ｌ膜１３ （Ｈすａ
ｏｏｏＸ ）とａ −Ｓｉの半導体薄膜１４ （厚さ１
０００ Ａ ）をＰ−ＣＶＤ法により連続形成した後、
１層目のレジスト（ノボラック系のポジ型レジスト；第
１の感光性樹脂膜） １５を２μｍ厚さで塗布する。そ
して９０ Ｃ＃ ３０ｍ１ｎのプリベークを行った後、
矢印線で示すようにレジスト表面側（基板表面側）より
通常のω〜８０％の露光量で全面露光を行う。FIGS. 1(a) to (e) are TF'r (reverse staggered type) manufacturing process diagrams of the first embodiment. When manufacturing TPT, first, as shown in FIG. 1(a), A gate electrode ν of Cr is patterned to a thickness of 800× on the substrate 1, and a 5iNC) insulator is formed on the substrate. l membrane 13 (Hsa
oooX) and a-Si semiconductor thin film 14 (thickness 1
000 A) was continuously formed by P-CVD method,
First layer resist (novolak positive resist; first photosensitive resin film) 15 is applied to a thickness of 2 μm. And after pre-baking 90C# 30m1n,
As shown by the arrow line, the entire surface is exposed from the resist surface side (substrate surface side) with an exposure amount of ω˜80% of the normal amount.
次に、第１図（ｂ）に示すように、２層目のレジスト（
１層目と同じポジ臘しジスト；第２の感光性樹脂膜）
１６を１μｍ厚さで塗布し、鉛’Ｃ＋２０ｔｎｉｎのプ
リベークの後、矢印線で示すように基板裏面からゲート
電極１０ｆｅマスクとしてセルファライメント露光を行
う。この場合、露光時間はａ −Ｓｉ層での吸収のため
通常露光の場合より長時間を要するが、１層目の２μｍ
厚のレジスト１５は既に感光されてお９該しジスト部分
での吸収が小さいため、２μｍ厚単層レジストによる裏
面露光法の場合よりもむしろ露光時間は短かくなる。Next, as shown in FIG. 1(b), the second layer of resist (
Same positive resist as the first layer; second photosensitive resin film)
16 is applied to a thickness of 1 μm, and after prebaking with lead'C+20tnin, self-alignment exposure is performed from the back side of the substrate using the gate electrode 10fe as a mask, as shown by the arrow line. In this case, the exposure time is longer than normal exposure due to absorption in the a-Si layer, but
Since the thick resist 15 has already been exposed to light and the absorption in the resist portion is small, the exposure time is shorter than in the back exposure method using a 2 μm thick single layer resist.
この後現像を行なうと、１層目のレジスト１５は裏面露
光時にマスクされた部分も全面露光時に感光しているな
め、２層目のレジスト１６が２２７パターンのエツジ部
で溶解が停止するのに対して、１層目のレジスト化はマ
スクパターン内側まで溶解が進み、第１図（Ｃ）に示す
ように断面形状１７はオーバハング状となる。When development is performed after this, the parts of the first resist 15 that were masked during backside exposure are also exposed during full exposure, and the dissolution of the second resist 16 stops at the edge of the 227 pattern. On the other hand, in the first layer of resist, the dissolution progresses to the inside of the mask pattern, and the cross-sectional shape 17 becomes an overhanging shape as shown in FIG. 1(C).
次に、このレジストを残したま＼でソース、ドレイン用
電極膜形成を行うと、第１図（ｄ）に示すように、該ソ
ース、ドレイン用電極膜１Ｂはレジストのオーバハング
部分で良好な分離状態となり、その後リフトオフを行っ
た際に、第１図（ｅ）に示すようにリフトオフ残）のな
い良好なパターン形成が実現される。１９はソース、ド
レイン電極である。Next, when the source and drain electrode films are formed while leaving this resist, as shown in FIG. When lift-off is performed thereafter, good pattern formation with no lift-off residue is achieved as shown in FIG. 1(e). 19 are source and drain electrodes.
第２図乃至第４図に第２〜第４の実施例を示す。Second to fourth embodiments are shown in FIGS. 2 to 4.
第２図の第２の実施例の場合は、スタガード型ＴＰＴの
製造途中（第１図（Ｃ）の工程に相当）の断面図を示し
、２１は基板、ｎはソース、ドレイン電極、詔は半導体
薄膜、罠は絶縁体薄膜、２５は１層目のレジスト（第１
の感光性樹脂膜）、２６は２層目のレジスト（第２の感
光性樹脂膜）（γはゲート電極である。In the case of the second embodiment shown in FIG. 2, a sectional view of the staggered TPT in the middle of manufacturing (corresponding to the process in FIG. 1(C)) is shown, where 21 is the substrate, n is the source and drain electrodes, and Semiconductor thin film, trap is insulator thin film, 25 is first layer resist (first layer)
(photosensitive resin film), 26 is a second layer resist (second photosensitive resin film) (γ is a gate electrode).
第３図の第３の実施例の場合は、コープレナー型ＴＰＴ
の製造途中（第１図（ｅ）の工程に相当）の断面図を示
し、３１は基板、諺は半導体薄膜、おはソース、ドレイ
ン電極、あは絶縁体薄膜、あは１層目のレジスト（第１
の感光性樹脂膜）、アは２層目のレジスト（第２の感光
性樹脂膜）、３７はゲート電極である。In the case of the third embodiment shown in FIG. 3, coplanar TPT
31 is the substrate, the semiconductor thin film is the semiconductor thin film, A is the source and drain electrodes, A is the insulator thin film, and A is the first resist layer. (1st
(photosensitive resin film), A is a second layer resist (second photosensitive resin film), and 37 is a gate electrode.
第４図の第４の実施例の場合は、逆コープレナー型ＴＰ
Ｔの製造工程を示し、４１は基板、４２はゲート電極、
４３は絶縁体薄膜、祠はソース、ドレイン電極、４５は
１層目のレジスト（第１の感光性樹脂膜）、４６は２層
目のレジスト（第２の感光性樹脂膜）、４７は半導体薄
膜である。本例の場合は、第４図（ａ）の状態でリフト
オフを行った後、第４図伽）に示すように半導体薄膜４
７を形成する。In the case of the fourth embodiment shown in FIG. 4, the inverse coplanar type TP
41 is a substrate, 42 is a gate electrode,
43 is an insulator thin film, the shrine is a source and drain electrode, 45 is a first layer resist (first photosensitive resin film), 46 is a second layer resist (second photosensitive resin film), 47 is a semiconductor It is a thin film. In the case of this example, after lift-off is performed in the state shown in FIG. 4(a), the semiconductor thin film 4 is
form 7.
これらの第２．３．４の実施例の場合も、上部電極膜（
スタガード型、コープレナー型；ゲート電極、逆コープ
レナー型；ソース、ドレイン電極）のり７トオフに用い
るレジストを２層とする（各レジストの露光方向は前例
と同様）もので、前例と同様の効果が得られる。In the case of these Examples 2.3.4 as well, the upper electrode film (
Staggered type, coplanar type; gate electrode, inverse coplanar type; source, drain electrode) The resist used for glue-off is two layers (the exposure direction of each resist is the same as the previous example), and the same effect as the previous example is obtained. is obtained.
なお、上述の説明では１層レジスト膜厚を２μｍとし、
２層目レジスト膜厚７＆：１μｍとする例について述べ
たが、良好なオーバハング形状を作るためには２層目の
膜厚が１層目よりも薄いことが望ましい。In addition, in the above explanation, the thickness of one layer of resist is 2 μm,
An example has been described in which the second layer resist film thickness is 7 &: 1 μm, but in order to create a good overhang shape, it is desirable that the second layer film thickness is thinner than the first layer.
また、本発明では、１層目レジストによって基板表面を
平坦化した上に２層目レジストを塗布することになるた
め、通常のリフトオフで用いられる膜厚（１，０〜２．
０μｍ）以下の薄い膜厚（０，５〜ｌｐｍ）に２層目レ
ジストを形成しても良好なバターニングが行える。この
ように薄い膜厚の２鳩目レジストを用いれば、露光時間
の短縮等が可能とな９、作業能率の向上が図れる。In addition, in the present invention, since the substrate surface is flattened by the first resist layer and then the second resist layer is applied, the film thickness used in normal lift-off (1.0 to 2.
Even if the second resist layer is formed to have a thin film thickness (0.5 to lpm) of 0 μm or less, good patterning can be achieved. By using a two-eyelet resist having such a thin film thickness, it is possible to shorten the exposure time, etc. 9, thereby improving work efficiency.
以上述べたように、本発明によれば、次の各種の優れた
効果を奏す゛ることが可能である。As described above, according to the present invention, it is possible to achieve the following various excellent effects.
（１） バターニング工程を複雑化することなくセル
フアライメント法によるＴＰＴのパターン形成時のリフ
トオフ残Ｊ）ｔ−なくすことができるため、歩留の向上
が実現できる。(1) Since the lift-off residue during TPT pattern formation by the self-alignment method can be eliminated without complicating the patterning process, the yield can be improved.
（２）リフトオフ後の電極形状嘉平滑なため、層間の電
極短絡をなくして信頼性を向上させることができる。(2) Since the electrode shape is smooth after lift-off, reliability can be improved by eliminating electrode short circuits between layers.
（３）第２層のレジストの膜厚を薄くすることができ、
露光時間を短縮して工程時間を短縮することが可能にな
る。(3) The thickness of the second layer resist can be made thinner,
By shortening the exposure time, it becomes possible to shorten the process time.
第１図（ＩＬ）〜（ｅ）は本発明の第１の実施例のＴＦ
Ｔ Ｍ造工程図、
第２図は同第２の実施例のＴＰＴ製造途中の断面図、
第３図は同第３の実施例のＴＰＴ製造途中の断面図、
第４図（ａ） 、 （ｂ）は同第４の実施例のＴＦＴ
ｉ造工程図、
第５図（ａ）〜（ｄ）は従来のＴＰＴ製造工程図である
。
図中、
１１ 、２１ 、３１ 、４１は基板、１２ 、２７
、３７ 、４２はゲート電極、１３ 、２４ 、３４
、４３は絶縁体薄膜、１４ 、２３ 、３２ 、４７は
半導体薄膜、１５ 、２５ 、３乳４５は１層目のレジ
スト（第１の感光性樹脂膜）、
１６ 、２６ 、３６ 、４６は２層目のレジスト（第
２の感光性樹脂膜）、
１８ 、２２ 、３３ 、４４はソース、ドレイン電極
である。
第 ２ 図
第 ３ 図
第 ４ 図FIG. 1 (IL) to (e) are TFs of the first embodiment of the present invention.
TM manufacturing process diagram, Figure 2 is a cross-sectional view of the TPT in the second embodiment during manufacture, Figure 3 is a cross-sectional view of the third example in the middle of TPT manufacture, Figure 4(a), ( b) is the TFT of the fourth embodiment
Figures 5(a) to 5(d) are conventional TPT manufacturing process diagrams. In the figure, 11, 21, 31, 41 are substrates, 12, 27
, 37, 42 are gate electrodes, 13, 24, 34
, 43 are insulator thin films, 14 , 23 , 32 , 47 are semiconductor thin films, 15 , 25 , 3 45 are first layer resists (first photosensitive resin films), 16 , 26 , 36 , 46 are 2 The resist layers (second photosensitive resin film) 18, 22, 33, and 44 are source and drain electrodes. Figure 2 Figure 3 Figure 4
Claims (2)
導体薄膜を介して下部電極と上部電極が位置合せされて
配置される薄膜トランジスタの製造工程において、 前記上部電極のパターン形成が、 前記基板の表面側から全面露光された第１の感光性樹脂
膜と、該第１の感光性樹脂膜の全面露光後にその上に形
成され裏面から前記下部電極をマスクとして自己整合的
に露光された第２の感光性樹脂とからなる２層の感光性
樹脂膜を用いて行われることを特徴とする薄膜トランジ
スタの製造方法。(1) In the manufacturing process of a thin film transistor in which a lower electrode and an upper electrode are aligned and arranged on an insulating substrate via an insulating thin film or an insulating thin film or a semiconductor thin film, the patterning of the upper electrode is performed on the substrate. A first photosensitive resin film that is entirely exposed from the front side of the first photosensitive resin film, and a second photosensitive resin film that is formed on the first photosensitive resin film after the entire surface of the first photosensitive resin film is exposed and is exposed from the back side in a self-aligned manner using the lower electrode as a mask. 1. A method for manufacturing a thin film transistor, characterized in that the method is carried out using a two-layer photosensitive resin film made of two photosensitive resins.
さな膜厚で形成された特許請求の範囲第１項記載の薄膜
トランジスタの製造方法。(2) The method for manufacturing a thin film transistor according to claim 1, wherein the second photosensitive resin film is formed to have a smaller thickness than the first photosensitive resin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60075201A JPH07101742B2 (en) | 1985-04-09 | 1985-04-09 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60075201A JPH07101742B2 (en) | 1985-04-09 | 1985-04-09 | Method of manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61234078A true JPS61234078A (en) | 1986-10-18 |
| JPH07101742B2 JPH07101742B2 (en) | 1995-11-01 |
Family
ID=13569340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60075201A Expired - Lifetime JPH07101742B2 (en) | 1985-04-09 | 1985-04-09 | Method of manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07101742B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005109014A (en) * | 2003-09-29 | 2005-04-21 | Sony Corp | Element formation method and interconnection formation method |
| JP2005158775A (en) * | 2003-11-20 | 2005-06-16 | Hiroyuki Okada | Manufacturing method of organic thin film field effect transistor |
| JP2010503192A (en) * | 2006-08-31 | 2010-01-28 | ケンブリッジ ディスプレイ テクノロジー リミテッド | Organic electronic equipment |
| JP2010123655A (en) * | 2008-11-18 | 2010-06-03 | Konica Minolta Holdings Inc | Method of manufacturing organic thin-film transistor array, and the organic thin-film transistor array |
| JP2010272877A (en) * | 2002-05-08 | 2010-12-02 | Oerlikon Trading Ag Trubbach | Method for forming unit including three-dimensional surface pattern, and use of the same |
| WO2013018546A1 (en) * | 2011-08-04 | 2013-02-07 | 国立大学法人大阪大学 | Organic transistor and method for manufacturing same |
| CN106933054A (en) * | 2015-12-31 | 2017-07-07 | 上海微电子装备有限公司 | A kind of figuring technique |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57100428A (en) * | 1980-12-16 | 1982-06-22 | Matsushita Electronics Corp | Method for photomechanical process |
| JPS58166769A (en) * | 1982-03-27 | 1983-10-01 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPS5927574A (en) * | 1982-08-04 | 1984-02-14 | Fujitsu Ltd | Manufacture of self-alignment thin film transistor |
-
1985
- 1985-04-09 JP JP60075201A patent/JPH07101742B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57100428A (en) * | 1980-12-16 | 1982-06-22 | Matsushita Electronics Corp | Method for photomechanical process |
| JPS58166769A (en) * | 1982-03-27 | 1983-10-01 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPS5927574A (en) * | 1982-08-04 | 1984-02-14 | Fujitsu Ltd | Manufacture of self-alignment thin film transistor |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010272877A (en) * | 2002-05-08 | 2010-12-02 | Oerlikon Trading Ag Trubbach | Method for forming unit including three-dimensional surface pattern, and use of the same |
| JP2005109014A (en) * | 2003-09-29 | 2005-04-21 | Sony Corp | Element formation method and interconnection formation method |
| JP2005158775A (en) * | 2003-11-20 | 2005-06-16 | Hiroyuki Okada | Manufacturing method of organic thin film field effect transistor |
| JP2010503192A (en) * | 2006-08-31 | 2010-01-28 | ケンブリッジ ディスプレイ テクノロジー リミテッド | Organic electronic equipment |
| US8481360B2 (en) | 2006-08-31 | 2013-07-09 | Cambridge Display Technology Limited | Organic electronic device |
| JP2010123655A (en) * | 2008-11-18 | 2010-06-03 | Konica Minolta Holdings Inc | Method of manufacturing organic thin-film transistor array, and the organic thin-film transistor array |
| WO2013018546A1 (en) * | 2011-08-04 | 2013-02-07 | 国立大学法人大阪大学 | Organic transistor and method for manufacturing same |
| JP2013038127A (en) * | 2011-08-04 | 2013-02-21 | Osaka Univ | Organic transistor and manufacturing method of the same |
| US9153789B2 (en) | 2011-08-04 | 2015-10-06 | Osaka University | Transistor with source/drain electrodes on pedestals and organic semiconductor on source/drain electrodes, and method for manufacturing same |
| CN106933054A (en) * | 2015-12-31 | 2017-07-07 | 上海微电子装备有限公司 | A kind of figuring technique |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07101742B2 (en) | 1995-11-01 |
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