JPS61232657A - Electrostatic breakdown preventive element - Google Patents
Electrostatic breakdown preventive elementInfo
- Publication number
- JPS61232657A JPS61232657A JP7473685A JP7473685A JPS61232657A JP S61232657 A JPS61232657 A JP S61232657A JP 7473685 A JP7473685 A JP 7473685A JP 7473685 A JP7473685 A JP 7473685A JP S61232657 A JPS61232657 A JP S61232657A
- Authority
- JP
- Japan
- Prior art keywords
- input
- terminal
- input terminal
- resistor
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015556 catabolic process Effects 0.000 title abstract description 9
- 230000003449 preventive effect Effects 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 3
- 230000002265 prevention Effects 0.000 description 10
- 230000006378 damage Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
静電気等により入力端子に入ってくる高電圧を、従来は
トランジスタＱ、を通じて電源端子ｖｃｃと入力端子Ｉ
Ｎ間で吸収していたが、本発明では基板内に形成された
抵抗の直下に高濃度埋込層を設けないで寄生トランジス
タＱ２を積極的に形成して、接地端子ＶＥＥと入力端子
ＩＮ間でも吸収することにより、デバイスの静電耐力を
上げる。[Detailed Description of the Invention] [Summary] Conventionally, high voltage that enters the input terminal due to static electricity, etc. is transferred to the power supply terminal VCC and the input terminal I through a transistor Q.
However, in the present invention, the parasitic transistor Q2 is actively formed without providing a high-concentration buried layer directly under the resistor formed in the substrate, and the absorption occurs between the ground terminal VEE and the input terminal IN. However, by absorbing it, it increases the electrostatic resistance of the device.
本発明は集積回路等半導体デバイスの入力端子に設けら
れる静電破壊防止素子に関する。The present invention relates to an electrostatic breakdown prevention element provided at an input terminal of a semiconductor device such as an integrated circuit.
近年、半導体デバイスの高速化、高集積化にともない、
デバイスはますます微細化され、静電耐力の低いＭＯ３
素子だけでなく、バイポーラデバイスにおいても、静電
気等により発生する高電圧による破壊を効果的に防ぐ必
要が生じてきた。In recent years, as semiconductor devices have become faster and more highly integrated,
Devices are becoming smaller and smaller, and MO3 with low electrostatic strength
It has become necessary not only for elements but also for bipolar devices to effectively prevent destruction due to high voltages generated by static electricity and the like.
第２図（］１）、 （２＋、 （３１はそれぞれ従来例
による静電破壊防止素子の平面図、断面図、等価回路図
である。FIG. 2 (]1), (2+, and (31) are a plan view, a sectional view, and an equivalent circuit diagram, respectively, of a conventional electrostatic breakdown prevention element.
図において、１はｐ型の基板、２は埋め込まれたｎ ４
型のコレクタコンタクト層、３はｎ型のコレクタ層、４
はｐ型の抵抗領域、５はｐ゛型のベース領域、６はエミ
ック領域、７は絶縁層、８゜９は配線層である。In the figure, 1 is a p-type substrate, 2 is a buried n4
3 is an n-type collector contact layer; 4 is an n-type collector contact layer;
5 is a p-type resistance region, 5 is a p-type base region, 6 is an emic region, 7 is an insulating layer, and 8.9 is a wiring layer.
電源電圧とその端子をＶ。Ｃ１接地電圧とその端子をＶ
Ｅ Ｅ 、入力端子をＩＮ 、ダイオードをＤ＋＋Ｄ
２、トランジスタを０１、抵抗をＲであられす。The power supply voltage and its terminals are V. C1 ground voltage and its terminal to V
E E, input terminal IN, diode D++D
2. The transistor is 01 and the resistor is R.
このような素子を静電破壊防止素子として、集積回路等
半導体デバイスの入力部に配設することにより、内部回
路を保護することができる。By disposing such an element as an electrostatic damage prevention element at the input section of a semiconductor device such as an integrated circuit, the internal circuit can be protected.
すなわち、入力端子ＩＮに高電圧の入力パルスの入来に
より、トランジスタＱ、をＯＮさせ、この入力パルスを
入力端子ＩＮ （！：電源端子ＶＣＣ間で吸収している
。That is, when a high voltage input pulse enters the input terminal IN, the transistor Q is turned on, and this input pulse is absorbed between the input terminal IN (!: power supply terminal VCC).
第３図、第４図は図示の等価回路によりシュミレーショ
ンした結果による、入力パルスと入力端子電圧対時間の
関係を示す図である。FIGS. 3 and 4 are diagrams showing the relationship between input pulses and input terminal voltage versus time based on simulation results using the illustrated equivalent circuit.
図において、図示の波形を有する波高値±５００ｖの入
力パルス■に対し、入力端子ＩＮにあられれるパルス電
圧の波高値■は３８Ｖ程度となる。In the figure, for an input pulse (2) having the waveform shown and having a peak value of ±500V, the peak value (2) of the pulse voltage applied to the input terminal IN is about 38V.
デバイスの微細化による静電耐力の低下にともない、さ
らに高性能の静電破壊防止素子が要求されるようになっ
た。As the electrostatic strength of devices decreases due to miniaturization of devices, even higher performance electrostatic damage prevention elements are required.
上記問題点の解決は、トランジスタ（ＱＩ）のコレクタ
を電源端子（ＶＣＣ）に、エミッタを入力端子（ＩＮ）
に、ベースを抵抗（Ｒ）を経由して入力端子（ＩＮ）に
それぞれ接続し、該抵抗（Ｒ）を形成するｐｎ接合の両
領域（４）と（３）、および基板（１）とでトランジス
タ（Ｃ２）を形成させ、該基板（１）を接地端子（Ｖ
ＥＥ）に接続するように形成してなる本発明による静電
破壊防止素子により達成される。The solution to the above problem is to connect the collector of the transistor (QI) to the power supply terminal (VCC) and the emitter to the input terminal (IN).
The bases are respectively connected to the input terminal (IN) via the resistor (R), and both regions (4) and (3) of the pn junction forming the resistor (R) and the substrate (1) are connected to each other. A transistor (C2) is formed, and the substrate (1) is connected to a ground terminal (V
This is achieved by the electrostatic breakdown prevention element according to the present invention, which is formed so as to be connected to EE).
本発明は、入力パルスをＩＮ Ｖｃｅ間だけでなく、
′ＩＮ ＶＥＥ間においても吸収すること
により、この種素子の静電破壊防止能力を向上するもの
である。The present invention provides input pulses not only between IN and Vce, but also between IN and Vce.
By absorbing it even between 'IN and VEE, the ability to prevent electrostatic damage of this type of element is improved.
第１図＋１）、 ＋２）； ＋３）はそれぞれ本発明に
よる静電破壊防止素子の平面図、断面図、等価回路図で
ある。Figures 1 +1), +2) and +3) are a plan view, a sectional view, and an equivalent circuit diagram, respectively, of an electrostatic breakdown prevention element according to the present invention.
図は従来例に寄生トランジスタＱ２を追加したものであ
る。The figure shows a conventional example in which a parasitic transistor Q2 is added.
寄生トランジスタＱ２はつぎのようにして形成する。Parasitic transistor Q2 is formed as follows.
素子分離領域として絶縁層１０で抵抗Ｒの周囲を囲うこ
とにより、抵抗Ｒを形成するｐｎ接合のｎ型領域３を、
ｎ＋型のコレクタコンタクト層２に接続しないで、ｐ型
の基板１に接続する。このようにして縦型ｐｎｐ寄生ト
ランジスタが形成される。By surrounding the resistor R with an insulating layer 10 as an element isolation region, the n-type region 3 of the pn junction forming the resistor R is
It is connected to the p-type substrate 1 without being connected to the n+ type collector contact layer 2. In this way, a vertical pnp parasitic transistor is formed.
これは、製造工程で抵抗Ｒの島領域に埋込層を形成しな
いようにすることにより容易に実現できる。This can be easily achieved by not forming a buried layer in the island region of the resistor R during the manufacturing process.
このような素子を静電破壊防止素子として、集積回路等
半導体デバイスの入力部に配設することにより、従来例
の素子以上にデバイスの静電耐力を向上できる。By disposing such an element as an electrostatic damage prevention element at the input section of a semiconductor device such as an integrated circuit, the electrostatic strength of the device can be improved more than that of conventional elements.
本発明では、入力端子ＩＮに高電圧の入力パルスの入来
により、トランジスタＱｌ、Ｑ２をＯＮさせ、この入力
パルスを入力端子ＩＮと電源端子ＶＣＣ間と、入力端子
ＩＮと接地端子■。０間で吸収している。In the present invention, when a high-voltage input pulse enters the input terminal IN, the transistors Ql and Q2 are turned on, and this input pulse is connected between the input terminal IN and the power supply terminal VCC, and between the input terminal IN and the ground terminal (2). It is absorbed between 0 and 0.
第３図、第４図において、図示の波形を有する波高値±
５００ｖの入力パルス■に対し、入力端子ＩＮにあられ
れるパルス電圧の波高値■は２１Ｖ程度となり、従来例
の波高値■の３８Ｖに比し向上していることがわかる。In Fig. 3 and Fig. 4, the peak value ±
It can be seen that for an input pulse (2) of 500 V, the peak value (2) of the pulse voltage applied to the input terminal IN is about 21V, which is improved compared to the peak value (2) of the conventional example, which was 38V.
以上説明したように本発明による静電破壊防止素子を入
力部に入れることにより、半導体デバイスの静電耐力を
向上することができる。As explained above, by inserting the electrostatic damage prevention element according to the present invention into the input section, the electrostatic withstand strength of the semiconductor device can be improved.
第１図（１１，＋２１． （３１はそれぞれ本発明によ
る静電破壊防止素子の平面図、断面図、等価回路図、第
２図（１１，（２１，（３）はそれぞれ従来例による静
電破壊防止素子の平面図、断面図、等価回路図、第３図
、第４図は入力パルスと入力端子電圧対時間の関係を示
す図である。
図において、
■はｐ型の基板、
２はｎ゛型のコレクタコンタクト層、
３はｎ型のコレクタ層、
４はｐ型の抵抗領域、
５はｐ３型のベース領域、
６は抵抗領域、
７は絶縁層、
８．９は配線層、
１０は素子分離領域で絶縁層、
ＶＣＣは電源電圧とその端子、
■ゆ、は接地電圧とその端子、
ＩＮは入力端子、
Ｄ、、Ｄ２はダイオード、
Ｑ、、Ｑ２、トランジスタ、
Ｒは抵抗
である。
Ａ−Ａ’話−面
従来例ρ士吉用１翔問埼
ρ ０．１ ０，２ ０．３ＪＩＲト
戸梢 （ｎｓ）
牟３ 喝
Ｄｏ、（０・２０・３
２凄「 ルミ （ｙ１５）
茅４０Figure 1 (11, +21. (31 is a plan view, cross-sectional view, and equivalent circuit diagram, respectively, of the electrostatic breakdown prevention element according to the present invention, and Figure 2 (11, (21, and 3) are the electrostatic breakdown according to the conventional example, respectively. The plan view, cross-sectional view, and equivalent circuit diagram of the destruction prevention element, as well as Figures 3 and 4, are diagrams showing the relationship between input pulse and input terminal voltage versus time. In the figure, ① is a p-type substrate, 2 is a n-type collector contact layer, 3 is an n-type collector layer, 4 is a p-type resistance region, 5 is a p3-type base region, 6 is a resistance region, 7 is an insulating layer, 8.9 is a wiring layer, 10 is the insulating layer in the element isolation region, VCC is the power supply voltage and its terminals, ■Y is the ground voltage and its terminals, IN is the input terminal, D, , D2 are the diodes, Q, , Q2 are the transistors, and R is the resistor. . A-A' Story - Side Conventional Example ρ Shikichi Use 1 Sho Question Saki ρ 0.1 0,2 0.3 JIR To
Tokozue (ns) Mu 3 Do, (0.20.3 2 great) Rumi (y15) Kaya 40
Claims (1)
＿Ｃ）に、エミッタを入力端子（ＩＮ）に、ベースを抵
抗（Ｒ）を経由して入力端子（ＩＮ）にそれぞれ接続し
、 該抵抗（Ｒ）を形成するｐｎ接合の両領域（４）と（３
）、および基板（１）とでトランジスタ（Ｑ＿２）を形
成させ、 該基板（１）を接地端子（Ｖ＿Ｅ＿Ｅ）に接続するよう
に形成してなることを特徴とする静電破壊防止素子。[Claims] The collector of the transistor (Q_1) is connected to the power supply terminal (V_C
_C), the emitter is connected to the input terminal (IN), the base is connected to the input terminal (IN) via the resistor (R), and both regions (4) of the pn junction forming the resistor (R) are connected. (3
) and a substrate (1) to form a transistor (Q_2), and the substrate (1) is connected to a ground terminal (V_E_E).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7473685A JPS61232657A (en) | 1985-04-09 | 1985-04-09 | Electrostatic breakdown preventive element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7473685A JPS61232657A (en) | 1985-04-09 | 1985-04-09 | Electrostatic breakdown preventive element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61232657A true JPS61232657A (en) | 1986-10-16 |
Family
ID=13555816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7473685A Pending JPS61232657A (en) | 1985-04-09 | 1985-04-09 | Electrostatic breakdown preventive element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61232657A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7053463B2 (en) | 1999-12-10 | 2006-05-30 | Stmicroelectronics S.R.L. | High-voltage integrated vertical resistor and manufacturing process thereof |
| US7294542B2 (en) | 2000-05-15 | 2007-11-13 | Nec Electronics Corporation | Method of fabricating a semiconductor device having CMOS transistors and a bipolar transistor |
| US7629210B2 (en) | 2000-05-15 | 2009-12-08 | Nec Corporation | Method for fabricating an ESD protection apparatus for discharging electric charge in a depth direction |
-
1985
- 1985-04-09 JP JP7473685A patent/JPS61232657A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7053463B2 (en) | 1999-12-10 | 2006-05-30 | Stmicroelectronics S.R.L. | High-voltage integrated vertical resistor and manufacturing process thereof |
| US7294542B2 (en) | 2000-05-15 | 2007-11-13 | Nec Electronics Corporation | Method of fabricating a semiconductor device having CMOS transistors and a bipolar transistor |
| US7629210B2 (en) | 2000-05-15 | 2009-12-08 | Nec Corporation | Method for fabricating an ESD protection apparatus for discharging electric charge in a depth direction |
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