JPS61231702A - Manufacture of circuit board - Google Patents

Manufacture of circuit board

Info

Publication number
JPS61231702A
JPS61231702A JP60073050A JP7305085A JPS61231702A JP S61231702 A JPS61231702 A JP S61231702A JP 60073050 A JP60073050 A JP 60073050A JP 7305085 A JP7305085 A JP 7305085A JP S61231702 A JPS61231702 A JP S61231702A
Authority
JP
Japan
Prior art keywords
circuit board
plating
substrate
photosensitive resin
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60073050A
Other languages
Japanese (ja)
Other versions
JPH0682570B2 (en
Inventor
田辺 功二
矢ケ崎 琢也
清水 次雄
村川 哲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60073050A priority Critical patent/JPH0682570B2/en
Publication of JPS61231702A publication Critical patent/JPS61231702A/en
Publication of JPH0682570B2 publication Critical patent/JPH0682570B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Adjustable Resistors (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Manufacture Of Switches (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、各種電子機器に使用される各種電子部品取付
は用の回路板や、スイッチ、エンコーダ等の各種電子部
品の接点回路板の製造法に関するものである。
Detailed Description of the Invention (Industrial Application Field) The present invention is directed to the manufacture of circuit boards for mounting various electronic components used in various electronic devices, and contact circuit boards for various electronic components such as switches and encoders. It is about law.

(従来例の構成とその問題点) 従来の回路板の製造法について、第1図により説明する
。第1図(a)に示した基体となるフエノ−ル積層板1
に貼り付けた銅1’i2の上に、第1図(b)に示すよ
うに感光性樹脂層3を形成した後、所定のパターンを有
する選択的遮光板4を被せて光5を照射する。これに現
像処理を施すと、第1図(c)に示すように、所定のパ
ターンで銅箔2の一部が選択的に露出する。これに化学
的エツチングを施して、第1図(d)に示すように露出
した箇所の銅M2を除去した後、残留した感光性樹脂層
3を剥離すると第1図(e)に示す所定のパターンを有
する回路板が得られる。
(Structure of a conventional example and its problems) A conventional method for manufacturing a circuit board will be explained with reference to FIG. Phenol laminate plate 1 serving as a substrate shown in FIG. 1(a)
After forming a photosensitive resin layer 3 as shown in FIG. 1(b) on the copper 1'i2 attached to the surface, a selective light-shielding plate 4 having a predetermined pattern is covered and light 5 is irradiated. . When this is subjected to a development process, a part of the copper foil 2 is selectively exposed in a predetermined pattern as shown in FIG. 1(c). This is chemically etched to remove the exposed copper M2 as shown in FIG. 1(d), and then the remaining photosensitive resin layer 3 is peeled off to form a predetermined area as shown in FIG. 1(e). A circuit board with a pattern is obtained.

しかしながら、エツチングの際に、配線回路を形成した
銅箔の側面が腐蝕される結果、設計の線幅より細くなり
、細かい設計線幅の場合には断線が生ずるため、高密度
配線回路板を形成することは難しいという問題点があっ
た6また1回路配線に用いられる銅M2の実効使用率は
、一般的に5%ないし30%と低く、かつ、配線回路上
にさらに金等の貴金属鍍金を行う際には、電気的導通の
ための引出し線が必要なため最終製品には必要のない配
線部分が多くなり共に製造コストを上昇させる原因にな
っているという問題点もあった。
However, during etching, the side surfaces of the copper foil on which the wiring circuit is formed are corroded, resulting in lines that are thinner than the designed line width, and in the case of fine designed line widths, disconnections occur, making it difficult to form high-density wiring circuit boards. 6 In addition, the effective usage rate of copper M2 used for circuit wiring is generally low at 5% to 30%, and it is difficult to further plate the wiring with precious metals such as gold. When doing so, there is a problem in that a lead wire is required for electrical continuity, which increases the number of unnecessary wiring parts in the final product, which also causes an increase in manufacturing costs.

また、配線回路上を金属等で作られた刷子が摺動する摺
動接点として用いられる回路板の場合には、基体である
フェノール積層板と配線回路の境界部分に段差があるた
め、摺動寿命が短かく、かつ刷子が摺動する際に上記の
段差に引掛る動作不良を起こすという問題点もあった。
In addition, in the case of a circuit board used as a sliding contact where a brush made of metal or the like slides on the wiring circuit, there is a step at the boundary between the phenol laminate that is the base and the wiring circuit, so the sliding contact There was also the problem that the lifespan was short and that when the brush slid, it got caught on the above-mentioned steps, causing malfunction.

この対策として、銅i1の厚さを6μmないし13μm
まで薄くする方法が採られているが、銅箔の薄さには製
造上の限界があり根本的な解決にはなっていない。
As a countermeasure for this, the thickness of copper i1 is increased from 6 μm to 13 μm.
Methods have been adopted to make the copper foil as thin as possible, but there are manufacturing limits to how thin copper foil can be, so this has not been a fundamental solution.

また、上記の段差をなくする目的で、上述のエツチング
法によってフェノール積層板やエポキシ積層板上に配線
回路を形成した後、その表面を硬質鏡面板で加熱加圧し
て、配線回路と基体表面とを同一平面化する方法も知ら
れているが、完全に段差をなくすることは難しく、高密
度配線の困難性を何ら解決しないばかりか、逆に硬質鏡
面板で加熱加圧する工程で回路が規定位置からずれると
いう問題点があり、さらに加熱加圧工程に長時間を要す
るため高価な製品となるという問題点もあった。
In addition, in order to eliminate the above-mentioned level difference, a wiring circuit is formed on a phenol laminate or an epoxy laminate by the above-mentioned etching method, and then the surface is heated and pressurized with a hard mirror plate to form a bond between the wiring circuit and the substrate surface. There is also a known method of making the same plane, but it is difficult to completely eliminate the level difference, and not only does it not solve the difficulty of high-density wiring, but the process of heating and pressurizing a hard mirror plate makes it difficult to define the circuit. There is a problem that the product may shift from its position, and furthermore, the heating and pressurizing process requires a long time, resulting in an expensive product.

(発明の目的) 本発明は上記の問題点をすべて解決するもので、高密度
配線回路板の形成が容易で、材料の歩留りが高く、量産
性に富むため極めて安価に製造することができ、かつ、
段差のない平滑な表面状態が得られるため、摺動接点回
路板として用いる場合は飛踊的に摺動寿命が向上する回
路板の製造法を提供しようとするものである。
(Objective of the Invention) The present invention solves all of the above-mentioned problems, and it is easy to form a high-density wiring circuit board, has a high material yield, and is highly suitable for mass production, so it can be manufactured at an extremely low cost. and,
The present invention aims to provide a method of manufacturing a circuit board that dramatically improves the sliding life when used as a sliding contact circuit board since a smooth surface with no steps can be obtained.

(発明の構成) 本発明は、導電性を有する仮基体上に形成した感光性樹
脂層に任意のパターンを露光した後、これを現像して選
択的に仮基体を露出せしめ、さらにこの露出部分に任意
の厚さの鍍金を施した後、これを接着剤を介して本基体
と接着し、しかる後に仮基体を取り除いて回路板を得る
回路板の製造法であり、仮基本を取り除いた後の回路板
は、配線回路と基体表面の境界に段差がなく、平滑に形
成されるものである。
(Structure of the Invention) The present invention involves exposing a photosensitive resin layer formed on a conductive temporary substrate to light with an arbitrary pattern, developing the pattern to selectively expose the temporary substrate, and furthermore, exposing the exposed portion of the temporary substrate. This is a circuit board manufacturing method in which a circuit board is obtained by applying plating to a desired thickness, then bonding it to the main base using an adhesive, and then removing the temporary base. The circuit board has no step difference at the boundary between the wiring circuit and the surface of the substrate, and is formed smoothly.

(実施例の説明) 本発明の実施例を第2図により説明する。第2図(a)
ないしくh)は本発明による回路板の製造法を工程を追
って示した断面図である。
(Description of Embodiments) An embodiment of the present invention will be described with reference to FIG. Figure 2(a)
to h) are cross-sectional views showing step by step the method for manufacturing a circuit board according to the present invention.

第2図(a)および(b)に示すように、仮基体となる
厚さ0.1閣、表面粗さ0.05μmのステンレス鋼板
6の表面に、膜厚が約1μmになるように感光性樹脂(
東京応化工業株式会社製、商品番号0FPR−2’)を
、スピンナーを用いて均一に塗布した後、乾燥して感光
性樹脂層3を形成する。
As shown in FIGS. 2(a) and 2(b), the surface of a stainless steel plate 6 with a thickness of 0.1 mm and a surface roughness of 0.05 μm, which will serve as a temporary substrate, is exposed to light to a film thickness of approximately 1 μm. Resin (
0FPR-2' (manufactured by Tokyo Ohka Kogyo Co., Ltd.) is uniformly applied using a spinner and then dried to form a photosensitive resin layer 3.

第2図(c)および(d)に示すように、線幅1μmな
いし100μm、長さ10mnの選択的遮光板である、
ポジ形フィルム4を上記の感光性樹脂層3に密着させて
キャノンPLA−300Fを使用して10秒間露光した
後、現像液(東京応化工業株式会社製、専用現像液)を
用いて現像、水洗を行った後、温度150℃で10分間
乾燥し、ポジ形フィルム4のパターンに一致したステン
レス露出パターン部を得た。
As shown in FIGS. 2(c) and (d), it is a selective light shielding plate with a line width of 1 μm to 100 μm and a length of 10 mm.
After the positive film 4 was brought into close contact with the above photosensitive resin layer 3 and exposed for 10 seconds using Canon PLA-300F, it was developed using a developer (manufactured by Tokyo Ohka Kogyo Co., Ltd., special developer) and washed with water. After that, it was dried at a temperature of 150° C. for 10 minutes to obtain an exposed pattern of stainless steel that matched the pattern of the positive film 4.

次に、第2図(e)に示すように、上記のステンレス露
出パターン部に、厚さ0.5μmの全鍍金(田中貴金属
工業株式会社製、商品名AUROBOND TN)を下
地にし、その上に厚さ1.5μmのニッケル鍍金を施し
、鍍金層7を形成した。
Next, as shown in FIG. 2(e), the above stainless steel exposed pattern was coated with full plating (trade name: AUROBOND TN, manufactured by Tanaka Kikinzoku Kogyo Co., Ltd.) with a thickness of 0.5 μm, and then Nickel plating was applied to a thickness of 1.5 μm to form a plating layer 7.

次に、剥離液(東京応化工業株式会社製、専用剥離液)
を用いて感光性樹脂層3を剥離すると第2図(f)の状
態となる。さらに、第2図(g)に示すように、ステン
レス鋼板6の鍍金層7の形成面に、エポキシ樹脂8 (
アミコンファーイースト社製、商品番号927−10 
E)を全面にわたって塗布し、本基体となる厚さ1.5
μmのエポキシガラス積層板9に接着した後、温度90
0℃で20分間加熱してエポキシ樹脂8を硬化させる。
Next, remover liquid (manufactured by Tokyo Ohka Kogyo Co., Ltd., special remover liquid)
When the photosensitive resin layer 3 is peeled off using a method, the state shown in FIG. 2(f) is obtained. Furthermore, as shown in FIG. 2(g), an epoxy resin 8 (
Manufactured by Amicon Far East, product number 927-10
E) is applied over the entire surface to a thickness of 1.5 to become the main base.
After adhering to the μm epoxy glass laminate 9, the temperature was 90°C.
The epoxy resin 8 is cured by heating at 0° C. for 20 minutes.

エポキシ樹脂8を硬化した後、仮基体のステンレス鋼板
6を剥がすと、第2図(h)に示すような、仮基体の鍍
金層7を本基体のエポキシガラス積層板9に転写した鏡
面状の回路板が得られる。
After curing the epoxy resin 8, when the stainless steel plate 6 of the temporary base is peeled off, a mirror-like surface is created by transferring the plating layer 7 of the temporary base to the epoxy glass laminate 9 of the main base, as shown in FIG. 2(h). A circuit board is obtained.

上述の本発明による回路板と比較するために、同一の回
路パターンで従来のエツチング法を用いた回路板を作っ
た。すなわち、厚さ6μmの銅箔が貼付された厚さ1.
5mmのエポシ積層板をエツチングし、さらに厚さ1μ
mの下地鍍金の上に厚さ0.5μmの全鍍金を施して回
路板を得た。
For comparison with the circuit board according to the invention described above, a circuit board with the same circuit pattern was made using a conventional etching method. In other words, a 1.0 mm thick copper foil with a thickness of 6 μm is pasted.
Etched a 5mm epoxy laminate and further added a 1μ thick layer.
A circuit board was obtained by applying full plating to a thickness of 0.5 μm on the base plating of 0.5 μm.

上記の実施例および比較例について、回路パターンの線
幅を測定し設計値と比較した結果を下表に示す。
The table below shows the results of measuring the line widths of the circuit patterns for the above examples and comparative examples and comparing them with design values.

単位μm 回路パターンの線幅の比較 表から判るように、従来のエツチング法では。Unit μm Comparison of line width of circuit patterns As you can see from the table, with the conventional etching method.

一般に設計線幅が痩せ、従って、線幅が5μmでは断線
が生じ、線幅が1μmでは全く回路パターンが形成され
ないのに対し1本発明による実施例では、何れの線幅も
忠実に再現している。
In general, the designed line width is thin, so if the line width is 5 μm, disconnection will occur, and if the line width is 1 μm, no circuit pattern will be formed.However, in the embodiment according to the present invention, any line width can be faithfully reproduced. There is.

また、上記各側の回路パターンの幅方向に、接点部半径
が1.4+mlの洋白製刷子を接触圧Logの条件で摺
動させ、電気的0N−OFFの状態をスペクトラムアナ
ライザーで分析した結果、比較例の回路パターンでは、
ON→OFF時、OFF→ON時共に実験の所期よりチ
ャタリングが発生するのに対し、実施例の回路パターン
では20万回反復摺動した後でもチャタリングは発生し
なかった。
In addition, a nickel silver brush with a contact radius of 1.4+ml was slid in the width direction of the circuit pattern on each side at a contact pressure of Log, and the electrical ON-OFF state was analyzed using a spectrum analyzer. , In the comparative example circuit pattern,
While chattering occurred as expected in the experiment both during ON→OFF and OFF→ON, in the circuit pattern of the example, no chattering occurred even after repeated sliding 200,000 times.

なお、本発明における導電性仮基体は、望ましくは表面
粗さ5μm以内のステンレス鋼箔、チタン箔、アルミニ
ウム箔等の金属箔やこれらの金属箔を合成樹脂フィルム
とラミネートし一体化した複合箔、あるいは導電性合成
樹脂フィルムから選定して使用することができる。さら
に、最終的に基体となる本基体には、フェノール積層板
やエポキシ積層板のみでなく、セラミック基板や金属板
、合成樹脂成形品等を任意に選定することが可能である
ことは言うまでもない。
The conductive temporary substrate in the present invention is preferably a metal foil such as stainless steel foil, titanium foil, or aluminum foil with a surface roughness of 5 μm or less, or a composite foil in which these metal foils are laminated and integrated with a synthetic resin film. Alternatively, a conductive synthetic resin film can be selected and used. Furthermore, it goes without saying that for the final substrate, not only a phenol laminate or an epoxy laminate, but also a ceramic substrate, a metal plate, a synthetic resin molded product, etc. can be arbitrarily selected.

(発明の効果) 本発明による回路板の形成法によれば、導電性を有する
仮基体の露出部分に鍍金によって回路パターンを形成す
るため、従来のエツチング法のように回路パターンを形
成した銅箔の側面を腐蝕する現象はなく、従って、回路
の配線線幅が設計値より細くならず、線幅が1μmない
し5μm程度の高密度配線回路板が容易に製造でき、か
つ従来のエツチング法のように断線の恐れもなく、信頼
性の高い、高品質の回路板が得られる。また、鍍金には
、11品に必要な回路部分のみの鍍金材料があればよく
、鍍金層の厚さも自由に選択できるので材料の無駄がな
く極めて安価に製造することができる。
(Effects of the Invention) According to the method for forming a circuit board according to the present invention, since a circuit pattern is formed by plating on the exposed portion of a temporary conductive substrate, a copper foil on which a circuit pattern is formed as in the conventional etching method is used. There is no phenomenon of corrosion on the side surfaces of the etching process, and therefore, the wiring line width of the circuit does not become thinner than the design value, and high-density wiring circuit boards with a line width of about 1 μm to 5 μm can be easily manufactured, and it can be easily manufactured using conventional etching methods. A highly reliable, high-quality circuit board can be obtained without fear of disconnection. Further, for plating, it is only necessary to use the plating material for only the circuit parts necessary for the 11 products, and the thickness of the plating layer can be freely selected, so there is no wastage of materials, and the product can be manufactured at an extremely low cost.

さらに、回路面を摺動接点として利用する各種スイッチ
やエンコーダ等の製品の場合には、配線回路の鍍金層と
基体の両表面は平滑な同一平面に形成されているため、
従来の接点基板と比較して摺動寿命が約100倍から1
000倍になる飛羅的な伸びを示し、また、摺動感勉も
従来品のように引掛り感がなく滑らかで、引掛りによる
動作不良は皆無である。
Furthermore, in the case of products such as various switches and encoders that use the circuit surface as a sliding contact, both the plating layer of the wiring circuit and the surface of the base are formed on the same smooth plane.
The sliding life is approximately 100 times longer than that of conventional contact boards.
It shows an incredible elongation of 1,000 times, and the sliding feel is smooth without any feeling of catching like conventional products, and there are no malfunctions due to catching.

以上説明したように、従来の品質、設計および性能上の
欠点をすべて解消することができるばかりでなく、さら
に量産性に優れるため製造コストの低減に著しい効果が
ある。
As explained above, not only can all of the conventional defects in quality, design, and performance be eliminated, but also it is excellent in mass production, which has a significant effect on reducing manufacturing costs.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)ないしくe)は従来の回路板の製造法を工
程順に描いた断面図、第2図(a)ないしくh)は本発
明による回路板の製造法を工程順に描いた断面図である
。 1.9 ・・・基体、 2・・・銅箔、 3・・・感光
性樹脂層、 4 ・・・選択的遮光板、 5 ・・・光
、6・・・仮基体、 7 ・・・鍍金層、 8 ・・・
エポキシ樹脂。 特許出願人 松下電器産業株式会社 第1図 く;ニレ
Figures 1 (a) to e) are cross-sectional views depicting the conventional circuit board manufacturing method in the order of steps, and Figures 2 (a) to h) depicting the circuit board manufacturing method according to the present invention in the order of the steps. FIG. 1.9...Substrate, 2...Copper foil, 3...Photosensitive resin layer, 4...Selective light shielding plate, 5...Light, 6...Temporary base, 7... Plating layer, 8...
Epoxy resin. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 1: Elm

Claims (5)

【特許請求の範囲】[Claims] (1)導電性を有する仮基体上に感光性樹脂層を形成し
、これを選択的遮光板で覆ってその上から光を照射して
上記の感光性樹脂層の少なくとも一部に露光したのち現
像処理を行い、感光性樹脂層が除かれ仮基体が露出した
部分に鍍金を施して選択的に鍍金層を形成し、次に感光
性樹脂層および鍍金層の上に、あるいは本基体の上に接
着剤を塗布して本基体と固着した後、物理的あるいは化
学的方法によって仮基体を除去することを特徴とする回
路板の製造法。
(1) After forming a photosensitive resin layer on a temporary conductive substrate, covering this with a selective light-shielding plate, and irradiating light from above to expose at least a part of the photosensitive resin layer, A development process is performed, and the portions where the photosensitive resin layer is removed and the temporary substrate is exposed are plated to selectively form a plating layer, and then a plating layer is formed on the photosensitive resin layer and the plating layer, or on the main substrate. A method for manufacturing a circuit board, which comprises applying an adhesive to the substrate and fixing it to the main substrate, and then removing the temporary substrate by a physical or chemical method.
(2)鍍金を施したのち感光性樹脂層を剥離し、仮基体
および鍍金層の上に、あるいは本基体の上に接着剤を塗
布して本基体と固着することを特徴とする特許請求の範
囲第(1)項記載の回路板の製造法。
(2) After plating, the photosensitive resin layer is peeled off, and an adhesive is applied on the temporary substrate and the plating layer or on the main substrate to fix it to the main substrate. A method for manufacturing a circuit board according to scope item (1).
(3)鍍金層を複数の金属層としたことを特徴とする特
許請求の範囲第(1)項記載の回路板の製造法。
(3) The method for manufacturing a circuit board according to claim (1), wherein the plating layer is a plurality of metal layers.
(4)複数の鍍金層のうち、最初の鍍金層を金、白金、
銀、ロジウムおよびパラジウムより選ばれた金属である
ことを特徴とする特許請求の範囲第(3)項記載の回路
板の製造法。
(4) Among multiple plating layers, the first plating layer is gold, platinum,
The method for manufacturing a circuit board according to claim 3, wherein the metal is selected from silver, rhodium, and palladium.
(5)鍍金層を形成したのち、又は感光性樹脂層を剥離
したのち、鍍金により形成した回路面に電気的抵抗層を
単層又は複数層形成したことを特徴とする特許請求の範
囲第(1)項ないし第(4)項の何れか1項記載の回路
板の製造法。
(5) After forming the plating layer or peeling off the photosensitive resin layer, a single or multiple electrical resistance layer is formed on the circuit surface formed by plating. A method for manufacturing a circuit board according to any one of items 1) to (4).
JP60073050A 1985-04-06 1985-04-06 Circuit board manufacturing method Expired - Lifetime JPH0682570B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60073050A JPH0682570B2 (en) 1985-04-06 1985-04-06 Circuit board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60073050A JPH0682570B2 (en) 1985-04-06 1985-04-06 Circuit board manufacturing method

Publications (2)

Publication Number Publication Date
JPS61231702A true JPS61231702A (en) 1986-10-16
JPH0682570B2 JPH0682570B2 (en) 1994-10-19

Family

ID=13507151

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60073050A Expired - Lifetime JPH0682570B2 (en) 1985-04-06 1985-04-06 Circuit board manufacturing method

Country Status (1)

Country Link
JP (1) JPH0682570B2 (en)

Also Published As

Publication number Publication date
JPH0682570B2 (en) 1994-10-19

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