JPS61230352A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS61230352A
JPS61230352A JP7085985A JP7085985A JPS61230352A JP S61230352 A JPS61230352 A JP S61230352A JP 7085985 A JP7085985 A JP 7085985A JP 7085985 A JP7085985 A JP 7085985A JP S61230352 A JPS61230352 A JP S61230352A
Authority
JP
Japan
Prior art keywords
circuit
mos
input terminal
switch
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7085985A
Other languages
Japanese (ja)
Inventor
Hirosuke Kurihara
啓輔 栗原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7085985A priority Critical patent/JPS61230352A/en
Publication of JPS61230352A publication Critical patent/JPS61230352A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To increase electrostatic breakdown resistance during the period while the power is not thrown-in during the time of the storing and manufacture and the like of a MOS-IC having high input impedance by arranging a switch by a MOS transistor in series with an input terminal. CONSTITUTION:In an input section having extremely high input impedance, an information from an input terminal 1 is received by an amplifying circuit 2 by MOS transistor constitution and outputted. A MOS switch 5 through which high resistance is acquired by a minute area is inserted in series with the input terminal 1, the switch 4 is brought to an open state when a power supply is not closed, and an internal circuit is separated electrically from the input terminal 1 and can be protected from static electricity. Accordingly, a protection circuit having high resistance by the extremely fine area is inserted to an input section, thus obtaining a semiconductor integrated circuit having large electrostatic resistance.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は静電破壊耐力の向上をはかった半導体集積回路
に係り、特に高入力インピーダンスを有するＭＯＳ−Ｉ
Ｃの静電気に対する破壊防止に好適な半導体集積回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit with improved electrostatic breakdown resistance, and in particular to a MOS-I circuit having high input impedance.
The present invention relates to a semiconductor integrated circuit suitable for preventing damage caused by static electricity.

〔発明の背景〕[Background of the invention]

従来のＭＯＳ−ＩＣの静電破壊防止方法としては、一般
の半導体カタログたとえば日立ロジックＩＣ’ＨＤ１４
０５２Ｂ“などに見られるように、抵抗とダイオードの
組合せの挿入により入力端子を保護している１、シかし
ながら非常な高入力インピーダンスが要求されるような
ＭＯＳ−ＩＣについては、保護回路の挿入による寄生素
子が生じて目的とする回路機能を損うため有効な静電破
壊防止方法がなかった。As a conventional method for preventing electrostatic damage of MOS-IC, there is a general semiconductor catalog such as Hitachi Logic IC'HD14.
052B", input terminals are protected by inserting a combination of resistors and diodes. However, for MOS-ICs that require extremely high input impedance, the protection circuit is There has been no effective method for preventing electrostatic damage since parasitic elements are generated due to insertion and impair the intended circuit function.

・〔発明の目的〕 本発明の目的は高入力インピーダンスを有するＭＯＳ−
ＩＣの保管および製造時などの電源未投入時の静電破壊
耐力を向上させる有効な保護回路を備えた半導体集積回
路を提供するＩこある１゜ 〔発明の概要〕 本発明は高入力インピーダンスの入力部をもつＭＯＳ−
ＩＣを特に保管および製造時の静電破壊から防止すべく
、入力端子に直列にＭＯＳトランジスタによるスイッチ
を配置することにより、電源未投入時に入力端子から内
部回路への導体路をし′Ｆ１放状態にした半導体４Ａ積
回路である０ 〔発明の実施例〕 以下に本発明の一実施例を図面により説明する０ 第１図（４）は本発明による保護回路を挿入した高入力
インピーダンスの半導体集積回路の一実施例を示す回路
図である。第１図（４）において、１は入力端子ＩＮ、
２はＭＯＳ）ランジスタで構成される増幅回路、３は保
護回路、４は保護用スイッチ（ＭＯＳスイッチ）、５は
保護用ダイオードＤｐである。また第１図の）は第１回
頭の等価回路図である。なお、各図面を通じて同一符号
または記号は同一または相当部分を示すものとする。本
回路は入力端子１の情報をＭＯＳトランジスタ構成の増
幅回路２で受けて出力する非常な高入力インピーダンス
の入力部である。・[Object of the invention] The object of the present invention is to provide a MOS-
This invention provides a semiconductor integrated circuit equipped with an effective protection circuit that improves electrostatic breakdown resistance when the power is not turned on during IC storage and manufacturing. MOS- with input section
In order to prevent the IC from being damaged by electrostatic discharge, especially during storage and manufacturing, by placing a MOS transistor switch in series with the input terminal, a conductive path from the input terminal to the internal circuit is established when the power is not turned on, and the 'F1 is released. [Embodiment of the Invention] An embodiment of the present invention will be explained below with reference to the drawings. Figure 1 (4) shows a high input impedance semiconductor integrated circuit in which a protection circuit according to the present invention is inserted. FIG. 1 is a circuit diagram showing an example of a circuit. In FIG. 1 (4), 1 is the input terminal IN;
2 is an amplifier circuit composed of a MOS transistor, 3 is a protection circuit, 4 is a protection switch (MOS switch), and 5 is a protection diode Dp. 1) is an equivalent circuit diagram at the beginning of the first circuit. Note that the same reference numerals or symbols indicate the same or corresponding parts throughout the drawings. This circuit is an input section with extremely high input impedance that receives information from an input terminal 1 through an amplifier circuit 2 having a MOS transistor configuration and outputs the received information.

入力端子１は保護回路３がないと、念とえばソースホロ
ワの差動増幅回路のように、ＭＯＳトランジスタ構成の
増幅回路（ＭＯＳ−ＩＣ）２のゲートに直接導かれるた
め静電気に対して非常に弱く取扱い上問題となる。Without the protection circuit 3, the input terminal 1 would be led directly to the gate of the MOS transistor-configured amplifier circuit (MOS-IC) 2, such as in a source follower differential amplifier circuit, and would be extremely vulnerable to static electricity. This poses a problem in handling.

これらの対策として従来一般には第２図に例示するよう
に入力端子１に保護抵抗＠５１とダイオード（Ｄｎ、　
Ｄｐ　）　３２を組み合せた保護回路を挿入して静電耐
圧を向上している。しかしながら十分な効果を生じさせ
るには大きな抵抗値または面積が必要となり、このため
に寄生的に存在する容量やリーク電流が増加する。この
ような寄生的な素子の発生は入力端子１のインピーダン
スを低下させて本来の回路機能を損う。Conventionally, as a countermeasure against these problems, a protective resistor @51 and a diode (Dn,
A protection circuit combining Dp) 32 is inserted to improve electrostatic withstand voltage. However, a large resistance value or area is required to produce a sufficient effect, which increases parasitic capacitance and leakage current. The occurrence of such parasitic elements lowers the impedance of the input terminal 1 and impairs the original circuit function.

このため本発明によれば第１図（〜に示すように微小な
面積で高い抵抗を得るＭ　ＯＳスイッチ４を入力端子１
に直列に挿入し、電源が投入されない時には開放状態と
なるようにして、入力端子１から内部回路（増幅回路２
）を電気的に分離させて静電気に対し保護することがで
きる。Therefore, according to the present invention, as shown in FIG.
Connect the internal circuit (amplifier circuit 2) from input terminal 1 to the internal circuit (amplifier circuit 2) by connecting it in series with
) can be electrically isolated to protect against static electricity.

なお、第１図（４）はｎ−ＭＯｓスイッチ４を挿入した
場合で、その等価回路は第１図（Ｂ）のように表現され
るため、等価的なダイオードＤｎとは反対方向ｌども静
電破壊防止が有効にできる−ように従来と同好の保護用
ダイオード５も挿入しである。なお保護用ダイオード５
はｎ−ＭＯＳスイッチ４のオン抵抗が低減できるように
Ｐ−ＭＯＳスイッチを並列に配置しても同様の働きが得
られる。Note that Fig. 1 (4) shows the case where the n-MOS switch 4 is inserted, and its equivalent circuit is expressed as shown in Fig. 1 (B). In order to effectively prevent electric breakdown, a protective diode 5 similar to the conventional one is also inserted. In addition, the protective diode 5
A similar effect can be obtained by arranging P-MOS switches in parallel so that the on-resistance of the n-MOS switch 4 can be reduced.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば入力部に非常に微小な面積
で高抵抗の保護回路を挿入しているため静電耐力の大き
い半導体集積回路が得られる０As described above, according to the present invention, a high-resistance protection circuit is inserted in the input section in a very small area, so a semiconductor integrated circuit with high electrostatic resistance can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１回頭、（Ｂ）は本発明による保護回路を挿入した半
導体集積回路の一実施例を示す回路図と、その咎価回路
図、第２図は従来の保護回路を挿入した半導体集積回路
を例示する回路図である０１・・・入力端子　２・・・
増幅回路　３・・・保護回路４・・・保護用スイッチ（
ＭＯＳスイッチ）５・・・保護用ダイオード 第１ＩＥＩAt the beginning of the first session, (B) is a circuit diagram showing an embodiment of a semiconductor integrated circuit in which a protection circuit according to the present invention is inserted, and its circuit diagram, and FIG. An example circuit diagram is 01...input terminal 2...
Amplifier circuit 3...Protective circuit 4...Protective switch (
MOS switch) 5...Protective diode 1st IEI

Claims (1)

【特許請求の範囲】[Claims] 高入力インピーダンスを有するＭＯＳ集積回路において
、その入力端子と内部回路の間にＭＯＳスイッチを直列
に挿入し、電源未投入時に入力端子と内部回路を電気的
に分離することにより静電破壊耐力を向上させるように
した半導体集積回路。In MOS integrated circuits with high input impedance, MOS switches are inserted in series between the input terminals and internal circuits to electrically isolate the input terminals and internal circuits when the power is not turned on, thereby improving electrostatic breakdown strength. A semiconductor integrated circuit designed to
JP7085985A 1985-04-05 1985-04-05 Semiconductor integrated circuit Pending JPS61230352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7085985A JPS61230352A (en) 1985-04-05 1985-04-05 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7085985A JPS61230352A (en) 1985-04-05 1985-04-05 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS61230352A true JPS61230352A (en) 1986-10-14

Family

ID=13443706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7085985A Pending JPS61230352A (en) 1985-04-05 1985-04-05 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS61230352A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8702576A (en) * 1987-07-23 1989-02-16 Mitsubishi Electric Corp INPUT PROTECTION DEVICE OF A SEMICONDUCTOR CHAIN DEVICE.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8702576A (en) * 1987-07-23 1989-02-16 Mitsubishi Electric Corp INPUT PROTECTION DEVICE OF A SEMICONDUCTOR CHAIN DEVICE.

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