JPS61228710A - Current source circuit - Google Patents

Current source circuit

Info

Publication number
JPS61228710A
JPS61228710A JP7022985A JP7022985A JPS61228710A JP S61228710 A JPS61228710 A JP S61228710A JP 7022985 A JP7022985 A JP 7022985A JP 7022985 A JP7022985 A JP 7022985A JP S61228710 A JPS61228710 A JP S61228710A
Authority
JP
Japan
Prior art keywords
transistor
current
base
emitter
whose
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7022985A
Other languages
Japanese (ja)
Inventor
Toshiyuki Eto
江藤 俊之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7022985A priority Critical patent/JPS61228710A/en
Publication of JPS61228710A publication Critical patent/JPS61228710A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a current source circuit without flowing a waste current even at output open with simple circuit constitution by connecting respectively the 1st - 5th transistors (TR) by a specific method. CONSTITUTION:A TR 1 and an input current source 2 are connected in series between a power supply V<+>1 and common, bases of TRs 3, 5 are connected in common, an emitter of a TR 6 is led to an output current terminal 7 and a base of the TR 4 is connected to an input current source 2. In the circuit formed above, each base current of the TRs 1, 6 is equal by the mirror circuit comprising the TRs 3, 5. Thus, the output current is equal to the input current. When the output is opened, that is, the emitter of the TR 6 is opened, the base current of the TR 5 is very small while taking the emitter current of the TR 3 into account. Thus, the current increase through a power supply V<+>2 is negligible.

Description

【発明の詳細な説明】 〔與業上の利用分野〕 5本発明は集積回路に適し九電流源回路に関する。[Detailed description of the invention] [Field of industrial use] 5 The present invention relates to a current source circuit suitable for integrated circuits.

〔従来の技術〕[Conventional technology]

電流源回路は種々提案されているが、その中で第2図に
示すようなカレントミラー回路は、ベース電流IBが補
償された回路として従来知られている。その構成はトラ
ンジスタ9と入力信号源8とが電源v3と接地間に直列
に接続され、一方出力端子12と接地間にはトランジス
タ11が接続され、トランジスタ9とトランジスタ11
0ベース同壱は共通に接続され、そこにトランジスタ1
゜のエミッタが接続される。トランジスタ1oはTB補
償用として用いられるもので、ベースに入力信号をうけ
、コレクタは電源■4+に接続されている。
Various current source circuits have been proposed, and among them, a current mirror circuit as shown in FIG. 2 is conventionally known as a circuit in which the base current IB is compensated. Its configuration is such that a transistor 9 and an input signal source 8 are connected in series between a power supply v3 and the ground, while a transistor 11 is connected between an output terminal 12 and the ground, and a transistor 9 and a transistor 11 are connected in series between the output terminal 12 and the ground.
0 base and 1 are connected in common, and transistor 1 is connected there.
The emitter of ゜ is connected. The transistor 1o is used for TB compensation, and receives an input signal at its base, and its collector is connected to the power supply 4+.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、かかる電流源回路では出力をオープンに
すると、出カドランジスタロが飽和する為、ベース電流
が大幅に増加する。今、トランジスタ11の順方向電流
増幅率をβF、逆方向′It流増幅率をβR1入力電流
をIlnとすると、トランジスター1のコレクタがオー
プンにされたときのベース電流は−「〒フ1X I I
nとなる(ここで、βF;閃とする)。
However, in such a current source circuit, when the output is opened, the output transistor becomes saturated, and the base current increases significantly. Now, assuming that the forward current amplification factor of the transistor 11 is βF, the reverse direction 'It current amplification factor is βR1, and the input current is Iln, the base current when the collector of the transistor 1 is opened is - "〒F1X I I
n (here, βF is assumed to be flash).

βBは通常1〜2程度の低い値である。いま、βR+=
=1とすれば211mとなり、この電流は当然電源から
供給されることになる。従って、出力オープンの状態を
もつ装置に於いては低電流化が著しく妨げられることに
なる。
βB is usually a low value of about 1 to 2. Now βR+=
If =1, the current will be 211 m, and this current will naturally be supplied from the power supply. Therefore, in a device with an open output state, lowering the current is significantly hindered.

〔問題点を解決するための手段〕[Means for solving problems]

本発明によれば、エミッタが電流入力端子に導出されか
つコレクタが接地された第1のトランジスタと、エミッ
タが接地されコレクタが第1のトランジスタのベースに
接続された、第1のトランジスタと異極性の第2のトラ
ンジスタと、第2のトランジスタと同極性でかつベース
どうし接続すれ、エミッタが接地された第3のトランジ
スタと、ベースが前記電流入力端子に接続され二でツク
が第3のトランジスタのベースに接続された、第3(D
 トラy ’)スタと同極性の第4のトランジスタと、
第3のトランジスタと異極性でコレクタが接地さレカつ
ベースが第3のトランジスタのコレクタと接続され、エ
ミッタが電流出力端子に導出された第5のトランジスタ
からなることを特徴とする電流源回路が得られる。
According to the present invention, a first transistor whose emitter is led out to a current input terminal and whose collector is grounded, and a first transistor whose emitter is grounded and whose collector is connected to the base of the first transistor and which have different polarities. a third transistor having the same polarity as the second transistor and whose bases are connected to each other and whose emitters are grounded; and a third transistor whose base is connected to the current input terminal and whose bases are connected to each other and whose emitters are grounded. The third (D
a fourth transistor having the same polarity as the try') star;
A current source circuit comprising a fifth transistor having a polarity different from that of the third transistor, whose collector is grounded, whose base is connected to the collector of the third transistor, and whose emitter is led out to a current output terminal. can get.

〔実施例〕〔Example〕

次に本発明をその実施例に従い、図面を用いて詳細に説
明する。
Next, the present invention will be explained in detail according to an embodiment thereof using the drawings.

第1図は本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of the present invention.

即ちトランジスタlと入力電流源2が電源Vl  と接
地間に直列に接続され、トランジスタ3とトランジスタ
5の各ベースは共通接続され、トランジスタ6のエミッ
タが出力電流端子7に導出され、トランジスタ40ベー
スが入力電流源2に接続される。
That is, the transistor 1 and the input current source 2 are connected in series between the power supply Vl and the ground, the bases of the transistor 3 and the transistor 5 are connected in common, the emitter of the transistor 6 is led out to the output current terminal 7, and the base of the transistor 40 is connected in series. Connected to input current source 2.

かかる構成に於いてトランジスタ3と5からなるミラー
回路により、トランジスタ1と6の各ベース電流は等し
くなる。従って、出力電流は入力電流と等しくなる。こ
こで出力がオープン、即ちトランジスタ6のエミッタが
オープンとなった場合、トランジスタ50ベース電流は
トランジスタ3のエミッタ電流を考慮すれば極めて微少
である。
In this configuration, the base currents of transistors 1 and 6 become equal due to the mirror circuit made up of transistors 3 and 5. Therefore, the output current will be equal to the input current. Here, when the output is open, that is, when the emitter of the transistor 6 is open, the base current of the transistor 50 is extremely small considering the emitter current of the transistor 3.

従って、電源v2+を通しての電流増加は無視しうる。Therefore, the current increase through the power supply v2+ is negligible.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、簡単な回路構成で出力
オー17時にも無駄な電流を流すことのない電流源回路
を得ることが出来る。
As described above, the present invention can provide a current source circuit with a simple circuit configuration that does not cause unnecessary current to flow even when the output is OFF.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す回路図、第2図は従来
のカレントミラー回路の回路図である。 1.3,4,5,6,9,10.11・・・・・・トラ
ンジスタ、2.8・・・・・・入力電流源。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional current mirror circuit. 1.3, 4, 5, 6, 9, 10.11...transistor, 2.8...input current source.

Claims (1)

【特許請求の範囲】[Claims] エミッタに入力信号をうけ、コレクタが接地された第1
極性の第1のトランジスタと、エミッタが接地され、コ
レクタが前記第1のトランジスタのベースに接続された
第2極性の第2のトランジスタと、該第2のトランジス
タと同極性でかつベースどうし接続され、エミッタが接
地された第3のトランジスタと、ベースに前記入力信号
をうけ、エミッタが前記第3のトランジスタのベースに
接続された第2極性の第4のトランジスタと、前記第1
のトランジスタと同極性で、コレクタが接地され、ベー
スが前記第3のトランジスタのコレクタと接続され、エ
ミッタが電流出力端子に導出された第5のトランジスタ
とを含むことを特徴とする電流源回路。
The first one has an emitter that receives an input signal and a collector that is grounded.
a first transistor with a polarity, a second transistor with a second polarity whose emitter is grounded and whose collector is connected to the base of the first transistor; and a second transistor with the same polarity as the second transistor and whose bases are connected to each other. , a third transistor whose emitter is grounded, a fourth transistor of a second polarity whose base receives the input signal and whose emitter is connected to the base of the third transistor;
A current source circuit comprising: a fifth transistor having the same polarity as the transistor, having a collector grounded, a base connected to the collector of the third transistor, and an emitter led out to a current output terminal.
JP7022985A 1985-04-03 1985-04-03 Current source circuit Pending JPS61228710A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7022985A JPS61228710A (en) 1985-04-03 1985-04-03 Current source circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7022985A JPS61228710A (en) 1985-04-03 1985-04-03 Current source circuit

Publications (1)

Publication Number Publication Date
JPS61228710A true JPS61228710A (en) 1986-10-11

Family

ID=13425520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7022985A Pending JPS61228710A (en) 1985-04-03 1985-04-03 Current source circuit

Country Status (1)

Country Link
JP (1) JPS61228710A (en)

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