JPS61224681A - Control circuit for picture memory device - Google Patents

Abstract

PURPOSE:To share an S/P and P/S converter and a D/A converter with a memory control circuit by equalizing the data composition which each memory handles and setting of the address in each memory. CONSTITUTION:A clock generator 22 outputs an address clock to an address counter 23, which counts said clock and constituted of 16 bits. Its value is used as address data common to an RAM 2 and an ROM 8. Since the address in the ROM 8 is set to the same value in the RAM 2, the position where information read out of the ROM 8 is projected on a screen is equal to the projecting position of a video signal read out of the same address in the RAM 2. In this case one memory control circuit 21 suffices. If a read/write control circuit 25 controls alternatively and selectively the read action of each memory, the S/P and P/S converter 3 and the D/A converter 4 can be commonly used, whereby one unit each suffices.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a control circuit for an image storage device including a plurality of semiconductor storage elements having different configurations.

[Technical background of the invention and its problems]

Conventionally, in order to control an image storage device equipped with a plurality of semiconductor storage elements (hereinafter referred to as memories) having different configurations, each memory requires a memory control circuit for setting addresses, operation settings, etc. In addition, if the speed of the signal written to and read from memory is faster than the memory cycle time, it is necessary to convert the signal to a parallel signal, write it, read it, and then convert it back to a serial signal. An S/P-P/8 converter (serial to parallel converter) was required for each memory.

For example, such an image storage device may be combined with a home video tape recorder (hereinafter referred to as VTR), and the playback signal may be stored in a random access memory (configured as shown in FIG. 4).
One field is written in the RAM (RAM), read continuously from there and supplied to the television receiver, and is also read-only memory (i(OM)-) as shown in FIG.
i Prepare, read other images, text, etc. information from there,
When trying to display images in addition to a television receiver,
It was necessary to have a circuit configuration as shown in FIG.

That is, when converting a color video signal as a composite video signal into a digital signal, the sampling frequency of the A/D converter 1 is usually selected to be an integral multiple of the color subcarrier frequency fsc, for example, 3 times 3 fsc. selected. Therefore, the sampling period is 93 ns. On the other hand, the normal Afld2 has a cycle time of about 220 ns, and cannot write to or read from the RAM 1 as it is. Therefore, S/P, P/S converter 3
For example, three pieces of data are converted into parallel signals and written with a data period of 280 nS. If the number of bits of one data of a digital video signal is 8, 8×3=24 bits of data will be written at one time.
Six M2s with a capacity of 64KX4 are required. Furthermore, when reading, the 8/P-P/S converter 3 converts the data into a serial signal, and the D/A converter 4 converts it into an analog signal.

Such a Φ converter 1.几AM2. S/P・P/S
Converter 3. A memory control circuit 5 is provided to control the operation of the D/A converter 4. That is, a 5 fsc signal obtained by multiplying the color subcarrier signal by 6, for example, by a multiplier circuit 6 is applied to the memory control circuit 5 as a master clock, and based on this signal, the A/D converters 1 . In addition to the 3 fsc sample clock for the D/A converter 4, the row address strobe signal (1 (, As ), column address strobe signal (CA
S) is output. Further, the memory system # circuit 5 has an address counter that counts an address clock having a frequency of fsc generated by the master clock. It is something that can be done.

On the other hand, other information signals are written in a RIOM consisting of 6 pieces with a capacity of 32Kx8, and the data is 1
The 8 data pits are converted into parallel signals of 3 data each. Therefore, the read signal is converted into serial data by the P/8 converter 9 to become a 3 fsc signal, which is then converted to an analog signal by the P D/A converter 10.

This Le OMs, P/8 converter9. The operation of the D/A converter 10 is also controlled by a memory control circuit 11 provided separately.The memory control circuit 11 receives a master clock from the multiplier circuit 6, and controls the operation of the P/A converter 9. It outputs a clock for the D/A converter 10 and also outputs a read signal (O
E) and a chip selection signal (c) that selects the ROMg chip.
g) Output (1). Further, the memory control circuit 11
It has an address counter and outputs address data of the ROM8.

The signals read from each memory and converted into analog signals are guided to terminals a and b of the switch 12, and the switch 1
2, one of them is selected and supplied to a television receiver (not shown).

As described above, in order to control the image storage device equipped with the RAM 2 and OMa, the memory control circuits 5 and 11 must be
and S/P, P/S converter 3. Since the P/8 converter 9 is required, the circuit configuration is undesirably complicated.

[Purpose of the invention]

The present invention has been made in view of the above points, and provides a control circuit for an image storage device that has a simplified circuit configuration by allowing each memory to share the memory control circuit and the 8/P and P/S converters. [Summary of the Invention] The present invention provides a method for controlling two memories with different configurations, so that address settings can be made common to each memory. The above purpose is achieved by matching the setting method to that of the other memory, making the structure of data handled in each memory the same, and making it possible to handle it in the memory with the longer data access time. .

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit configuration diagram of one embodiment of the present invention, and the fifth
Similar to the figure, this figure shows an example in which the present invention is combined with a VTR.

In FIG. 1, the same parts as in FIG. 5 are given the same reference numerals.

In the embodiment shown in FIG. 1, the address settings of the RAM 2 are matched with the address settings of the OMs.

0 The memory control circuit 21 has a clock generator 22 that generates various clocks from the master clock supplied from the multiplier circuit 6. This clock generator 22 outputs an address clock to an address counter 23, and an address counter 23 counts it. The address counter 23 consists of 16 bits, and its value is stored in the RAM 2.
and OM8 are commonly used as address data.

For RAM Z, it is divided into upper 8 bits and lower 8 bits, the lower 8 bits are used for example row addresses, and the upper 8 bits are used for column addresses.

These address data are switched and selected by the address switching circuit 24, and each 8-bit address data is supplied to the RAM 2 in a time-division manner. Further, the lower 15 bits are supplied to the ROM 8 as address data, and the most significant 1 bit is used as a chip selection signal (CG). Further, the memory control circuit 21 is a write/read control circuit 25.
and a control circuit 2 that generates each control signal.
6 and outputs write, read, and address setting signals to each memory 2.8.

Now, when writing a video signal (a reproduced signal or a signal received by a tuner built into the VTR) from a VTR into the RAM 2, it is desirable to associate the address with the operation of the VTR. Therefore, the head switching pulse (H-8W pulse) of VTfL initializes the address of RAM 2. The edge of this head switching pulse is detected by the edge detection circuit 27 because the rising or falling edge of this head switching pulse exists 5 to 7 horizontal scanning periods before the vertical synchronizing signal of the video signal obtained from the VTR. −
If the address counter 23 is cleared at that timing, the address of AM2 and the VTR (7) video signal will be associated with each other. Also, when reading from the RAM 2, the address is initialized using a head switching pulse.

Since the address of the video signal OM8 is also set to the same value as the AM2, the position where the information read therefrom is displayed on the screen matches the position where the video signal read out from the RAM 2 at the same address is displayed.

In addition, at this time, if the information written in RC) Mg is a video signal, the vertical synchronization signal is located at the address of the same 1st shift as the address where the vertical synchronization signal is located. The video signal from the IcVT is stored in RAM2.
If the data is written in the memory 2.8, vertical wobble or skew distortion on the screen will not occur when the video signals read from each memory 2.8 are switched.

Therefore, as a signal for clearing the address counter 23, it is also possible to use the vertical synchronization signal of the video signal obtained from the vT processor.

In this embodiment, only one memory control circuit 21 is required, and
The structure of the data handled in each memory is converted into serial data, which consists of 8 bits per data, and the speed is 3fs.
c. Therefore, if the readout control circuit 25 selectively controls the readout operation of each memory, the S/P
- The P/S converter 3 and the 1)/AK converter 4 can be used in common, and only one of each is required.

FIG. 2 shows another embodiment of the invention, in which the same parts as in FIG. 1 are given the same reference numerals.

In this embodiment, a 0M31 is used which incorporates a row address and column address switching circuit.
Since the address of OM31 is set by a row address and a column address, the address data is 8 bits, and the number of addresses can be reduced.

FIG. 3 shows still another embodiment of the present invention, in which character information written in the ROM is read out while reading out the video signal written in the AM2, and white is added to the video signal. It is inserted.

That is, the AND gate 41 is opened by a white character insertion control signal given from the outside, and the switch 43 is switched to the terminal side by character information read from the ROM 42, and the video signal is fixed at a predetermined DC level while the character information is present. It is something to do.

In this case, if the access methods for R, AM2 and ROM 42 are different, an address conversion circuit 44 is required as shown in the figure. In this case, as in the embodiment of Fig. 1.2,
Since the address is set in the same way as 几AM2, no vertical wobble or skew occurs when displaying character information. Furthermore, R Ori 42 only needs to be one bit.

As described above, by storing character information in +(, OM), it is possible to display the operating status of the VTR on the screen.

In other words, when the VTRJ is in an operating state in which no video signal is displayed on the screen, such as when the VTRJ is loading a tape, fast forwarding, or reversing, etc., it displays text on the screen to indicate that it is in operation. is possible.

Also, the information stored in the ROMIC$ includes information indicating the operating status of the VTR, as well as how to operate the V7rR.

Possible examples include instructions on how to set a timer, and still images such as title images.

〔Effect of the invention〕

As described above, according to the present invention, since the configuration of data handled in each memory and the address setting of each memory are made the same, the memory control circuit and the S/P/P/S converter, D
/A converters can be used in common, and the circuit configuration is simplified.

Furthermore, by applying this invention to a VTR, effective images can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. 2 and 3 are circuit block diagrams showing other embodiments of the present invention, FIGS. 4 and 5 are circuit block diagrams showing the memory structure, and FIG. 6 is a conventional circuit block diagram. It is. 21...Memory control circuit agent Patent attorney Nori Chika Kensuke (and 1 other person) (transferred) Half-S diagram

Claims (3)

[Claims] (1) A first semiconductor memory element in which a video signal can be written and read, a second read-only semiconductor memory element in which information signals are written in advance, and an address of the first and second semiconductor memory element. A control circuit for an image storage device, comprising: address setting means for commonly setting , and means for reading out signals from the first and second semiconductor storage elements and selectively switching and deriving the signals. . (2) The information signal written in advance in the second semiconductor memory element is used as a video signal, and the address value corresponding to the position of the vertical synchronization signal and the vertical direction of the video signal written in the first semiconductor memory element 2. A control circuit for an image storage device according to claim 1, wherein the address values corresponding to the positions of the synchronization signals are the same. (3) The video signal written to the first semiconductor memory element is a signal obtained from a video tape recorder, and the address of the first semiconductor memory element and the address of the second semiconductor element are set to the video tape recorder. 2. A control circuit for an image storage device according to claim 1, wherein the control circuit is set based on a head switching pulse of .