JPH04241592A - Color image signal reproducing device - Google Patents

Abstract

PURPOSE:To output image signals by one channel and to make the device compact and inexpensive by serially rearranging a digital color image data corresponding to picture elements on a screen before D/A conversion. CONSTITUTION:Before the output of a field memory 4A is converted to analog signals by a D/A converter 7A, the read-out digital color image data is serially rearranged corresponding to the picture elements on the screen. Then, the analog signals are applies to sample-and-hold pulse circuits 17-19 and sampled and held by sample-and-hold pulses SH1-SH3 applied from a timing generator 14A. The analog image signals in R, G and B outputted from these circuits 17-19 are turned to a luminance signal Y and color difference signals R-Y and B-Y through a matrix circuit 10, and a chrominance signal C is generated by an encoder 11. An adder 12 adds the signals C and Y to a cycle signal outputted from the generator 14, and a standardized image signal is prepared.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color image signal reproducing apparatus applied to a digital still camera system using, for example, an IC memory card as a storage medium.

0002

2. Description of the Related Art In the digital chill camera system as described above, information compression technology is used to efficiently store digital image data in a storage medium. This information compression technology includes an adaptive DPCM encoding method (
For example, Japanese Patent Application No. 2-163127) is known. When such an information compression method that utilizes the correlation between adjacent pixels is used, the correlation is stronger and the encoding efficiency is higher when the entire screen data of the same color is encoded individually. Therefore, for example, R (or Y) full-screen data is first encoded, and then processed as G (or R-Y) full-screen data and B (or B-Y) full-screen data. At this time,
A storage medium such as an IC memory card stores R(Y) full-screen compressed data and G(R
-Y) Full-screen compressed data B (B-Y) Full-screen compressed data is stored in the order.

[0003] Compressed and stored image data is read out from a storage medium and decoded. The data read from this storage medium and decoded is stored in a buffer memory such as field memory (memory whose memory address is automatically incremented by clock input) or random access memory (RAM), and /A conversion and processed into an analog video signal. By the way, in a color component image signal, 3 signals such as R, G, B or a luminance signal and a color difference signal (Y, R-Y, B-Y) are used.
Since the data of the channels must be processed simultaneously, three channels of buffer memory and D/A converters are normally required.

FIGS. 10 and 11 are block diagrams of conventionally known image reproducing devices for displaying images. These conventional examples will be explained below.

First, FIG. 10 shows a block diagram when R, G, and B image data are employed. The compressed data read from the IC memory card (1) storing the above-mentioned image data is information expanded (decoded) by the decoder (2) and input to the changeover switch (3). The switch (3) is a switch for distributing R, G, and B decoded data to field memories (4), (5), and (6) corresponding to R, G, and B, respectively, and each field memory has R, G, and B image data are written in order. Next, each color data is simultaneously read out from each field memory, and a D/A converter (7) corresponding to each color is connected.
It is converted into an analog signal by (8) and (9). These analog R, G, B signals are converted into Y, R-Y, B-Y by a matrix circuit (10), and the R-Y, B-Y color difference signals are further converted into chromaticity signals by an NTSC encoder (11). It is considered to be C. The Y, C and synchronization signals from the timing generator (14) are added by an adder (12) to form an NTSC signal. In addition, IC memory card (1)
is controlled by a memory card controller (16), and each field memory is controlled by a field memory controller (15). Also timing generator (14
) controls all the timing of each processing block, and these are further controlled by the system control microcomputer CP.
It is controlled by U(13).

FIG. 11 shows a block diagram when image data of Y, RY, and BY signals are employed. In this case, field memories (4), (5), and (6) for Y, R-Y, and B-Y are used instead of R, G, and B, and three D/A converters are used as in FIG. (7), (8), (9
) is converted to an analog signal. Furthermore, since the signal is already processed as a color difference signal, no matrix circuit is required. The other parts are the same as those in FIG. 10, so explanations will be omitted.

[0007]

However, according to the above-mentioned prior art, three channels of paths are required to obtain an analog color image signal, which is an obstacle to miniaturization and cost reduction of equipment.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a color image signal reproducing apparatus which outputs an analog image signal in one channel, and which can reduce the size and cost of the apparatus.

[0009]

[Means for Solving the Problems] A color image signal reproducing apparatus according to the present invention includes a reading means for reading color compressed image data from a storage medium storing color compressed image data for at least one screen; a decoding means for decoding the compressed color image data into digital color image data; and a rearranging means for serially rearranging the digital color image data decoded by the decoding means in correspondence with pixels on the screen. It is characterized by having the following. The digital color image data rearranged by the rearrangement means is converted into an analog image signal by the D/A conversion means of the color image signal reproducing device according to the present invention, and the analog image signal is converted into a digital color image signal corresponding to a pixel. A standardized image signal is obtained from the sampled and held signals.

0010

[Operation] Since the color image signal reproducing device according to the present invention is constructed as described above, the output of the rearranging means is such that each color image data is output in series in correspondence with the pixels on the screen. D/A conversion for one channel
This can be done by the conversion means, and it is also possible to use only one field memory for rearranging.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a color image signal reproducing apparatus according to the present invention will be described with reference to the accompanying drawings FIGS. 1 to 9. Hereinafter, the same reference numerals are given to the components in FIGS. 10 and 11. FIG. 1 is a block diagram of a color image signal reproducing apparatus according to an embodiment of the present invention. This embodiment shows a case where three primary color data of R, G, and B are employed as image data. One field memory 4A is provided downstream of the decoder 2, and a field memory controller 15A controls writing of image data to this field memory 4A as shown in FIG. Field memory controller 15A
The CPU 13 sends a reset write signal RSTW that initializes the write address pointer of the field memory.
receive from When this reset write signal RSTW is set to H level, the write address is initialized to address 0. The field memory controller 15A provides a write enable signal WE to the field memory 4A, and when this signal is at H level, the field memory 4A is enabled for writing. The field memory controller 15A is a timing generator (TIMINGGEN).
) Serial write clock SWC given from 14A
Write enable signal WE is enabled in synchronization with K (
(H level), the write address is incremented. Furthermore, the field memory controller 15A provides the field memory 4A with an input enable signal IE that enables data to be taken in, and this signal becomes H.
Control is performed so that data is written to the given address when the level is set.

Compressed image data stored in the memory card is read out by the memory card controller 15A. This compressed image data is supplied to the decoder 2, decoded and expanded, and converted into R, G, and B digital image data, and sent to the field memory 4A. At this time, since the image data stored in the memory card 1 is continuous for every full screen of the same color, the output of the decoder 2 is the image data for the full screen of R (R, R, R ,...), then the image data for the entire screen of G (G, G, G...), and then the image data for the entire screen of B (B, B, B...). Therefore, the CPU
13 first sets the reset write signal RSTW to H level at a timing before the R image data is output from the decoder 2, and initializes the write address pointer of the field memory 4A to 0. At the timing when this reset write signal RSTW is set to H level, the write enable signal WE is raised and the serial write clock SWCK is raised.
The write address pointer is incremented in synchronization with the write address, and the write address is incremented as 0, 1, 2, 3, and so on. When such an increment is performed, the field memory controller 15A sets the input enable signal IE to a write address of 0, 3, 6, 9, . . .
It is enabled (H level) at the timing of skipping two addresses. Then, the above 0, 3 is stored in the field memory 4A at the next rising edge of the serial write clock SWCK when the input enable signal IE is set to H level.
, 6, 9, . . . R image data is written to the addresses of , 6, 9, . Note that the decoder 2 uses the timing clock given from the timing generator 14A to perform (R, R,
Each R (G, B) of R…, G, G, G…, B, B, B…)
1 data is output in such a way that it is switched every time the input enable signal IE rises. In this way, R
When the image data for the entire screen is written to the field memory 4A, the CPU 13 sends a reset write signal RSTW.
is set to H level again, the write address pointer is initialized to 0, and the writing of G image data begins. When the reset write signal RSTW is set to H level, the write enable signal WE is set to H level again and is output, and the write address is set to 0, 0, 0 in synchronization with the serial write clock SWCK.
It is incremented as 1, 2, 3, etc. When such an increment is performed, the field memory controller 15A enables the input enable signal IE at the timing when the write address is 1, 4, 7, 10, . . . in two-address jumps. Then, G image data is written into the field memory 4A at the addresses 1, 4, 7, 10, . . . at the next rising edge of the serial write clock SWCK after input enable signal IE is set to H level. When the image data for the entire screen of G is written into the field memory 4A, the CPU 13 sets the reset write signal RSTW to H level again, initializes the write address pointer to 0, and proceeds to write the B image data. When the reset write signal RSTW is set to H level, the write enable signal WE is set to H level again and is output, and the write address is incremented as 0, 1, 2, 3, etc. in synchronization with the serial write clock SWCK. . When such an increment is performed, the field memory controller 15A outputs the input enable signal IE when the write address is 2, 5, 8, etc.
11, . . . is enabled at two address intervals. Then, the above 2, 5, 8, 11 are stored in the field memory 14A at the next rising edge of the serial write clock SWCK after the input enable signal IE is set to H level.
, . . . image data of B is written to the addresses of , . . . . Through the above operations, RGB image data is serially stored in the field memory 14A corresponding to the pixels on the screen.
This means that B... is written.

In this embodiment, the output of the field memory 4A is converted into an analog signal by one D/A converter 7A (FIG. 1). The field memory controller 15A uses addresses 0, 1, 2, 3, . . . to read image data.
By sequentially applying R to the field memory 4A,
Image data is read out in the order of GBRGB... The read image signal converted into an analog signal by the D/A converter 7A is given to three S/H circuits 17, 18, and 19. S/
Timing generator 1 in H circuits 17, 18, and 19
Sample & hold pulse SH1 given from 4A,
Signal sampling and holding is performed by SH2 and SH3. FIG. 3 shows the detailed configuration of the S/H circuits 17, 18, and 19. The input signal is sent from the input terminal IN to the buffer circuit 17.
C, and is output from the output terminal OUT via the analog switch 17a, which is opened and closed by the sample and hold pulse SH. FIG. 4 shows a sample-and-hold timing chart. D/ACLOCK is an input clock of the D/A converter 7A. At the timing of the rise of this D/ACLOCK pulse, the image data is converted into analog and an image signal is output. Sample & Hold Palace SH
1 is generated to sample and hold the 0th, 3rd, 6th,...th signal in the output signal of the D/A converter 7A, and the sample & hold pulse SH2 is generated to sample and hold the 0th, 3rd, 6th, ...th signal in the output signal of the D/A converter 7A. The sample and hold pulse S is generated to sample and hold the 1st, 4th, 7th,...th signal.
H3 is 2, 5, 8,... in the output signal of the D/A converter 7A.
It is generated to sample and hold the second signal. As a result, the output signal of the D/A converter 7A is RGBRG.
Since the signals are output in the order of B..., the S/H circuit 17 has R.
The image signal of is sampled and held, and the S/H circuit 18
Then, the G image signal is sampled and held, and the B image signal is sampled and held in the S/H circuit 19. Below, R output from the S/H circuits 17, 18, 19,
G and B analog image signals are converted into a luminance signal Y and color difference signals R-Y, B-Y via a matrix circuit 10, a color signal C is created by an encoder 11, and a color signal C and a brightness signal are created by an adder 12. Y and timing generator 14
The synchronization signal output from the NTSC signal is added to the NTSC signal.

FIG. 5 shows a color image signal reproducing apparatus corresponding to the case where the memory card 1 stores an image signal obtained by compressing information of a luminance signal Y and color difference signals R-Y, B-Y. There is.

In FIG. 5, the decoder output signals include a Y full-screen signal, followed by an R-Y full-screen signal, and a Y full-screen signal.
B-Y full screen signal is output (YYYYYYY...R-
YR-YR-Y...B-YB-YB-Y...). by the way,
Regarding the luminance signal Y and the color difference signal, the band of the color difference signal is usually less than 1/2 of the band of the Y signal, so the digital image data is also 1/2 of the Y signal for both R-Y and B-Y signal data. Generally, the amount of data is 2. Therefore, in the field memory 4B, Y:RY:B-Y
are stored in a data amount of 2:1:1. Therefore, the field memory controller 15B writes data into the field memory 4B as shown in FIG.

That is, the CPU 13 and the field memory controller 15B output a reset write signal RSTW, a write enable signal WE, and a serial write clock SWCK.
is controlled in the same way as the embodiment shown in FIG. When enabled, the image data of the luminance signal Y is written to addresses 0, 2, 4, 6, . . . of the field memory 4B. next,
When writing the color difference signal R-Y, the input nebule signal is enabled when the write address is 4 addresses at a time, such as 1, 5, 9, 13, etc., and the memory address 1,
5, 9, 13, . . . so that the image data of the color difference signal RY is written. Also, when writing the image data of the color difference signal B-Y, the input enable signal is enabled when the write address jumps 4 addresses such as 3, 7, 11, 15, etc., and the memory address 3, 7, 1
1, 15, . . . The image data of the color difference signal B-Y is written. Thus, consecutive addresses in the field memory 4B include Y, R-Y, Y, B-Y, Y, R-Y.
, Y, . . . The field memory controller 15B sets addresses 0, 1, 2,
3, . . . are sequentially applied to read image data from the field memory 4B as Y, RY, Y, BY, Y, . The read data is converted into analog data by the D/A converter 7B and provided to the S/H circuits 17, 18, and 19.

The S/H circuits 17, 18, and 19 perform sample and hold using sample and hold pulses SH1, SH2, and SH3 given from the timing generator 14B. FIG. 7 shows a sample-and-hold timing chart. D/ACLOCK is the same as shown in FIG. Sample & hold pulse SH
1 is 0, 2, 4, 6, in the output signal of the D/A converter 7B.
The sample and hold pulse SH2 is generated to sample and hold the ...th signal, and the sample and hold pulse SH2 is sent to the D/A converter 7B.
The sample & hold pulse SH3 is generated so as to sample and hold the 1st, 5th, 9th, 13th,...th signal among the output signals of the D/A converter 7B.
, 7th, 11th, 15th, . . . are generated so as to sample and hold the signals. As a result, the output signals of the D/A converter 7B are output as Y, R-Y, Y, B-Y, Y, ..., so the S/H circuit 17 receives the Y image signal as a sample. & held, the S/H circuit 18 samples and holds the R-Y image signal, and the SD/H circuit 19
The B-Y image signal is sampled and held. The following processing is similar to that of the device in Figure 11, and finally the NT
The SC signal is reproduced and output.

FIG. 8 shows a color image signal reproducing apparatus using an RGB image signal system in which a RAM is used as the field memory. In this embodiment, RGB image data read from the memory card and decoded by the decoder 2 is stored in the R data RAM 20, the G data RAM 21, and the B data RAM 22. Here, each RAM has R,
The RAM controller 23 controls writing of image data corresponding to G and B. This RAM controller 23 controls chip enable CE and addresses as follows. That is, the output of the decoder 2 first arrives as R full-screen data, then G full-screen image data, and finally B full-screen image data. Therefore, when image data for the entire R screen is being output, the chip enable signal C is sent only to the R data RAM 20.
Give EI as enable and increment the address from 0 to the total number of pixels on the screen. Next, the chip enable signal CE2 is applied as enable only to the RAM 21 for G data, and the address is incremented from 0 to the number of pixels of the entire screen. Furthermore, next, RAM22 for B data
The same control as above is performed for each RAM 20 to 22.
The corresponding image data will be written.

On the other hand, when reading image data, the RAM controller 23 controls the address and chip enable signal CE as shown in FIG. That is, one address is generated, and during this period the chip enable signal CE is
1, CE2, and CE3 are selectively enabled in sequence to perform reading. As a result, the D/A converter 7C has RG
Image data is given in the order of BRGB... This D/A
The operation after analogization by the converter 7C is the same as that in the embodiment shown in FIG. 1, so its explanation will be omitted. In the embodiment shown in FIG. 8, the image data includes a luminance signal Y and a color difference signal RY.
, B-Y can also be used to configure a color image signal reproducing device.

[0020] In the above, an example has been described in which compressed color image data is decoded by the decoding means, but the present invention is not limited to this, and uncompressed data may be used.

[0021] In this embodiment, the reproduced signal is NTSC.
Although the television signal system is used, the present invention can also be applied to other systems such as the RAL television signal system or when obtaining a reproduction signal from a special color video printer.

[0022]

As described above in detail, according to the present invention, the digital color image data is serially rearranged in correspondence with the pixels on the screen by the rearranging means before D/A conversion, so that one channel This can be achieved by using a D/A converter, which has the effect of making the equipment smaller and cheaper.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of an embodiment of the present invention.

FIG. 3 is a configuration diagram of main parts of the present invention.

FIG. 4 is a timing chart of sample and hold.

FIG. 5 is a configuration diagram of a color image signal reproducing device according to another embodiment of the present invention.

FIG. 6 is a timing chart showing the operation of the embodiment shown in FIG. 5 of the present invention.

FIG. 7 is a timing chart of sample and hold according to the embodiment of FIG. 5;

FIG. 8 is a configuration diagram of a color image signal reproducing device according to another embodiment of the present invention.

FIG. 9 is a timing chart for reading image data according to the embodiment of FIG. 8;

FIG. 10 is a configuration diagram of a conventional color image signal reproducing device.

FIG. 11 is a configuration diagram of a conventional color image signal reproducing device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1...Memory card, 2...Decoder, 4A, 4B...Field memory, 7A, 7B, 7C...D/A converter, 10...Matrix circuit, 11...Encoder 12...Adder, 13...
CPU, 14, 14A, 14B...Timing generator 15A, 15B...Field memory controller, 1
6...Memory card controller, 17, 18, 19...S
/H circuit, 20, 21, 22...RAM, 23...RAM controller

Claims (4)

[Claims] 1. Reading means for reading out color image data from a storage medium in which at least one screen worth of color image data is stored, and digital color image data read out by the reading means being serially arranged corresponding to pixels on the screen. A rearrangement means for rearranging the digital color image data rearranged by the rearrangement means, a D/A conversion means for converting the digital color image data rearranged by the rearrangement means into an analog image signal, and a digital color image signal forming a pixel using the output of the D/A conversion means. A color image signal reproducing device comprising a sample and hold means for a predetermined channel that samples and holds each correspondence, and an image signal creation means for creating a standardized image signal from the output of the sample and hold means. . 2. Reading means for reading out color compressed image data from a storage medium in which at least one screen worth of color compressed image data is stored, and a digital color image by decoding the color compressed image data read by the reading means. a decoding means for converting the digital color image data read out into data; a rearranging means for serially rearranging the digital color image data read out by the reading means in accordance with the pixel correspondence on the screen; D/A conversion means for converting into an image signal; sample and hold means for a predetermined channel for sampling and holding the output of this D/A conversion means for each digital color image signal forming a pixel; and this sample and hold means. 1. A color image signal reproducing device comprising: image signal generating means for generating a standardized image signal from the output of the color image signal reproducing device. 3. The rearranging means includes a field memory and a memory controller that writes digital color image data at predetermined address jumps in the field memory and reads out the digital color image data in address order. Claim 1 or Claim 2
The color image signal reproducing device described above. 4. The rearranging means is characterized by comprising a predetermined number of RAMs and a RAM controller that writes one type of digital color image data to each RAM and sequentially accesses each RAM when reading data. A color image signal reproducing device according to claim 1 or 2.