JPS61224631A - Circuit for preventing external disturbance over signal transmission system - Google Patents

Abstract

PURPOSE:To obtain a stable internal clock signal even if power source noise takes place by providing a gate controlled by an internal clock signal control means, an internal clock signal generating means, a frequency detecting means for an external clock signal and a phase detecting means. CONSTITUTION:The frequency detection circuit 62 detects the frequency of the external clock signal T for synchronization from a power supply synchronization circuit 5 and when a signal T entering the phase detection circuit 63 is within the range of phase error, the circuit 63 detects the phase of the signal T. A control circuit 64 initializes the internal clock signal CLK generated in the internal clock signal generating circuit 65 by using the phase and frequency detected in this way. The control circuit 64 controls the input of the signal T to a gate 61 by using the signal CLK. When the signal T is inputted, the gate 61 is opened only within a permissible error range for the expected time. Even when the gate 61 is closed and the signal T is inputted to the gate 61 due to noise, its input is neglected and the signal CLK is held.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a disturbance prevention circuit for a signal transmission system that performs synchronous communication using a clock signal, and is particularly effective when the external clock signal is easily disturbed by noise. This invention relates to a disturbance prevention circuit for a signal transmission system.

[Conventional technology]

When transmitting and receiving signals, a synchronous communication is sometimes performed using an external clock signal. This specific prior art is disclosed in, for example, Japanese Unexamined Patent Publication No. 148435 of 1982. The synchronous communication system described in Japanese Unexamined Patent Publication No. 148435/1983 will be explained based on FIGS. 5 to 7. In FIG. 5, 1 is a power line as a signal line, 14 is a power source, 15 is a transmitting unit, 16 is a receiving unit, and the transmitting unit 15 connected to the power line 1
And the receiving unit 16 performs communication in synchronization with the power waveform AC generated from the power supply 14 on the power 11. The process of obtaining an external clock signal for synchronization in synchronization with this power supply waveform AC will be explained based on FIG. In FIG. 6, the power supply waveform AC is half-wave rectified, and a square wave H is obtained by performing the half-wave rectification and shaping. The obtained square wave H is differentiated to obtain a differential waveform P, and the obtained differential waveform P is half-wave rectified to obtain an external clock signal T for synchronization. To perform synchronous communication using this external clock signal T, the external clock signal T is input to the reset terminal 18 of the shift register 17 as shown in FIG. Synchronize with waveform AC. The transmission unit 15 modulates the transmission data using the output of the shift register 17 and transmits the modulated data. In addition, the receiving unit 16 also uses the same shift register 17 using the method described above.
Since it is synchronized with C, the transmitting unit 15 and the receiving unit 16
The external clock signals T for power synchronization of the two match, and synchronous communication between the transmitting unit 15 and the receiving unit 16 is performed.

[Problem to be Solved by the Invention 3] As explained above, in a signal system that performs synchronous communication using the conventional external tarlock signal T, an external power supply voltage signal such as the one described above is used to perform synchronization. Since an external clock signal is obtained, the synchronization between the transmitting unit 15 and the receiving unit 16 is completely determined by the power waveform AC, and even if noise etc. enters the power waveform AC or a momentary interruption of the power supply occurs. In some cases, synchronization may be lost and communication may become impossible.

In particular, commercial power supplies have a lot of noise generated by connected loads, and synchronous communication that is 100% dependent on this noise has problems with reliability.

The present invention was made to solve the above problems, and
The purpose is to obtain a stable internal clock signal for synchronization even when noise enters the power waveform or momentary power interruption occurs.

[Means for solving problems]

Therefore, the present invention includes a gate, an internal clock signal generating means, a frequency detecting means for detecting the frequency of an external clock signal, a phase detecting means for detecting the phase of the external clock signal, and an internal clock signal controlling means. , the gate is opened and closed to extract only a reliable external clock signal, and the internal clock signal generating means is controlled by the frequency and position of the extracted external clock signal.

[Effect]

The internal clock signal control means opens a gate based on the internal clock, and sets the frequency of the internal clock signal generated by the internal clock signal generation means based on the frequency and phase of the external clock passed through this gate.

〔Example〕

An embodiment of the present invention will be described below based on the drawings. 1st
The figure is a block diagram showing synchronous communication using signal lines. In Fig. 1, 1 is a signal line such as a power line, 2 is a coupling transformer, 3 is a modem, 4 is a carrier detection circuit, 5 is a power synchronization circuit, 6a and 6b are signal line transport controllers, 7 is a host computer, and 8 is a self-contained Address setting switch, 9
is a destination address setting switch. Here, various control signals QBF are provided between the signal line transport controller 6a and the host computer 7.

ACK, STB, IBF, CMD, PAS, and data signal DATA are input and output, and a signal from the self-address setting switch 8 is manually input to the signal line transport controller 6a. The signal line transport controller 6a further receives the detection signal CD from the carrier detection circuit 4 and the external clock signal T from the power synchronization circuit 5, and inputs and outputs various signals SD, RD, and R3 to the modem 3. There is. The output from this modem 3 is carried on a signal line 1 via a coupling transformer 2. On the other hand, a signal detection line 10 for extracting a power supply voltage signal from the signal line 1 is connected to the power synchronization circuit 5, and a carrier detection line 11 for detecting whether a carrier is on the signal line 1 is connected to the modem of the coupling transformer 2. It is connected to the carrier detection circuit 4 from the side.

In such a configuration, when the signal line controller 6a receives data from the host computer 7, the carrier detection circuit 4 detects the carrier on the signal line 1, and if there is no carrier, the signal line 1 is transmitted via the modem 3 and the coupling transformer 2.
Put the data signal on. This loaded data signal is input to the signal line transport controller 6b configured similarly to the transmitting side, and upon receiving the input data signal, the signal line transport controller 6b transfers the data signal again to the signal line transport on the transmitting side. A data signal is output toward the controller 6a.

The extraction of the synchronization signal necessary for transmitting and receiving this data signal will be explained below with reference to FIGS. 2 and 3.

FIG. 2 shows a part of the internal configuration of the transport controller 6a where the internal clock signal CLK is generated. An external clock signal T for synchronization is input to a gate 61, and the output of this gate 61 is sent to the frequency detection circuit 62. and phase detection circuit 6
3 is entered. The output of this frequency detection circuit 62 and the output of the phase detection circuit 63 are both input to an internal clock signal control circuit 64.
The output is input to an internal clock signal generation circuit 65. The output of this internal clock signal generation circuit 65 is input to a communication control circuit 66, and various signals are input and output from this communication control circuit 66. The signal of the one-way clock signal control circuit 64 is fed back to the gate 11, and the output of the internal clock signal generation circuit 65 is fed back to the internal clock signal control circuit 64.

Here, the operation of the above configuration will be explained based on the flow chart shown in FIG. circuit 62
reads a certain number of synchronizing external clock signals T, and detects the frequency of the synchronizing external clock signals T (step Pi).

Next, when a certain number of external clock signals T for synchronization successively enter the phase error range of the phase detection circuit 63, the phase detection circuit 63 detects the phase of the external clock signal T for synchronization. The internal clock control circuit 64 uses the phase of the external clock signal T for synchronization detected by the phase detection circuit 63 and the frequency of the external clock signal T detected by the frequency detection circuit 62 to generate the internal clock signal generation circuit 65. Initialize the generated internal clock signal CLK (step P2
). Once initialized, the internal clock signal CLK causes the internal clock signal control circuit 64 to control the input of the external clock signal T through the gate 61 (step P3).
). When the external clock signal T is input here, the gate 61 only clocks in within the expected time tolerance (±5%).
is open. Therefore, even if the external clock signal T is input to the gate 61 due to noise or the like while the gate 61 is in the closed state, the input of the external clock signal T is ignored and the internal clock signal CLK is held.

Further, it is determined whether or not the external clock signal T is input while the gate 61 is in the open state (step P5). Here, when the external synchronization clock signal T is input to the gate 61 while the gate 61 is open, the internal clock signal control circuit 64 resets the phase of the internal clock signal CLK based on the output from the phase detection circuit 63. (Step P6).

If the external clock signal T is not input while the gate 61 is open, the number of times the external clock signal T that is not input is lost is calculated (step P7). If the number of losses is less than a predetermined number (for example, 8 times), it is determined that it is a temporary noise or momentary interruption, and the internal clock signal CLK
(Step P8). If the number of losses is equal to or greater than a predetermined number, it is determined that there is a synchronization difference between the external clock signal T and the internal clock signal CLK, and the internal clock signal CLK is initialized. The manner in which a stable internal clock signal CLK is obtained in the process of this operation will be explained based on the waveform diagram shown in FIG.

In FIG. 4, it is assumed that there is noise 12 etc. in the power waveform AC of an alternating current for power supply, for example, which is transmitted through the signal line 1. At this time, an unnecessary pulse 13 is present in the external clock signal T obtained by rectifying and shaping the power supply waveform AC, and other pulse omissions 14 and the like are also present. In this case, the open/close state of the gate 61 is as shown by the gate waveform G, and the input of the unnecessary pulse 13 of the external clock signal T when the gate 61 is in the closed state (0 state) is ignored and the internal clock signal CLK is Retained. Further, when the gate 61 is in the open state (1 state), the pulse omission 14 of the external clock signal T is ignored and the internal clock signal CL
K is retained. Note that R5 in FIG. 4 is a control output signal of the modem 3, which is in a state of 1 when a transmission request is made.

SD indicates a transmission data signal, each bit 15a, 1
5b will be transmitted in synchronization with internal clock signals CL and K.

In this embodiment, a gate 61 is provided, the opening and closing of the gate 61 is controlled by an internal clock signal control circuit 64, and the input of the external clock signal T in the open state of the gate is detected to re-phase the internal clock signal CLK. Since the settings are made, the phase of the internal clock always follows the phase of the external clock signal.

〔Effect of the invention〕

As described above, according to the present invention, the internal clock generation means is provided, and by controlling the gate by the internal clock control means, only reliable external clock signals are selected and taken out. Since the internal clock signal is controlled by the clock signal, a highly stable internal clock signal can be obtained even if the external clock signal becomes unstable due to disturbances such as noise. Highly synchronous communication control becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing synchronous communication using signal lines used in the present invention, FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is a flowchart showing the operation of one embodiment.
FIG. 4 is a waveform diagram showing signal waveforms in each block constituting the present invention, and FIGS. 5 to 7 are diagrams for explaining conventional synchronous communication. 62... Frequency detection circuit, 63... Phase detection circuit,
64... Internal clock signal control circuit, 65... Internal clock signal generation circuit.゛Representative Masuo Oiwa (and 2 others) 2nd r.
I! i Fig. 3 Fig. 4 , □ SO+ Fig. 5 Fig. 6 Fig. 7 Self-motivated to write procedural amendments

Claims (2)

[Claims] (1) In a signal transmission system that performs synchronous communication control using a clock signal, a gate, frequency detection means and phase detection means for detecting the frequency and phase of an external clock signal T input through the gate, and internal clock signal generating means controlled based on the frequency and phase detected by the frequency detecting means and the phase detecting means; and internal clock signal control for opening the gate based on the internal clock signal output from the internal clock signal generating means. 1. A disturbance prevention circuit for a signal transmission system, characterized in that the disturbance prevention circuit for a signal transmission system is characterized in that it performs synchronous communication control using an internal clock signal output from the internal clock signal generating means. (2) A disturbance prevention circuit for a signal transmission system according to claim 1, wherein the external clock is composed of a power synchronization pulse extracted from a commercial power supply frequency.