JPS61223962A - Memory controller - Google Patents

Abstract

PURPOSE:To attain data transfer in high speed independently of data width by shifting a data in the unit of bits, masking the data in the unit of bits and writing it to a transfer destination. CONSTITUTION:A shift mask production section 12 gives a shift amount of data to a barrel shifter 10 and gives a command which bit is to be masked to a mask circuit 11. A control section 16 controls the shift mask production section, a transfer address production section 6, an address switch section 7 and a register 8 at each bus cycle by the start from a CPU 1 to control the execution from a VRAM to VRAM transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory control device that controls memories, and more particularly to a memory device that controls data transfer between the same memory or between different memories.

(Prior art) Conventionally, rectangular areas are stored in refresh memory (VRAM), such as when drawing characters or moving part of a screen using a bitmap method that expresses one point on a display such as a CRT using one or more bits of information in memory. Data transfer was handled by software. Since this configuration requires many program steps, it has the problem of requiring a large amount of processing time for data transfer.

Therefore, in order to solve this problem and increase the speed, for example, Japanese Patent Laid-Open No. 58-4470 discloses a technology that has a transfer address counter in hardware and uses control logic to speed up data transfer in a rectangular area. is disclosed.

(Problem to be Solved by the Invention) However, although the configuration described in the above document can achieve high-speed data transfer, it does not take data width into account, so for example, the number of bits in an l word is large. In some cases, there is a problem in that there are restrictions on both the transfer device and the transfer size.

Therefore, an object of the present invention is to provide a memory control device that solves these problems and enables high-speed transfer of bits to any position regardless of data width and without restrictions on transfer size. shall be.

(Means for Solving the Problems) The present invention is a memory control device that controls data transfer between the same memories or between different memories.

According to the invention, this memory control device includes a shift circuit, a mask circuit, and a shift mask circuit. The shift circuit shifts the data stored in the transfer source bit by bit. The mask circuit masks the shifted data of the transfer source bit by bit and outputs data to be written to the transfer destination. The shift mask circuit determines the shift amount of the shift circuit and information regarding the mask based on information including the storage state of data at the transfer source and the transfer destination.

(Operation) Data at the transfer source is shifted bit by bit by the shift circuit, further masked bit by bit by the mask circuit, and written to the transfer destination. This bit-by-bit shifting and masking is controlled by a shift-mask circuit based on information including the data storage states of the transfer source and transfer destination.

For example, when data is transferred between the same memories using the read-modify-write method, data to be transferred stored in this memory is input to a shift circuit. The shift circuit shifts the data at the source by the difference between the transfer start points of the source dot address and the destination dot address. The mask circuit inputs the shifted data of the transfer source as well as the data of the transfer destination, and determines which data should be written to the transfer destination of the memory based on the mask information. For example, data from the transfer source is rewritten in a portion of the same memory where there is no need to rewrite the data currently written in the transfer source, and data from the shift circuit is written in a portion that needs to be rewritten. Which data to write is determined by a shift mask circuit based on information regarding the storage state of data at the transfer source and transfer destination. Similarly, the shift amount of the shift circuit is determined by the shift mask circuit.

(Example) Hereinafter, the present invention will be described in detail based on an example with reference to the drawings.

First, in the following explanation, the transfer source will be referred to as the source, and the transfer destination will be referred to as the destination. In addition, the first
The following embodiment will be described assuming that both the source and destination are the same memory (VRAM) and that data of an arbitrary rectangular area is transferred. Note that this transfer is referred to here as V
This is called RA) I→VRAM transfer.

First, the concept of VRAM→VRAM transfer performed in the first embodiment and the definition of the symbols related thereto are shown in FIG. 2(a).
This will be explained with reference to and (b). Figure 2 (a) shows the VRA
The storage area of M is shown.

In the figure, P is the VRAM pitch, SP is the transfer start point on the source side, the transfer start point on the destination side, HS is the horizontal transfer size, and vs is the vertical transfer size. This information (hereinafter referred to as SP)
. On this occasion,
According to this invention, as will be described later, both the transfer position and the transfer size can be freely changed in bit units. Note that the transfer order is from left to right and from top to bottom. Also,
The numbers in the small sections in the figure indicate addresses of the VRAM, and in this example, the VRAM has a shape of P words in width and N lines in length.

(a) and (b) in Figure 2(b) are SP and D, respectively.
In the figure, which shows details of the top line of P, SP is an address in word units S%1lA (hereinafter referred to as SWA) and a position in dot units (dot address) SDA (
(hereinafter referred to as S[]A) in bit units. Like SP, DP also uses word-based address OWa.
(hereinafter referred to as DWA) and position 00A in dot units
(hereinafter, [)DA) is specified in bit units.

In addition, in the figure, HS is the horizontal transfer size (hereinafter simply H
5), and the horizontal transfer size in words HIII
S (hereinafter referred to as HWS) and horizontal transfer size HDS (hereinafter referred to as HDS) in bit units.

Next, FIG. 1 shows a block diagram showing the hardware configuration of a first embodiment that performs the VRAM→VRAI'1 transfer. In the figure, 1 is a CPU, and 2, 3, and 4 are an address bus, a data bus, and a control bus of the CPU, respectively. Reference numeral 5 denotes a display address generation unit which generates a display address for a CRT (not shown); 6 a transfer address generation unit which generates a source address and a destination address for the VRAM 13 having the storage area shown in FIG. 2(a); and 7 a display address generation unit. Part 5. Transfer address generation unit 6
and an address switching unit that selects one of the address buses 2 of CPU i and supplies an address to the VRAM 13. 8 is a register for temporarily storing source data output from the VRAM 13. 9 is a changeover switch for writing data from CPU i and for writing source data in register 8 during VRAM→VRAM transfer.

IO is a barrel shifter that shifts the data supplied via the changeover switch 9 in a ring shape. Reference numeral 11 denotes a mask circuit for retaining data that does not need to be rewritten as it was. 12 is a barrel shifter 10 and a mask circuit 11
This is a shift mask generator that controls the The shift command mask generation unit 12 provides the amount of data shift to the barrel shifter 10, and provides an instruction to the mask circuit 11 as to which bit to mask. 14 is the contents of VRAM13
This is a buffer 7 register for PU 1 to read. 1
Reference numeral 5 denotes a parallel/serial converter that converts parallel data into serial data in order to display the contents of the VRAM 13 on a CRT (not shown). 16 is a transfer address generation unit 6.1 upon activation from the CPU 1. Address switching unit 7. This is a control unit that controls the register 8 and the shift mask generation unit 12 for each bus cycle, and controls the execution of VRAM→VRAI'1 transfer.

Next, a detailed configuration example of the transfer address generation section 6 is shown in FIG. 3, where 20 is a destination address register (
Hereinafter, DAI) R toiu) -t', VRAM13 (7)
This initial value indicating the destination address is set in the DWA of FIG. 2(b). This address is set to +1 or a new value each time data is written once or twice. 21 is a destination line start address register (hereinafter referred to as DLSA);
Like 0ADR20, the initial value is set to DIIIA, which indicates the left end address of the rectangular area on the destination side. This address holds the same value until the transfer of l line is completed, and transfer is transferred to the next line. When + pitched. At this time, the same value is also stored in the DADR 20, and the destination address is also moved to the left end of the next line. 22 is a source address register (hereinafter referred to as
5ADR), and 23 is a source line start address register (hereinafter referred to as 5LSA). Both of these initial values are set in SWA in FIG. 2(b).

5ADH22 is set to +1 or a new value each time data is read. When the 5LSA 23 completes the transfer of one line and moves on to the next line, the content P of the pitch register 26, which will be described later, is added. At this time, the same value is also stored in 5ADR22, and the source address also moves to the next line. 24 is a selector.

0AOR20, DLSA21,
Any one of the outputs of 5ADR22 and 5LSA23
Select one.

25 is a register that stores data l, 2B is CPU 1
A pitch register, 2?, stores the pitch P supplied via the data bus 3 from 2? is register 25 and register 2
This is a selector that selects one of the outputs of B. 2B is an adder that adds the outputs of the selectors 24 and 27. A selector 29 selects the output of the adder 28 and cp according to a control signal supplied via a control line 29c.
Select one of the data from u t (data at the time of initial setting of each register), 0ADR20, 0LSA2
1, 5AOR22 and St, 5A23 inputs, respectively. 30 is an address selector which selects the address selector according to the control signal supplied from the control unit 1B via the control line 30c.
Either the output of the DADR 20 or the output of the 5ADR 22 is selected and supplied to the VRAM 13 via the address switching unit 7 shown in FIG. In addition, in the figure.

20c, 21c, 22c, and 23c are the DADR 20, DLSA 21, and 5AD from the control unit 16, respectively.
This is a strobe signal line that supplies control signals to R22 and 5LSA23.

With such a configuration, the transfer address generation unit 6 generates a transfer address (an address including both a source address and a destination address) that moves from left to right and from top to bottom on the storage area of the VRAM 13. As one of the operations, the pitch register 26 is set to the value of the mouth LSA 21.
Adding the value and storing the added value in the LSA 21 and DADR 20 can be realized by controlling as follows. First, the selector 24 is connected to the DLSA 21 via the control line 24c.
The selector 27 is set via the control line 27c so that the data in the pitch register 2B is selected. Further, the selector 29 is set so that the output of the adder 28 is selected via the control line 29c. The output of the adder 28 is connected to the strobe signal line 200.
and 21c, 0ADR20 and DLSA2
Written to 1.

The control lines and strobe signal lines shown in FIG. 3 are controlled by a control section 16 that operates according to a control flowchart described later.

FIG. 4 shows a detailed configuration example of the shift mask generation section 12 shown in FIG. 1. In the figure, 31 is a mask register (hereinafter referred to as Ml) that stores first mask information;
32 is a mask register II that stores second mask information.
(hereinafter referred to as MII). 42 is a register (hereinafter referred to as MIIc) that simultaneously stores the carry of the adder 37, which will be described later, when data is stored in the MU 32. 33 is the dot position ii 5 of the transfer start point on the source side.
A source dot address register (hereinafter referred to as 5DAD) stores the DAD, and 34 is a register that stores the shift 1sHIFT of the barrel shifter IO (Fig. 1) written as a result of subtracting 5DAD from the dot position DDAD of the transfer start point on the destination side. (Hereinafter, 5HIFT
35 is a horizontal dot register (hereinafter referred to as HO) that stores the transfer size HDS in bit units in the horizontal direction.
3B is a selector, and control unit 1B (referred to as OT) is a selector.
5DAD 33, 5HIFT 34 and HD
Select and output one of the outputs of the OT35. 3B
is a register that stores DDAD given from CPU l via data bus 3 during initial setting, and 39 is data 0.
A register 40 stores the control line 40 from the control unit 16.
This is a selector that selects the output of one of registers 38 and 39 based on a control signal given via c. Note that the selection of the register 38 means that the selector 36
This means that the output from the adder/subtracter 37 is output as is. 37 is an adder that adds or subtracts the outputs of selectors 3B and 40; The selection between addition and subtraction is made by the control unit I8.
This is performed by a control signal applied from the control line 37c to the control line 37c. 41 is a selector that selects either one of the data from the adder/subtractor 37 and the data from the CPU I (data at the time of initial setting of each register) based on a control signal given from the control unit 16 via the control line 41c. MI 31
, M II 32 , SDA [133, 5t (EF
Output to T34 and HDOT35. Whether or not to capture the selected data is determined by the strobe signal lines 31c and 3.
2c.

It is determined by the control signal from the control gI section 16 via 33c, 34c and 35c.

The outputs of MI31 and M TI 32 are connected to the inputs of mask source I43 and mask source Tl44, respectively.

The mask source I43 outputs information as to whether each bit of data output from the VRAM 1B should be masked, in response to the first mask information output from the MI 31. Here, Table 1 shows a mask source I truth table that defines the relationship between the first mask information and the mask source I43.

(Left below) This table shows the case where the first mask information is 4 bits and the width of 1 word is 16 bits. As can be seen from the table, when the first mask information is all O from the mask source I43, all 16 bits are left unmasked (indicated by 0°).
In other cases, the LSB side is masked without including the bit decoded from the first mask information (“l”
) output is obtained. Similarly, mask source H44
has a mask source truth table shown in Table 2 below.

(Left below) As can be seen from the table, from the mask source 1144, the second
When the mask information is all 0, all IB bits are masked, and in other cases, bits obtained by decoding the second mask information are included, and from this, an output that masks the MSB side is obtained.

The output of mask source I (mask bits) is output from EOR gate 45.
The output of the mask source (mask bit) is supplied to one input of the EOR gate 46.

The other inputs of EOR gates 45 and 46 are connected to mask inversion control line 51 from control section 1B in FIG. The outputs of the mask source I43 and the mask source 1144 are controlled to be inverted or non-inverted depending on the state of the mask inversion control line 51.
The outputs of EOR gates 45 and 4B are connected to one input of AND gates 47 and 48, respectively. The other inputs of the AND gates 47 and 48 are connected to a mask I valid control line 52 and a mask II valid control line 53, respectively, which are connected to the control section 1B. Depending on the states of these control lines 52 and 53, mask source I43 and mask source lI4
Control is performed so that all outputs of the mask source I43 are valid, only the output of the mask source I43 is valid, or only the output of the mask source 1144 is valid. The outputs of AND gates 47 and 48 are connected to OR gate 48 and mask line 50.
is connected to the terminal M of the mask circuit 11 in FIG.

As mentioned above, there are two types of mask sources, and these are used as EO.
R gate 45.4B, AND gate 47.48 and OR
At the mask line 50 through the gate 48,
The greatest feature of this invention is that it is possible to create continuous mask areas and non-mask areas at arbitrary positions and with arbitrary widths.

FIG. 5 shows a detailed configuration example of the mask circuit 11 shown in FIG. signal line, 81 is VRAM
It is connected to the output of
This is a signal line for supplying to the D gate 63. The mask line 50 is connected to an AND gate 62 via an inverter and to an input of an AND gate 63. The outputs of AND gates 62 and 83 become inputs to OR gate 64.

The output of OR gate 84 is connected to the input of VRAM13. To explain the operation, when the mask line 50 is a “1” bit, the destination side is selected;
When the bit is “O”, the source side is selected and VRAM1
This will be the write data of 3. Therefore, for data whose mask bit is 1, the same data as before is written, and for data whose mask bit is 0, source side data is written.

FIG. 6 shows a detailed configuration example of the control unit 1B shown in FIG. It is reset when the tree 71 starts operating. A register 72 stores the horizontal transfer word size HWS, and is initialized by CPU t. 73 is a counter that manages the amount of data transferred in the horizontal direction, and is decremented by 1 every time one word of data is transferred in the horizontal direction, and when it reaches 0, the control tree 7
1, the HWS will be notified by the control tree.
is loaded and returns to the initial value. Reference numeral 74 denotes a counter for managing the number of words to be transferred in the vertical direction vs. the initial value is set by the CPU l. When VRA → VRAM transfer is started, -1 is set every time one horizontal line transfer is completed, and when it becomes 0, the control tree 71 is notified of this and the transfer ends. 7
A register 5 stores the dot positional relationship between the source side and the destination side, and is calculated and initialized by the CPU 1 in advance. Depending on this state, the operation of the control tree 71 differs as will be described later. A flip-flop (ILFF) 76 provides a flag when the control tree 71 operates, indicating that the left end of the rectangular area is being transferred, and the control tree 71 is reset. Similarly to the flip-flop 78, 77 is a flip-flop (referred to as RFD, F) that provides a flag when the control tree 71 operates.
Reference numeral 1 denotes a control tree that controls each part of the apparatus according to an algorithm described later. control tree 7
1 outputs the various control lines described above.

The above is the configuration of one embodiment of the present invention.

Next, the operation will be explained.

:s7 Figure shows a flowchart showing an outline of the operation. In the figure, 100 is the initial setting performed by GPIJI. First, in step 101 (hereinafter, step is simply abbreviated as S), the width pitch P of the old VRA 3 is set, and the source start point SP of the 0th order is set in 5102. Specifically, the word address sWA explained in $2 figure (b)
are respectively written to 5ADR22, Sl, and 5A23 shown in FIG. 3. Next, in step 103, a destination start point DP is set. Specifically, in step 104, the transfer size HS in the horizontal (horizontal) direction is
Set. At this time, use DDAD in advance using cpul.
+ HOOT is calculated, and if this value is larger than IB, the horizontal transfer word size HWS is +ll and written to the register 72 in FIG. Further, the dot portion HDS is written to HDOT 35 shown in FIG. Next, the vertical transfer size VS is set in step 105. At this time, the 6th
The initial value VS is set in the counter 74 shown in the figure. Next, in step 10B, the source S and the destination D are set.
The CPU 1 calculates the magnitude relationship of 0 and sets it in the register 75 shown in FIG. 6. Next, in step 107, the register 70 shown in FIG. After making the initial settings as described above, move the VRA from the source side to the destination side in a rectangular area as shown in Figure 2 (a).
M→VRAM transfer is performed.

Next, the operation of the control tree 71 shown in FIG. 6, which controls VRAM→VRAM transfer, will be explained according to an operation flowchart. Here, the notation used in the operation flowchart will be explained using FIGS. 12(a) to 12(d). 11
0 is a flip-flop, and each step is divided into rows <,
Reference numeral 111 indicates conditional judgment, which is composed of logic gates. 112 indicates the operation performed by the control tree 71 at that step. 113 outputs a control signal so that the data on the right side is stored on the left side of the symbol, and when the primary flip-flop is set, the data is stored. 114 indicates that the left signal is changed to the right state. Reference numeral 115 indicates a connection relationship between flowcharts, in which objects having the same symbols in this figure are connected.

FIG. 8 shows the initial operation flow of the control tree 71. A flip-flop 5201 waits for activation and continues to be set until the start register 70 in FIG. 6 is set. 3202 is a start determination section based on the output of the start register 70 in FIG. 6, and when the start register 70 is set, Sl is set at 8203. When S1 is set, a complementary signal for performing the control operation shown at 5204 is output, and when S2 is set, the operation ends. 5TART R9T issues a signal to reset the start register 70, 5HIFT -DD
AD-9DAD outputs signals to each control line of the shift-mask generator 12 shown in FIGS. 1 and 4.
-5DAD(7) value is stored in 5) IIFT34. H
C←old means that the contents HSW of the register 72 shown in 6 are stored in the counter 73.

When 82 is set in 5205, SA is set according to the flag SD indicating the positional relationship between the source and destination shown in FIG.
It branches to either D or SAD and is processed.

FIG. 9(a) shows the case where S=D. First, 8 in FIG.
When 82 of 205 is set and branching to this flow, various control signals for performing the processing shown at 5301 are issued, and when R1 is set, the operation is completed.

301 is a cycle in which source data is stored in register 8 in FIG. First, the 33011 outputs a load signal to the register 8 via the control line 80 shown in FIG.
A control signal for selecting the output of the 5ADR 22 is output via the control line 30c. In addition, in the following explanation, VRAM13
The address supplied to 53012 is called VADR.
Then, depending on the value of HC of the counter 73, the following two types are used. That is, when IC=O, it indicates that this is the last destination read in the horizontal direction, and when H#O, it indicates that the destination read in the horizontal direction is still being continued.

53013, M n 32 and 5HIFT3 in Fig. 4
4 stores D[lAD -9DAD, and 5AD in Figure 3.
R22 is incremented by +1, and counter 73 in FIG. 6 is decremented by -1.
53014 moves the source address to the beginning of the next line,
Initialize the counter 73, increment the counter 74 by 1, and
Each control signal is output from the control tree 71 so that II 32 is replaced with DDAD +HDOT.

302 relates to an operation in which the contents of the register 8 are shifted by the barrel shifter 10 and data masked by the mask circuit 11 is written to the destination.

53021, in order to set MASK=MI (a valid mask source is represented by MASK=), a control signal is output to the mask I valid line 52 shown in FIG. 4, and VADR is changed to DA.
To set it as DR, the address selector 30 shown in FIG. 3 outputs a complementary signal that outputs 0ADR20,
Outputs a write enable signal to.

In S3022, the process is divided into two depending on the HC value of the counter 73. Similarly to 53012, when HC=O, it indicates that this is the last write in the horizontal direction, and when HCζ0, it indicates that the process is still continuing. In 53024, for the next word transfer, the value of 5HIFT 34 is set in J 31. Write and issue a control signal to increase DADR20 by 1, 3
In 3024, in order to move the transfer to the left end of the next line, the third
DISA+P to DADR2G and [1ISA21 in the figure
Since the current write is at the right end, M n 32 is also output as a mask signal along with MI 31 to prevent unnecessary parts on the right side from being rewritten.

Reference numeral 303 is a part that determines the end of horizontal direction transfer and the end of vertical direction transfer. 1 in 53031 and S 3032
(The transfer of all areas is completed when c=o, vc=o, and NOTBUSY 201 in FIG. 8 is executed) and waits until the next transfer starts.

Figure 9(b) shows an example of transfer of 5DAD=DDAD0
The figure shows only one line of source and destination. 001 is the first source data and is read into register 8. The value of DDAD (7 in this example) is preset in MI31, so by enabling MI, the 001A part is masked and becomes 0OIB.
Source data is written only to

Next, add 1 to the source and destination.
and reads 002 into register 8, oo to MI132
When reading t, the value of DDAD + HDOT (in this example, 1
5+7=22 The lower 4 bits are taken and 6) is set, and by enabling M II 32, 002A is masked and source data is written only to 002B.

In this way, data is written only to the necessary portions.

After that, the source address and the destination address are moved to the beginning of the next line, and the same process is repeated to perform data transfer in the rectangular area.

FIG. 1O(a) shows a processing flow when 5DAD<[1DAD. 401 is a cycle for reading data from the source and storing it in the register 8, which is the cycle 3 shown in FIG. 9(a).
Performs the same operation as 01. 402 is a write cycle to the left side of the destination, and 403 is a write cycle to the right side of the destination. That is, the data read to transfer one word is divided into two parts and written to the destination. S4
In 021, MI31 is enabled and VADR@DADR
I, VRAM write enable signal (VRAMW
E) and add 1 to 0AOR20. At 54022, the process branches into two depending on the He value of the counter 73. 5
At 4023, HC″r, 0, that is, horizontal transfer is in progress, the value of 5HIFT 34 is stored in M T 31, and DADR20 is incremented by 1.

S4024 determines that MIIc42 is 0 in order to detect the last left 'transfer in the lateral direction.54025
is when MIIc42 is 0, that is, when the last transfer is sufficient only to the left side, and MII32 is also a mask condition.

DDAD to MI31 to disable the next right transfer.
+HDOT, that is, the same value as MII32 is stored. 4
03 is a write cycle to the right side. 54031 sets VADR to DADR and outputs a VRAM write enable signal, 54032 performs HC=O determination, 5
4033 operates when HCxOl, that is, horizontal transfer is still continuing, and is when writing data to the left side of the next address of the destination written in 402.

Therefore, in order to mask the opposite side of MI 31, the mask source! 43 and mask source n44 are respectively inverted by EOR gate 45 and 4B-t' (MASK INV), M
I 31 shall be valid. In 54035, the above-mentioned 4024
Make the same judgment. 8403B is the case where left side transfer is not required at the end of the horizontal direction, and MI31 is M at 54025.
It is set to the same value as II32. Here, MI3
By enabling 1, MII32 with 54034
is enabled, so both are enabled, all bits are masked, and no write operation is performed.4
04 is similar to 303 in FIG. 9(b).

FIG. 1(b) shows an example of a transfer where SDA<DDAD. Oll is the first source data and is read into the register 8 shown in FIG. The read data is shifted by the barrel shifter 10, and by enabling M I 31, 0OIA is masked and data is written only to 001B. Add 1 to the destination address and M I
31 is made valid and the mask is inverted (M I ), thereby masking 0110 and writing data only to 011G. Next, add 1 to the source address and read the data of 012 into register 8, MII32 is 口DA口+)
Since it is set to IDOT, MI31 and M II
By enabling 32, 012A and 0120 are masked, and only 012B is written. The 0th order is MI31.
is set to D[]A[l+HDOT, that is, the same value as MI31, and MI31 and MI32 are enabled, thereby masking both 0120 and 012E, that is, all bits are masked. These operations are repeated to transfer data in a rectangular area.

FIG. 11(a) shows the processing in the case of SDA>DDAD.

501 is a cycle for reading data from the source and storing it in the register 8. In addition to the same operation as 401 shown in FIG. When O, set flip-flop 77 (ILFF 5ET)
, 502 is a write cycle to the right side of the destination, 503 is a write cycle to the left side of the destination, and 5DAD<
As in the case of DDAD, l words are read and written in two parts.

S 5021 and S 5022 are each S 4021
, has the same function as S4022. 35023 determines the ILPP of the flip-flop 76. 5502
4 is when ILFF=1, that is, the first word in the horizontal direction, and since the writing operation of the part 012B in FIG. 11(b) is performed, M II 32 is also output. Furthermore, in order to write 022B, DADR must not be +1.

Furthermore, the flip-flop 77 is reset to prevent writing of 022C. 35027 is HC=0
, MIIc = O, that is, when the second write operation is unnecessary in the last transfer in the horizontal direction, the flip-flop 7B is reset and M n is used as mask information.
32 is also enabled. 35028 skips the second memory write depending on the value of flip-flop 7B, 503 indicates the second memory write size') Ay-QT
o6.5503141, VADRf DADR L, V
55032, which issues a RAM write enable signal, determines whether or not it is the last transfer in the horizontal direction. 35033 is a case where the horizontal transfer is still continued, and the transferred state of M I 31 is masked. 35034 is the last write operation in the horizontal direction, data is masked by MII32, and D
LSA21.

Move DADR20 to the beginning of the next line, 504 is the ninth
This is similar to 303 in Figure (a).

FIG. 11(b) shows an example of SDA>mouth DAD, 02
1 is read into the register 8 and shifted by the barrel shifter 10 as in the example of SDA port < DDA port. Mn31 is D
DA port, MII32 is set to 5) IIFT amount,
By enabling both, only the source address of the 0th order where only 012B is rewritten is incremented by 1, and the source data is read into the register 8. Next, set M I 31 to 5 HIFT amount, and by masking Mn 31, only 022B data is rewritten. Next, set the destination address by +1.
, By inverting and masking Ml, data is written only to 002C. Add 1 to the source address of the 0th order, read data to register 8, and set MII32 to DDAD+ HD.
Set to OT, enable M I 31 and Mn 32,
023B+71 completes the transfer of the rewritten l line. Thereafter, the same process is repeated to transfer the rectangular area.

The first embodiment of this invention has been described above. According to this embodiment, VRAM→VRAM transfer can be performed in bit units at high speed regardless of the data width. In addition, in this embodiment, an address of 18 bits is used for a general microC.
The same form of addressing as the PU is now possible, and the CPU
It has the advantage that it is easy to directly access the VRAM 13 from l and process data. Furthermore, since the bus of CPU 1 is free during the transfer process, CPU 1 can execute other programs, improving system throughput.

Furthermore, a mask circuit! Since read-modify-write is used for I, masking operations with destination data can be easily performed by adding a circuit, which is also highly effective for graphic processing. Furthermore, since a portion of the screen can be moved at high speed, the screen can be easily edited. If this embodiment is applied to a multi-window system, which is currently being developed into a multi-window system, it will be possible to open and close windows at very high speed.

Next, a second embodiment of the invention will be described. 1st
The concept of this embodiment is shown in FIGS. 3(a) and 3(b). 3(a) shows the storage area of VRAM, and FIG. 2(b) shows the storage area of font memory. In this embodiment, data is transferred from the font memory to the VRAM. In the font memory, images are normally stored at consecutive addresses 0°1.2, . . . . According to this embodiment, by specifying the pitch P of the VRAM, the horizontal and vertical sizes of the font, the font start point FP, and the VRAM start point DP, information in the font memory can be stored at any position on the VRAM in any size. Can be transferred. FIG. 13(C) shows the configuration of this second embodiment. As can be seen from FIG. 13(C), this configuration is the same as that shown in FIG. 1 in which the register 8 is replaced with the font memory 17. It is. The operation is the same as that of the first embodiment except that the address increment of the font memory 17 does not have a + pitch like the first embodiment, so a detailed explanation will be omitted here.

In the second embodiment described above, character fonts of different sizes can be drawn at arbitrary positions at high speed, and scientific and technical calculation formulas and scripted characters can be drawn.

FIG. 14(a) shows the concept of a third embodiment of the present invention. This embodiment is a multi-plane version of the VRAM 13 shown in FIG.
FIG. 14(b) shows the configuration of this third embodiment, which performs AM transfer. As shown in FIG. 14(b), the register 9, barrel shifter 10, mask circuit 11, and VRAM 13 are shown.
, the buffer register 14, and the parallel/serial converter 15 are each composed of a plurality of elements as shown in the figure. The operation is similar to the first embodiment.

According to this embodiment, since the number of bits per pixel can be increased, color display is possible and the transfer speed can be increased.

(Effects of the Invention) As described above, according to the present invention, data can be transferred between the same memories and between different memories at high speed in units of bits at arbitrary positions regardless of the data width. Further, according to the present invention, the central processing unit can perform completely different control during data transfer, and the throughput of the system can be improved.

This invention applies not only to data transfer of refresh memory related to CR7 display, data transfer between font memory and refresh memory, and data transfer between multi-plane refresh memories, but also data transfer between refresh memory and external storage devices such as disk devices. It can be applied to control of data transfer of all kinds of memories, such as data transfer of memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a diagram for explaining the concept of data transfer in the first embodiment, and FIG. 3 is a transfer address generation shown in FIG. 1. 4 is a block diagram showing an example of the structure of the shift mask generating section shown in FIG. iB. FIG. 5 is a block diagram showing an example of the structure of the mask circuit shown in FIG. FIG. 6 is a block diagram showing an example of the configuration of the control section shown in FIG.
FIG. 7 is a flowchart of the general operation of the first embodiment, FIG. 8 is a flowchart of the initial operation of the first embodiment, and FIG. 9 is a flowchart of the initial operation of the first embodiment.
Figure (a) shows 5DAD=DDAD in the first embodiment.
FIG. 9(b) is a flowchart of the operation in the case of , and is a diagram showing an example of data transfer according to this operation. Figure 1θ (a) shows 5t) AD<0 in the first embodiment.
An operation flowchart in the case of OAO, FIG. 1θ (b) is a diagram showing an example of data transfer according to this operation, FIG. 11 (a)
is an operation flowchart in the case of 5OAO>口04口 in the first embodiment, and FIG. 11(b) follows this operation.)
A diagram showing an example of data transfer, FIGS. 12(a) and 12(b) are diagrams for explaining the definitions of figures used in the above operation flowchart, and FIGS. 13(a) and (b) are diagrams showing the second example of this invention.
Figure 1 for explaining the concept of data transfer in the embodiment of
3(C) is a block diagram showing the configuration of the second embodiment, FIG. 14(a) is a diagram for explaining the concept of data transfer in the third embodiment of this invention, and FIG. 14(b) is a block diagram showing the configuration of the second embodiment. ) is a block diagram showing the configuration of a third embodiment. l...CPU, 5...Display address generation section, 6...
- Transfer address generation section, 7...address switching section. 8...Register, 9...Selector switch, 10.
...Barrel shifter, 11...Mask circuit, 12...
Shift mask generation unit, 13...VRAM, 14...
- Buffer register, 15... Parallel/serial converter, 16... Control unit, 17... Refresh memory, 20... Destination address register (DADR), 21... Destination line start address register (DLSA), 22... Source address register (5ADH), 23
...Source line start address register (5LS
A), 24.27.29...Selector, 25...Register, 26...Pitch register, 28...Adder, 30
...address selector,

Claims (1)

[Claims] A memory control device that controls data transfer between the same memory or between different memories includes a shift circuit that shifts data stored in a transfer source bit by bit, and a shift circuit that shifts data stored in a transfer source bit by bit. and a shift mask circuit that determines a shift amount of the shift circuit and information regarding the mask based on information including storage states of data at the transfer source and the transfer destination. A memory control device characterized by: