JPS604984A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention uses a dynamic RAM as a display memory [2], and controls memory access for display cycles and data update cycles in a time-sharing manner. ] This invention relates to a display device that performs READ/WRITE of display data.

[Technical background of the invention and its problems]

Recently, due to the demand for advanced graphic display, there are display devices equipped with a large amount of memory as display memory. In addition, peripheral LSIs dedicated to graphic display have also appeared (I), which have not only synchronization signal generation and character display control functions, but also high-speed graphic drawing functions and large-capacity display memory control functions. This LSI won the Grand Prize for 1) applications ranging from negative character display control to high-grade full graphic drawing/display control and image display control, as well as applications unrelated to display. It can be applied to fields that require memory control.

Note that drawing here refers to updating the contents of the display memory (
"Modification/change operation)" and "display" means reading out the contents of the display memory.

Therefore, the above LSI has a drawing cycle and a display cycle, and in the drawing cycle, there is always a read-modify-write (RMW).
te) the action is performed.

By the way, in the memory access of the above-mentioned device, there are typically two types: one in which the memory for display is read during the display period and drawing is performed only during the non-display period, and the other in which display and drawing are performed in a time-sharing manner. ) exists. Particularly in the latter case, separate display memories are provided for each even number raster and odd number raster, and the display memory has several words (two or more memory brains) in the horizontal direction to store display data. Therefore, it has the disadvantage that the memory area for display becomes large.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks.In a device that performs memory access for display and drawing in a time-sharing manner, display data used at the time of reading data for display and at the drawing timing is also read. The object of the present invention is to provide a display device that improves drawing speed and saves memory capacity.

[Summary of the invention]

In order to achieve the above object, the present invention continuously generates a CAS signal (page mode) for continuously reading a predetermined length of data from a display memory, and also inputs a column address during a READ cycle for display. By generating the lower number of bits as part of the column address, combining it with the externally given column address and supplying it to the address selector, selecting this in the READ cycle as the column address, and continuously supplying the CAS signal. Read ahead several words of data (
(including display data used in the drawing cycle).

As a result, the drawing speed is improved and the capacity of the display memory can be saved.

[Embodiments of the invention] Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, II is a microprocessor (μCPU) that controls the entire display device, and 12 is a CRT controller (CRTC).

The CRT controller 12 is a peripheral control LSI used to display characters and figures on a rusk scanning type CRT (cathode ray tube), and is used in most display fields from simple character display control to high-grade full graphic drawing display. Covers control in CRT controller 12
obtains the basic link (2
ADH), a row address selection signal (RAS), and a signal rBLANK indicating a non-display period. A bus driver (BD) 13 supplies data read from a display memory (MEM14), which will be described later, to the CRT controller 12 (DB
IN). A display memory (MBM) 14 stores display data, and is composed of a dynamic RAM. The display data (M0UT) obtained from the display memory 14 is transferred to the shift registers 15 to 18.2.
1 to 24. Shift register (PI3) ts
~1B, 2Z~24 convert parallel data obtained from the display memory 14 into serial data. The converted output (serial dots) is supplied to the CRT display 33 in accordance with the display timing and displayed as desired video data.

19 is an address register (AR). Address information (row/column) output from the C'RT controller 12 is latched into the address register 19. The address latched here is the address selector (ADRSE).
L zo). In the embodiment of the present invention, address information is set in the address selector 20 as an address (U/L) divided into upper 8 bits and lower 8 bits,
Further, address information (lower two bits of column address MCNTAD) output from the memory control circuit 31, which will be described later.

, , ) are also supplied as part of the lower address. The address information selected and output here is the display memo 111.
This is the access address for 4. Normally, the upper/lower address (U/L) of address information (row/column) is selectively supplied, but in the present invention, L' is selectively output as the lower address (limited to the time of READ for display). be done.

25 and 26 are AND circuits. AND circuit 25.26
The outputs of shift registers 15 to 1B and shift registers 21 to 24 are supplied to one input terminal of , respectively, and the control signal (DBL BLANK) output from the memory control circuit 31 and timing control circuit 32 is supplied to the other input terminal.
, $CLK, /$CLK) are commonly given. Here, it is determined whether or not the serial data obtained via the shift registers 15-18 and 21-24 should be supplied to the CRT display 33. 27 is an OR circuit (q). The OR circuit 27 obtains the outputs of the AND circuits 25 and 26, takes the logical sum condition, and supplies it to the CRT display 33. 28 is an OR circuit. The OR circuit 28 is a memory control The signals (MCAS, . . . ) output from the circuit 31 are obtained and logically summed to form a column address selection signal rMcA8), which is supplied to the display memory IJI4. 29.30 is the gate.

The gates 29 and 30 receive the upper signal (MC) from the control circuit 3I.
A8o to 3) are obtained, and based on the load enable signal (LD BNBo, , ) output from the memory control circuit 31, the corresponding shift registers are set to 15 to 18.21, respectively.
~24 Load signal LDo~, , LD to be supplied to ~24
, ~, are selected and output.

31 is a memory control circuit (MCC), and 32 is a timing control circuit (TCC). The memory control circuit sr is CR
BLANK signal, address information (ADD), and RAS signal from the T controller 12, and a clock $CLK which is 8 times the basic clock from the timing control circuit 32.
4, memory RAS signal, write enable signal (
WE), a signal obtained by delaying the BLANK signal by a predetermined time (
DELI3LANK ), and READ for display
At this time, the lower two bits of the column address are generated. Since this address generation is achieved by, for example, providing a binary counter and inputting an appropriate lock, it is intentionally not shown in the figure. The timing control circuit 32 uses a basic clock (2XCCLK) obtained from the outside.
), various timing signals are generated 12 and supplied to each part of the display device. For example, the basic clock (2XCCL
$CLK multiplied by K) by 8. $CLK multiplied by 16.

is supplied to the memory control circuit 3I and AND circuits 25 and 26. Also, LD ENBo and LD ENB select load signal supply for gates 25 and 26.

Generate and output signals.

FIG. 2 is a timing chart showing the operation of the present invention. In the figures, Shinbetsu with the same reference numerals or symbols as those in FIG. 1 have the same functions and names as those in FIG. 1. In addition, in the figure, RDS is the display cycle (READ
), RMWS indicates a drawing cycle (read-modify-write).

Hereinafter, the operation of the embodiment of the present invention shown in FIG. 1 will be explained in detail using the timing chart of FIG. 2.

The CRT-y controller I2 operates by controlling the display memory I4 in the READ cycle for display, and in the read modify write (R/M/W) cycle when updating the contents of the display memo II1.

First, the operation will be explained from the READ cycle.

RAS signal and address information (AD
D) is generated and output. The RAS signal generated here is input to the memory control circuit 31, where the memory RAS
A signal (MRAS) is generated i'L.

In addition, the control signal MCA3 is the basis for generating the MCA3 signal.

~ is generated and output. Address information ('ADD) output from the CRT controller 12 is latched into the address register 19 at the falling edge of the RAS signal (1). The latched address information is supplied to the address selector 2o, switched to a load address/column address, and becomes an access address for the display memory 14.

Here, the lower two bits of the column address are the address signal (MCNTA) output from the memory control circuit 3I.
) is selected by the address selector 2o. At this time, the memory control circuit 31 sends a control signal (MCk
So~3) are used sequentially, and the memo 1jcAs signal (MCA8) is stored in the display memory 14 via the OR circuit 28.
is continuously supplied.

As a result, l) sequential outputs (M0UT) are obtained from the display memory 14, and when the LDENB signal is active, the gate 29 outputs LDo-LDs are generated and set in the shift registers 15-18; on the other hand,
When the LD BNB signal is active, the display memory 14 output (MOU'I') is the gate 30 output LD
, ~LD, shift registers 21-2 are set. The input conditions of the AND circuit 25 are satisfied for the data set in the shift registers 15 to 18 (DL BLANK;
1. $CLK.

;1), the CRT display 3 via the OR circuit 27
Output to 3. In addition, the data set in the shift registers 21 to 24 satisfy the input condition of the AND circuit 26 (DL
BLANK;1. $CLK;1), it is output to the CRT display 33 via the OR circuit 22.

Next, the operation during the read/modify/write cycle will be explained. When the microprocessor II issues a drawing command to the CRT controller 12, the CRT
The controller 12 performs a drawing operation in the read/Φmodify/write cycle. First, the basic clock (2X
At the falling edge of CCLK), the CRT controller 12 sends the RAS signal and address information (ADD; A).
Do"=+s) is output, and its address is latched in the address register t9. The RA8 information is supplied to the memory control circuit 31, and based on this, the memory control circuit 3
1 is display memory l MRAS, M'C for 14
Generates and outputs an AS signal. The display memory 14 is
When both the λ1RAs and MCA3 signals are applied, memory data (M 0UT) corresponding to a predetermined address is output. This content is determined when the bus driver 13 is enabled by the DB IN signal and 3. +1, address bus (
READ to CRT controller I2 via ADR)
be done.

The CRT controller 12 modifies the RBAD1 data and outputs it to the address bus (ADH) at the rising edge of the fourth clock. DB IN this data
Write enable signal (WE) generated (depending on the signal)
Based on tc, it is written to the display memory 14.

In the embodiment of the present invention, the column address generated by the memory control circuit 31 is the lower two bits, and four words are read out at the display timing, but the present invention is not limited to this.

By varying the number of bits, the number of words to be read becomes possible as long as the memory speed allows.

〔Effect of the invention〕

As explained above, according to the present invention, it is not necessary to prepare multiple memory planes, saving memory capacity, and display data used at the drawing timing can also be read at the display timing. Improves drawing speed.

According to the present invention, the drawing speed is improved by 4 to 6 times, especially compared to a system that draws only during the non-display period.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the embodiment of the present invention. II...Microprocessor (μ CPU"112)
...CRT controller (CRTC') 13...Path driver (BI)) 14...Display memory (MEM) 15~
18, 21-24...Shift register (P/S)
l9... Address register (AR) 20... Address selector ('ADR5EL) 25.
26...AND circuit 27.28...OR circuit 29.30...gate 31...memory control circuit (MCC) 32...timing control circuit (TCC) 33...C
RT Display device applicant's agent Patent attorney Hiko Rin Ushiki

Claims (1)

[Claims] In a display device that performs memory access using a dynamic RAM as a display memory [by controlling the display cycle and data update cycle in a time-sharing manner using 7], after the RAS signal is supplied, the display memory is Continuous RFiAD data of a predetermined length from
In addition to generating and outputting the CAS signal, the memory control circuit also generates and outputs the lower n bits of the column address when displaying the image. address information (
(row/column) input and an address selector 17 that outputs either one as the access address of the display memory.During the display cycle, the column address output from the memo+1 control circuit is determined by the address selector (17). A display device characterized in that I) reads 2n words of desired display data by selectively supplying a CAS signal and continuously supplying a CAS signal.