JPS61222169A - Manufacture of hetero-junction bipolar transistor - Google Patents

Abstract

PURPOSE:To obtain a hetero-junction bipolar transistor having a fast switching rate by forming at least one of an emitter-base junction and a collector-base junction having no excess P-N junction except intrinsic regions in a hetero-junction. CONSTITUTION:An SiO2 film 22 is deposited on a semi-insutaling GaAs substrate 21, a hole is bored at a desired position, an N<+> sub-collector region 23 is shaped through ion implantation, the SiO2 film 22 is removed, and an AlGaAs layer 24 and a P<+> type AlGaAs layer 25 are grown. An Si3N4 layer 26 and an SiO2 layer 27 are formed onto the layer 25, and used as masks, and a hole is bored up to the surface of the substrate 21, and an N-type GaAs layer 28, a P<+> type GaAs layer 29, an N-type AlGaAs layer 30 and an N<+> type cap layer 31 are grown on the hole. An AuGe/Au layer 33 is evaporated, the SiO2 layer 27 is peeled, an intrinsic region in a transistor and a region as an external base region are coated with a CaF2/Au layer 34, and the resistance of a P<+> type AlGaAs layer 25 is increased through ion implantation while employing the coating layer as a mask for implantation. The layer 34 is removed, an ohmic electrode and an ohmic contact are shaped, and lastly a wiring is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a heterojunction bipolar transistor in which at least one of an emitter-paste junction and a collector-base junction is a heterojunction.

[Technical background of the invention and its problems]

Heterojunction bipolar transistors using heterojunctions such as GaAs/AIIGaS have attracted attention as next-generation high-speed devices, and have been developed using molecular beam epitaxy (MBB) method, which allows precise control of vertical dimensions, and organic Development is actively underway using epitaxial growth techniques such as vapor phase growth (MO('VD)) using metal gas.

FIG. 2 shows an example of a conventional GaAs/AJGaAs heterojunction transistor fabricated on a semi-insulating GaAs substrate. This structure can be created as follows. A mouth-type GaAs layer 12 that will serve as a collector, a p-type GaAs layer 13 that will serve as a paste, and an n-type AJG that will serve as an emitter are formed on a semi-insulating Ga substrate 1 by the MBE method.
aAs layer 14, emitter ohmic contact 9
15 epitaxially grown n"GaAs 1815 to facilitate the growth of this vkn"m Ga layer 15.
is etched leaving only a predetermined region, and for example Be is ion-injected into other regions to form the p+ type external paste layer 16.
form. Then, use the mesa etch knob to expose the collector layer, and attach 17 to each of the emitter, pace, and collector poles.
, 18 and 19 are formed.

Heterojunction bipolar transistors are expected to have high-speed switching characteristics because they use a high-carrier-concentration layer in the base to achieve low base resistance, but actual devices do not require an external base or collector, as shown in Figure 1. A junction is formed, and the capacitance of this junction increases the switching speed. For this reason, transistors have excellent characteristics in the intrinsic region, but unnecessary junctions caused by immature processes greatly impair their original characteristics. Therefore, in order to fully exploit the characteristics of a heterojunction bipolar transistor, it is necessary to eliminate the junction between the external space and the collector.

[Purpose of the invention]

An object of the present invention is to provide a preferred manufacturing method for producing a heterojunction bipolar transistor with high switching speed.

[Summary of the invention]

The method of the present invention involves forming a region to become a subcollector in a predetermined region of a semiconductor substrate by ion implantation or diffusion, epitaxially growing a semiconductor layer having the same lattice constant or the same as that of the substrate on this substrate, and growing the semiconductor layer epitaxially on this substrate. A conductive layer of the same thickness as the surface is formed from the surface to an appropriate depth, and with an appropriate mask, the portion overlapping a part of the previously formed sub-collector region is deposited to the semiconductor substrate.
E, etc.] and apply MBE or MO to the opened area.
Collector, base, emitter in order by CVD method,
The base layer is epitaxially grown so as to be in partial contact with a semiconductor conductive layer of the same type as the layer formed on the surface of the epitaxial layer, and electrodes are formed on the emitter, base, and collector, and an extra kp-n junction is formed outside the intrinsic region. The present invention is characterized by a hetero bipolar transistor t-i in which at least one of the emitter-paste junction and the collector-base junction is a heterojunction.

〔Effect of the invention〕

The heterojunction bipolar transistor manufactured by the method of the present invention has no extra collector-base junction other than the intrinsic region of the transistor, and the ohmic electrode to the emitter can be easily formed in a self-aligned manner, so the device size can be reduced. This allows the characteristics of a heterojunction bipolar transistor to be brought out to the fullest, making it possible to construct an ultra-high-speed switching element.

[Embodiments of the invention]

Figures 1(a) to (f) show the emitter-base junction.
An embodiment of the manufacturing process of a bipolar transistor without an extra base-collector junction according to the present invention using a GaAs/Ga heterojunction is shown. The following explanation will be given based on this figure.

CVD IC Te8i02 on semi-insulating GaAs substrate 21
A film 22 is deposited, holes are opened at desired positions to serve as a mask, and S
An n+ sub-collector region 23 having a depth of about 1 μm is formed by injecting i or 8 nt − ions as shown in No. 111(a). This sub-collector can also be formed by diffusing Si, Sn, etc. Next, after removing the 5i02 film 22 used as a mask and subjecting it to an appropriate surface treatment, MBE is applied to the semi-insulating GaAs substrate 21 to form a 4oooX undoped AJGaAs Ji 24 (AlAs/Ga
As=3/7).

p+ type AlGaAs doped with Be 5X10"m-"
Layer 25 is grown epitaxially as shown in FIG. 1(b). At this time, MOCVD may be used. In addition, the growing shrimp layer is the GJIAS layer, the AIGaAa layer and the Ga km
A combination of layers is also acceptable. Next, on top of this shrimp layer, xsooi's 8i3N4 layer of 26.1μ 8i
The 02 layer 27 is formed using plasma CVD, and a hole is opened up to the surface of the semiconductor substrate 21 using R and IE at a position overlapping a part of the previously formed sub-collector 23 as shown in FIG. 1(C).

At this time, under appropriate gas conditions, etching automatically stops when the semiconductor substrate 21 is exposed. After suitably pretreating the substrate, MBE is used to form an n-type GaAs layer 28 that will become a collector, and a p+-type GaA layer that will become a base.
S layer 29, mouth-shaped AIG layer 31 for emitter, mouth-shaped cap layer 31 for ohmic contact.
Evidentially grow. At this time, an amorphous GaAs layer 32 and an AJGaAs layer 32 are formed on the 8102 layer 32.
The Ga As layer 28, which serves as the collector, has a thickness of 500 mm and is a layer doped with 5×10” sub-3 of 8i. The thickness and doping amount of each layer of the base, Ivy, and cap are respectively xoool, Be 3 x 10”cm-
” , 3QQQ N , 3i as 1×1017 −3,
100OA, St is 2X10"m-". Continued tn-
(On top of this, a KAuGe/Au layer 33 is deposited as shown in FIG. 1(d). Then, after peeling off the 8i02 layer 27 by soaking it in ammonium fluoride, the regions to be the transistor's intrinsic region and external paste region are formed using CaF2/Au. It is covered with an Au layer 34 and used as a mask for implantation.
150 keV, IXIO"~IXIO"cm
-"Ion implantation is performed to make the p+ type AIGaAsMi 25 high in resistance as shown in FIG. After that, the CaF2/U layer 34 is removed by dissolving the CaF2 with dilute hydrochloric acid, and as shown in FIG. 1(f), an ohmic electrode 35 to the base and an ohmic contact 36 to the collector are formed by a well-known method. Finally, the wiring 37t- is completed.

The characteristics of the transistor manufactured using the method of the present invention are excellent, with s hyg': 0:199 or more even in a transistor with an emitter size as small as 2 x 4μ. When I made the oscillator, the 'rpct was very fast, less than 50 ps.

[Brief explanation of drawings]

FIG. 1 is a process sectional view for explaining an embodiment of the present invention, and FIG. 2 is a sectional view for explaining a conventional method for manufacturing a heterojunction bipolar transistor. 21: Semi-insulating 1i GaAs substrate, 22, 27: 8i
02 film, 23: sub-collector region, 24: AI Ga
A s layer, 25: p” type A7!' G a person 3 layer,
26: 8s 3N4 M %28: R-type GaAs
Ji, 29: pJ GaAs layer, 30: Mouth type A
IGa layer 3, 31: Capry layer, 32: Amorphous GaAs, AlGaAs layer, 33: AuGe
/Au layer, 34: CaF2/U layer, 35.36:
Ohmic contact. Representative Patent Attorney Kensuke Norichika (and 1 other person) (α) , Doj tb) <d) Figure 1 (e) Geλ Figure 1 Figure 2

Claims (1)

[Claims] The emitter-base junction, collector
In manufacturing a heterojunction bipolar transistor in which at least one of the base junctions is a heterojunction and there is no collector/base junction other than the transistor's intrinsic part,
A process of forming a part of the collector region in a predetermined region on a semiconductor substrate by ion injection or diffusion, and a process of forming a base from the surface to a required depth using the same semiconductor or a semiconductor with the same lattice constant on this semiconductor substrate. A step of epitaxially growing a conductive layer of the same type, or growing a semiconductor layer of the same type or a semiconductor layer having the same lattice constant on the semiconductor substrate to form a conductive layer of the same type as the base in a required region to a required depth; A step of applying a mask to the epitaxial layer and opening a hole in the epitaxial layer up to the semiconductor substrate, a step of sequentially epitaxially growing a semiconductor layer to become a collector, a base, and an emitter in the opened region, and a step of sequentially growing a semiconductor layer to become a collector, a base, and an emitter in the opened region. 1. A method for manufacturing a heterojunction bipolar transistor, comprising the step of forming an electrode.