JPS61220586A - Storing and reproducing device for video signal - Google Patents

Abstract

PURPOSE:To enable to reproduce a superior still picture with simple constitution by generating a clock signal that is synchronized with a synchronizing signal for re-writing to a memory and reading out information stored at the memory by this clock signal. CONSTITUTION:When the still picture is reproduced, a switch 23 is switched to (b) side and a compound signal that is added to an amplifier 2 is supplied to an LPF3, a synchronization separation circuit 10 and a BPF11. At the LPF3, an unnecessary frequency component of the signal is eliminated and the signal is converted to a digital signal at an A/D converter 4 and is written to a memory 5 by share of one field in order. So that a jitter component is included in the signal written at the memory 5, a synchronizing signal generating circuit 21 is operated and dummy horizontal and vertical synchronizing signals are generated and these dummy signals are to be synchronized with the synchronizing signal that is used for the re-writing of the memory 5. As a result, the superior reproduction of the still picture can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a video signal storage and playback device that performs good still image playback.

(b) Conventional technology In the video signal of the NTSC color television system, the frequency of the color subcarrier is an odd multiple of 1/2 of the horizontal scanning frequency, that is, 455/2 times, and therefore the phase of the color subcarrier is 1 Each horizontal scan is shifted by 180 degrees and reversed, and since the number of horizontal scans in one frame is limited (525 lines), the phase of the color subcarrier at the start point of the adjacent frame is also 180 degrees.
The signals are shifted and reversed, and this has complicated the addressing and signal processing of digital video equipment for the signals.

Here, Japanese Patent Laid-Open No. 19388/1988 discloses a technique for reproducing still images from a composite video signal received by a television receiver, a composite video signal reproduced from a video tape recorder, etc., and is generally described above. When playing back still images, for example, a video signal of the NTSC color television system is converted into a digital signal, one field of the same digital signal is sequentially rewritten, stored and read out in a field memory, and then the digital signal is converted into a digital signal. Still images were played back each time they were converted to an analog signal.

(c) Problems to be Solved by the Invention However, when converting the aforementioned video signal into a digital signal and storing it in the field memo IJK, the signal continued from the field memory will have an even field and an odd field. Since there is a difference of H/2 (H is the horizontal scanning period), the continuity of the horizontal synchronization signal is lost, and on the other hand, there is a 180° phase difference in the color subcarrier between frames, making it impossible to perform complete color reproduction. could not. Therefore, an H/2 delay circuit was used to delay the signal continuing from the field memory by a time of H/2 minutes, and a chroma inverter was used to match the phase of the color subcarrier, but the configuration became complicated. It had some problems, such as:

B) Means for Solving the Problems The present invention has been made to solve the above problems, and its purpose is to perform good still image reproduction with a simple configuration, and converts video signals into digital signals. A/D conversion means for converting the digital signal into an analog signal; a memory means for sequentially rewriting and storing one field of the digital signal and sequentially reading it; and a D/D converter for converting the digital signal output from the memory means into an analog signal.
A conversion means, a synchronization signal separated from the video signal, and a signal that locks to the burst of the video signal and has a frequency that is a predetermined multiple of the color width carrier wave, the phase of which is inverted with respect to the horizontal synchronization signal in the synchronization signal. a clock signal generating means that generates a synchronized clock signal without the need for image processing; and a memory control unit that operates the memory means and sequentially rewrites, stores, and reads one field of the same digital signal using the clock signal during still image reproduction. This is a video signal storage and playback device consisting of:

According to the video signal storage and reproducing device of the present invention, the synchronization signal in the synchronization signal is separated from the video signal, and the signal locks to the burst of the video signal and has a frequency that is a predetermined multiple of the color subcarrier. A clock signal synchronized with the horizontal synchronization signal without inversion in phase is created, and the control output of the memory control unit that operates by inputting the clock signal allows one field of digital signals written in the memory means to be read. It has the effect of allowing good still image reproduction.

(f) Example The details of the present invention will be specifically explained with reference to the illustrated embodiments.

FIG. 1 is a block diagram illustrating the video signal storage and playback device of the present invention, FIG. 2 is a block diagram showing the inside of the clock signal generation circuit of the video signal storage and playback device of the present invention, and FIG.
The timing chart showing the input/output waveforms of each part in Figures and Figure 2, Figure 4 is the timing chart when no clock signal is created.
．． 74 is a timing chart showing 74 MHz and color subcarriers.

To explain the figure numbers and configurations of Figures 1 and 2,
(1) is an input terminal for inputting a composite video signal reproduced from a video tape recorder or received by a television receiver; (2) is an amplifier for amplifying the composite video signal; (3) ) is a low-pass filter, and (4) is an A/V converter that converts the composite video signal passed through the low-pass filter (3) into a digital signal.
D converter (5) is a memo IJ that sequentially rewrites and stores one field of digital signals after A/D conversion and sequentially reads them out.
, (61 is a D/A converter that converts the digital signal output from the memory (5) into an analog signal, (7) is D
(8) is a low-pass filter that removes unnecessary frequency components from the analog signal after A/A conversion and performs analog interpolation; (8) is an amplifier that amplifies the analog signal after passing through the low-pass filter (7); The output terminal (00) outputs the analog signal amplified by the amplifier (8) K as a composite video signal; The circuit 01) is a bandpass filter that passes a 3.58 MHz burst signal from the composite video signal amplified by the amplifier (2), and α is 3.58.
P locking the phase of the 10.74 MHz signal to the phase of the burst signal at MHz, i.e. the phase of the color subcarrier;
LL circuit (13) is the horizontal synchronizing signal and the PLL circuit;
A clock signal generation circuit that generates a 10.74 MHz clock signal from the output of the circuit (12) that is synchronized with the horizontal synchronization signal without phase inversion with respect to I-, and inputs it to input terminal 04)K. The synchronization signal separation circuit θ0
) and a one-shot multi (15) for waveform shaping the output of EXOR circuit 08) that calculates exclusive OR from the output,
A, N that calculates a logical product from the output of the one-shot multi (15) and the inverted output of the EXOR circuit (18);
D circuit (1,9).

An output terminal (
20), (21) is a synchronization signal generation circuit that independently generates horizontal and vertical synchronization signals, (22) is operated by the output of the clock signal generation circuit 03) and the synchronization signal generation circuit 0, and the memory (23) is a switch that switches the composite video signal amplified by the amplifier (2) between still image playback and other modes using a control signal S from the system control. be.

The need for a low-pass filter (3) is that the composite composite video signal has a sampling frequency of 10.7MHz.
If the sampled signal has a frequency component higher than 1/2, overlapping parts will occur in the spectrum of the sampled signal,
This is because aliasing noise will occur in the composite video signal after passing through the low-pass filter (7). Also 1
It is assumed that a frame is composed of two fields of 263 horizontal scans and 262 horizontal scans, and the continuity of the horizontal synchronization signal is maintained.

First, in a mode other than still image playback, the switch (C) is switched to the a side by the control signal S from the system control, and the composite video signal is input to the input terminal (1) and amplified by the amplifier (2). is output from the output terminal (9) via the switch (c).

Next, in the still image playback mode, the switch C3) is switched to the b side by the control signal S from the system control, and the composite video signal input to the input terminal (1) K and amplified by the amplifier (2) is After unnecessary frequency components are removed by a low-pass filter (3) via a switch (23), the signal is converted into a digital signal by an A/D converter (4).

On the other hand, the composite video signal amplified by the amplifier (2) is also input to the synchronizing signal separation circuit 00) and the bandpass filter 01), and here the signal processing in the clock generation circuit (I3) is shown in Figs. 2 and 3. Let's think about using it.

First, the horizontal synchronizing signal shown in FIG. 3(a) is input to the input terminal 04), and the horizontal synchronizing signal shown in FIG. 3) is input to the input terminal 04).
10 locked to the phase of the 58 MHz color subcarrier
．． 7. A MHz signal is input. The horizontal synchronization signal input to the input terminal (14) rises at the rising edge of the horizontal synchronization signal as shown in Figure 3 (b) due to the Funshot Multi α4, and the color subcarrier is detected before the rise of the next horizontal synchronization signal. The waveform is shaped into a signal that falls at a time when continuity is maintained, and then rises at the rising edge of the horizontal synchronization signal, and is converted into a horizontal synchronization signal by the 1/2 frequency divider (16) as shown in Fig. 3H. The waveform is shaped into a signal that rises at the rising edge of , and falls at the rising edge of the next horizontal synchronizing signal. When the signal shown in Fig. 3 (c) is input to the EXOR circuit (country) and calculated, the signal shown in Fig. 3 (e) is output, and the inverted output of Fig. 3 (e) and the signal shown in Fig. 3 (e) are output. When the signal shown in (b) is input to an AND circuit (1) and operated, the signal shown in FIG. 3 (f) is output.

From this, the signal shown in FIG.
221.

As mentioned above, the digital signal after A/D conversion is sampled at the rising edge of the clock signal and sequentially rewritten one field at a time in the memory IJ (51). At this time, the horizontal and vertical synchronization signals after synchronization separation are converted to digital signals. It is synchronized with the horizontal and vertical synchronization signals in the composite video signal,
Further, the synchronization signal generation circuit (21) is not operating. The digital signals that are sequentially rewritten in the memory (5) one field at a time are read out one field at a time, and in particular, the horizontal and vertical synchronization signals after synchronously separating the composite video signal reproduced from the video tape recorder are contains a jitter component, and it is not possible to perform a good readout even if the synchronization signal is used.

Therefore, the synchronization signal generation circuit (21) is operated to create pseudo horizontal and vertical synchronization signals and input them to the memory control unit +22). synchronized to the signal.

The digital signals that are sequentially rewritten in the memory (5) one field at a time are read out at the rising edge of the clock signal, and from this point on, the digital signals are sequentially read out one field at a time. After that, the digital signal is converted to an analog signal by a D/A converter (6), unnecessary frequency components are removed by a low-pass filter (7), and then amplified by an amplifier (8), and a composite image is output from an output terminal (9). Output as a signal.

Next, let's consider color reproduction during still image reproduction.

In Figure 4, O6 is (b) to) (7]'Kl (to) is 3.
A digital signal of a 58 MHz color subcarrier is shown. In addition, (A) (/j each indicates a 10.74 MHz signal locked to the phase of the color subcarrier shown in (B)), both of which correspond to one continuous horizontal scanning period, that is, one continuous frame. This can be considered as one horizontal scanning period for the first grain.

Here, when (a) and (b) are one horizontal scanning period of the first grain of the frame and a still image is played back after scanning one frame, the color subtransport of (b) is sampled with the signal of ←j, and 1) is one horizontal scanning period of the first grain of the frame.
When reproducing a still image after scanning a frame, it is necessary to sample the color subcarriers shown in (a) using the signals in (a), and each of them becomes the color subcarrier shown in (b) and is stored in the memory (5). However, since the clock signal rises at the rising edge of the horizontal synchronization signal, the above-mentioned discontinuity of the color subcarrier does not occur in each field.

(g) Effects of the Invention According to the video signal storage and reproducing device of the present invention, the synchronization signal is separated from the video signal and the signal that locks to the burst of the video signal and has a frequency that is a predetermined multiple of the color subcarrier. A clock signal synchronized with the horizontal synchronization signal in the signal without inversion is created, and the control output of the memory control section that operates by inputting the clock signal allows one field's worth of data written in the memory means to be generated. Since good still image reproduction can be performed using digital signals, advantages such as no need for a complicated configuration can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the video signal storage and playback device of the present invention, FIG. 2 is a block diagram showing the inside of the clock signal generation circuit of the video signal storage and playback device of the present invention, and FIG.
The timing chart showing the input and output waveforms of each part in Figure 2 and Figure 4 is 10.74 when no clock signal is created.
3 is a timing chart showing MHz signals and color subcarriers. Explanation of main figure numbers (4)...A/D converter, (5)...memory,
(6)...D/A converter, 03)...Clock signal generation circuit, (2η...Memory control unit. Author: Sanyo Electric Co., Ltd. and one other representative, patent attorney Shizuo Sano S. 3 S ε S Otsuko 已 ≦ $ t and [su7

Claims (1)

[Claims] (1) A/D conversion means for converting a video signal into a digital signal; a memory means for sequentially rewriting and storing one field of the digital signal; and converting the digital signal output from the memory means into an analog signal; D/A to do
a conversion means, a synchronization signal separated from the video signal, and a signal that locks to the burst of the video signal and has a frequency that is a predetermined multiple of the color subcarrier, the phase of which is inverted with respect to the horizontal synchronization signal in the synchronization signal; a clock signal generating means for generating a synchronized clock signal without any interference, and a memory control section for operating the memory means and sequentially rewriting, storing and reading one field of the same digital signal using the clock signal during still image reproduction. A video signal storage and playback device characterized by: