JPS61220565A - Clamp circuit - Google Patents

Abstract

PURPOSE:To reproduce stably a DC by providing a bias path for a current flowing into a DC stopping capacitor from a load side in order to minimize charges built up in the DC stopping capacitor during non-clamp period. CONSTITUTION:A video signal inputted from a terminal A is amplified by an emitter grounding amplifier 1, and only its AC component is transmitted to a clamp circuit through the DC stopping capacitor 4. When a clamp pulse is not inputted to a terminal B, charges are built up in the DC stopping capacitor 4 through a bypass transistor 11. The discharge is executed by a base current, and therefore its amount comes to an extremely small amount. Then, when the clamp pulse is inputted to the terminal B, a clamp transistor 12 is conducted to interrupt the bypass transistor 11, whereby charges built up during non-clamp period are pulled out of the DC stopping capacitor 4, and a potential at the cathode side of the capacitor 4 equals that of a clamp power source 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a clamp circuit in a video circuit for a television, display, etc., and particularly to a lamp circuit suitable for a large amplitude, wideband video circuit.

[Background of the invention]

A general configuration of a video signal pedestal clamp circuit is shown in Japanese Patent Publication No. 59-55542. This configuration is based on the assumption that a low output impedance circuit is connected to the front stage of the clamp circuit, and a high input impedance circuit is connected to the rear stage, and a high output impedance circuit is connected to the front stage. No consideration was given to cases where

As an example of lowering the output impedance of the amplifier that sends the signal to the clamp circuit and improving the clamp characteristics,
There is a circuit described in [Television Technology, December 1981 issue] K and shown in Figures 5 and 6.

T ) L 705 and 704 in FIG. 5 are constructed of complementary emitter and follower circuits in order to lower the output impedance of the amplifier. In the circuit shown in Fig. 5, at a frequency of about 1-1x to 20MHz,
Although TR705 and TR704 contribute to lowering the output impedance as impedance conversion amplifiers, no consideration was given to the high frequency region where loss increases significantly and impedance change is incomplete.

That is, the impedance of the signal source that sends the <g signal to the clamp circuit becomes high, which is the 9 major reason why the signal level after one signal is clamped is -4111.

[Purpose of the invention]

The purpose of the present invention is to have a low output impedance at the front stage, a relatively low input impedance at the rear stage, and a relatively low circuit configuration.
- To provide a lamp circuit that enables stable DC regeneration.

[Overview of the invention]

A normal synchronous clamp circuit places a low output impedance circuit in front of it to suppress voltage fluctuations caused by the current flowing during clamping. However, in a high output wide band circuit, low output impedance is There is a problem in that it tends to lead to an increase in consumed intelligence and an increase in circuit scale.
When the output impedance of the Fg is high at °C, the charge accumulated in the DC closing capacitor during the non-clamping period is extracted at once during the clamping period, and at that time, it flows and the voltage drop increases, causing normal or lamp operation. deviate from. Therefore,
The present invention is characterized in that the DC blocking capacitor is provided with a bypass path for current flowing into the DC blocking capacitor from the load side in order to reduce as much as possible the charge accumulated in the free current blocking capacitor during the non-clamping period. Ru.

[Embodiments of the invention]

FIG. 1 is a diagram showing the principle of the present invention. 1 is a circuit before the clamp circuit, and is a voltage source with an output impedance r. 2
is the load of the clamp circuit, that is, the next stage circuit, through which the load current 11 flows according to the input Machida. 5 is a current bypass circuit, 4 is a DC blocking capacitor, 5 is a clamp voltage source, and 6 is a synchronous switch. When a signal is output from the @stage circuit 1, only its AC component is transmitted to the clamp circuit via the DC blocking capacitor 4. In the clamp circuit, the synchronous switch 6 is periodically closed, and a DC potential is applied to No. 15 by the clamp voltage source 5. While the synchronous switch 6 is open, current flows from the next stage circuit 2 to the clamp circuit or from the clamp circuit to the next stage circuit 2. Since the principles are the same, only the case where current flows from the next stage circuit 2 to the clamp circuit will be described below. Further, as a condition in this case, the clamp potential is higher than the DC output potential of the front stage circuit 1. When a current flows into the clamp circuit from the next-stage circuit 2, the current bypass circuit 5 draws the current from the clamp circuit to the previous-stage circuit 1 in accordance with the current flow. The current flowing from the next stage circuit 2 is tl, the current bypass circuit 18
If the current drawn to the preceding stage circuit 1 by 5 is 12, it is assumed that i, ≦12 is satisfied. At this time, a current (iltz) flows into the DC blocking capacitor 4 and charges are accumulated. Next, when the synchronous switch 6 is closed, the charge accumulated in the DC blocking capacitor 4 during the period when the synchronous switch 6 is open, that is, the non-clamping period, is extracted at once.
DC regeneration is performed by the clamp voltage source 5. Here, the end time of a certain clamp is 01, and the start time of the next clamp is 1. , the next clamp end time is t2, and the current drawn from the DC blocking capacitor 4 during the clamp period (clamp current) is i3, then the following formula ht is established.
Sdt and therefore the average t! of the clamp current i1! is given by Is −, ', 0o(il-12)'',
The average voltage drop ΔV during the clamp period due to the output impedance j1° of the front-stage circuit 1 is O = r = t, "-t, Oo""-"dt.

becomes. This voltage drop interferes with faithful lamp operation, so it is desirable to keep it as small as possible.

Therefore, if the setting is made so that i2 and i1, Δυ is set to 0, and a stable clamping operation can be performed. In addition, the effects of the output impedance of the front-stage circuit 1, the input impedance of the rear-stage circuit 20, and the clamp period are also reduced. 2nd 1
(a) is a diagram showing an example of the waveform of clamped t or Shingetsu, (
hl is a diagram showing the waveform of the clamp pulse. When the clamp pulse is manually applied, the synchronous switch 6 closes and the clamp it
, DC regeneration is performed by the IF source 5. Figure 2 (a
) is caused by the voltage drop caused by the output impedance of the preceding stage circuit 1, which causes a depression j in the signal waveform during the clamp period.

An embodiment of the invention in the output stage of a CRT display video circuit is shown in FIG. Resistor 7, transistor 8
, a resistor 9 constitutes a common emitter amplifier, and corresponds to the front-stage circuit 1 in FIG.

10 is a cathode of CR'l', which corresponds to the next stage circuit 2 in FIG. Further, 11 is a bypass transistor, and 12 is a clamp transistor, each of which is connected to the current bypass circuit F8 in FIG.
5. Synchronous switch 61C equivalent 1-ru. Other signals are the same as in FIG. A video signal inputted from a terminal A is amplified by a common emitter amplifier 1, and only its alternating current component is transmitted to a clamp circuit via a direct current closing capacitor 4.

Therefore, the DC component is regenerated using a synchronous clamp, and the cathode 1
This is a circuit that drives 0. The operation will be explained in detail below. First, when no clamp pulse is input to the terminal B, that is, during the display period of the C1T display, a cathode current flows and charges are accumulated in the DC blocking capacitor 4 via the bypass transistor 11.

However, since it is charged by the base current of the bypass transistor 110, if the current amplification factor of the bypass transistor 11 is hf·, the charging current of the DC blocking capacitor 4 is /(1□person, 1) times the cathode current, The remainder is bypassed to the common emitter amplifier 1 in the previous stage. Therefore,
If A/, is sufficiently large .degree. C., the DC blocking capacitor 4 is hardly charged during the non-clamping period. Next, terminal B
When the K clamp pulse is input, the clamp transistor 12 becomes conductive, the charge accumulated in the non-clamp period is extracted from the DC blocking capacitor 4, and the potential on the cathode side of the DC blocking capacitor 40 becomes the potential of the clamp voltage source 5. is approximately equal to . Here, if the clamp current that flows when the charge is extracted from the DC blocking capacitor 4 by the clamp transistor 12 is large, the clamp current is considered to flow in an alternating current manner through the output impedance of the front stage circuit 1, that is, the load resistor 9, so that the output The impedance causes a voltage drop, making it impossible for the lamp to operate normally.

However, as mentioned above, in the circuit of FIG. 5, not much charge is accumulated in the DC blocking capacitor 4 during the non-clamping period. Therefore, the clamp current that flows during the clamp period is small (and therefore, the voltage drop due to the output impedance of the previous stage is also small, and normal lamp operation can be performed.Furthermore, according to the circuit shown in Fig. 5, during the non-clamp period Since the DC blocking capacitor 4 is hardly charged, it is stable against sag and potential fluctuations during the vertical blanking period.In the circuit shown in Figure 5, the potential of the clamp voltage source 5 is It is assumed that the collector potential of transistor 8 is higher than that of transistor 8 at that time.

FIG. 4 shows an improved embodiment of the circuit shown in FIG. 1st
The difference is that a parallel K, 7F, 7, and 14 are inserted between the base and emitter of the bypass transistor H, which prevents deterioration of the frequency characteristics. In the circuit shown in Figure 5, when the cathode current is small, the base-emitter resistance of bypass transistor 1 is extremely large;
A low-pass filter is used along with the capacitance of the cathode terminal IO.
Due to this configuration, the high frequency characteristics deteriorated, causing the signal waveform to become blunt. Therefore, as shown in FIG. 4, by inserting a capacitor 14 between the base and emitter of the bypass transistor 1, the extra frequency is bypassed and the signal waveform is improved. The second difference is that the cathode is connected to a sufficiently high voltage source through a resistor 15 so that the cathode potential is fixed even when no cathode current flows.Diode +5 is used to prevent backflow and connect the cathode terminal 1
It was inserted to reduce the capacitance attached in parallel with 0. The other operations are the same as those of the circuit shown in FIG. 5, so the explanation will be omitted here.

FIG. 5 shows the final stage of the video circuit of the same (CR1' display), and is a diagram showing an example in which a current mirror is used in current bypass circuits 5 and 1. Bypass transistor 11 and diode +6 are current bypass circuits 5 and 1. Since the mirror is configured, the cathode current is divided into a current flowing into the DC closing capacitor 4 and a current flowing into the front stage circuit 1 via the bypass transistor 11.The division ratio is determined by the resistors 17 and 18. Therefore, if the value of resistor +8 is set sufficiently small, most of the cathode current will be bypassed to M-stage circuit 1 via resistor 18 and transistor 1, and [B current blocking capacitor +4 will be mostly charged. Here, the characteristics of the diode 16 are compensated by connecting a transistor with almost the same characteristics as the bypass transistor 11 in a diode connection.
4 is to prevent the signal waveform from becoming dull, and the same effect can be obtained by inserting it between the base and emitter of the bypass transistor 110 or between the base and cathode 10 of the bypass transistor 110. . In addition, in the insertion method as shown in FIG. 5, the value of the resistor 17 cannot be made very large because the high frequency characteristics will deteriorate.

Figure 6 shows the circuit of Figure 5 with a current mirror 2
7 is a diagram illustrating an embodiment in which a stage configuration is used and all cathode current is bypassed to the previous stage circuit 1. FIG.

Bypass transistor 11, diode +6, resistor 17
, the resistor 18 constitutes a first current mirror, and the transistor 21, the diode 19, the resistor i2o, and the resistor 22 constitute the second current mirror. Bypass transistor RO and diode 16, transistor 21 and diode 1
No. 9 uses transistors each having almost the same characteristics to compensate for the characteristics. Further, the resistor 17 and the resistor +8, and the resistor 20 and the resistor 21 are assumed to have the same resistance value. The cathode current is divided by the first current mirror in the inverse ratio of resistor 17 and resistor 18.

Since the resistance value of the resistor +7 and the resistance value of the resistor 1 are equal, the cathode current is divided into two parts, one of which flows to the DC blocking capacitor 4, and the other to the previous stage circuit 1 via the second current mirror diode 19. In the current mirror circuit, the resistance values of the resistors 20 and 22 are equal, so the diode 19
A current equal to the current flowing through the DC blocking capacitor 4 is drawn from the DC blocking capacitor 4. In other words, a current equal to the current injected by the first current mirror is transmitted by the second current mirror,
It will be pulled out from the DC blocking capacitor 4, and the DC blocking capacitor 4 will not be charged. Note that in the circuit shown in Figure 6, the sum of the currents drawn by the current mirror is the cathode 1! It is necessary to design so as not to exceed i-style. This is because if it exceeds 1,000,000, the cathode potential will continue to fall automatically due to a vicious cycle in which the cathode potential decreases, the cathode current increases, and the cathode potential further decreases.

Since the charge accumulated on the DC blocking capacitor 4 is almost 0, there is no voltage drop due to the output impedance of the common emitter amplifier 1 in the preceding stage, and stable clamping operation is exhibited.

FIG. 7 is a diagram showing an embodiment of a clamp circuit in which emitter followers are arranged at the front stage and the rear stage.

Transistor 24 and resistor 25, transistor 26 and resistor 1
2 - The resistors 25 each constitute an emitter follower, and each resistor 25 constitutes a first emitter follower.
This corresponds to the first stage circuit 1 and the next stage circuit 2 in the figure.

The operation will be briefly explained below. The circuits shown in FIGS. 5 and 6 differ from each other in that the transistor 26 and the resistor 2 are
An emitter follower 20 input current consisting of 5 is drawn from the clamp circuit, but by a bypass transistor 11.
Most of it is directly supplied from the preceding stage circuit 1, and only a small amount is supplied from the DC blocking capacitor 4. Therefore, during the clamp period, the clamp transistor 12 and the diode! Even if charge is injected from the clamp voltage source 5 via the clamp voltage source 5, the amount of clamp current flowing at that time is small, and the influence of voltage drop due to the output impedance of the preceding stage circuit 1 is also small. Normally, in the configuration shown in FIG. 7, the input impedance of the next stage circuit 2 is large and the output impedance of the previous stage circuit 1 is small. The circuit of the present invention is effective when used in a high frequency range and in a high frequency region, since this increases power consumption and requires a sufficient reduction in the output impedance of the front-stage circuit 1. It should be noted that in the cycle shown in Fig. 7, '-M f is a clamp π (the Kawahara 50 potential is smaller than the previous stage output v1 current I1'!).

FIG. 8 is a diagram showing an actual example of a clamp waveform of a conventional clamp circuit, in which a 20V η1 ratio drop is observed during clamping.

FIG. 9 is a diagram showing a single clamp waveform using the same circuit as FIG. 8 but improved by the method shown in FIG. 4. Voltage drop during clamping which was about 20V in Figure 8/115~5■
[Effects of the Invention] According to the present invention, by adding at least one transistor and one capacitor to the conventional clamp circuit, the DC blocking capacitor can be reduced to a certain extent. This not only suppresses charging and suppresses voltage level fluctuations during clamping, but also improves sag characteristics, making stable DC regeneration possible. Furthermore, power consumption can be reduced compared to the case where a low output impedance circuit is inserted before the clamp circuit.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a waveform diagram showing a clamped signal waveform and clamp pulse, Fig. 5 is a circuit diagram showing the most basic embodiment of the invention, Fig. 4 is Figure 5 is a circuit diagram showing an example of an improved high-frequency custom order. A circuit diagram showing,
FIG. 7 is a circuit diagram showing an embodiment using a PNP type clamp transistor, FIG. 8 is a waveform diagram showing a clamp waveform of a conventional circuit, and FIG. 9 is a clamp waveform of the circuit of the present invention shown in FIG. 4. FIG. 1... Pre-stage circuit 2... Next-stage circuit 5... Current bypass circuit 4... DC blocking capacitor 5... Clamp voltage source No. 7 Fig. 5P^/d iV No. cl Fig. s/Ns/drv Procedural amendment (spontaneous) Indication of the case 1932 patent application No. 60570 Title of the invention
11 people who correct the clamp circuit 1! Patent Applicant Name WF 15+01 Co., Ltd. 1F Manufactured by Hitachi Manufactured by Agent Agent Subject of amendment Contents of amendment in the detailed explanation of the invention in the specification 2
is the load of the clamp circuit, that is, the next stage circuit, Jk12
is the next-stage circuit.'' 2. The "clamp circuit" described in line 4 @ line 17 and lines 17 to 18 of the specification is corrected to "next stage circuit 2."& The "clamp circuit" described in page 5, line 581, line 1g, line 2, line 4, and line 7 of the specification is replaced by "DC blocking contin '9'.
4”. 4. "Clamp circuit" described on page 5, line 9 of the specification
is corrected as "next stage circuit 2". 5. "L+≦Lt" stated in page 5, line g13 of the specification is corrected to [L2≦L+J. & [Clamp circuit] described on page 7, line 20 of the specification
τ is corrected as “cathode 10”. l Correct the statement "DC blocking capacitor 4" written on page 8, line 16 of the Akira #JJU book to read "From the DC blocking capacitor 4."that's all

Claims (1)

[Claims] In a synchronous clamp circuit, the signal transmission path is separated by a DC blocking capacitor, and a low impedance voltage source is connected to the output terminal of the capacitor via a switch that periodically conducts for a certain period of time. A clamp circuit characterized in that a bypass path is provided for the current flowing into the transmission side through the capacitor, or the current flowing from the transmission side to the output side load through the DC blocking capacitor, and charging and discharging of the DC blocking capacitor due to the current is suppressed. .