JPS61220476A - Schottky gate type field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To make mutual conductance high, by laminating a low resistance GaAs layer and a high resistance GaAs layer on a high resistance AlGaAs layer in this sequence, and forming a Schottky gate electrode on the surface. CONSTITUTION:On a semi-insulating GaAs substrate 11, a high resistance AlGaAs layer 12, a low resistance GaAs operating channel layer 13 and a high resistance GaAs surface layer 14 are sequentially grown as crystals and laminated. A Schottky gate electrode 15 comprising a high heat resisting metal is formed on the layer 14. In this constitution, high concentration electrons in the layer 13 can be confined in the layer by utilizing the heterojunction of GaAs/AlGaAs. A high Schottky barrier can be maintained by inserting the layer 14 beneath the electrode 15. Thus the high performance Schottky gate type FET having excellent gate characteristics and high mutual conductance can be implemented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a Schottky gate field effect transistor using GaAs and a method for manufacturing the same.

[Technical background of the invention and its problems]

In compound semiconductors such as GaAs, electrons can travel with higher mobility and saturation speed than in 3i.

For this reason, Schottky gate field effect transistors (MESFETs) using GaAs are
They have superior high frequency characteristics compared to ESFETs or MOSFETs, and are gaining an important position in the fields of microwave devices and high-speed logic devices. Recently, molecular beam epitaxy (MB)
With advances in crystal growth techniques such as the E) method and metal organic chemical vapor deposition (MOCVD) method, new MESFETs that apply heterojunctions are being developed.

In this new device, two-dimensional ions occur at the heterojunction interface consisting of an impurity-doped semiconductor with low electron affinity and a substantially impurity-free semiconductor with high electron affinity.
A dimensional electron storage layer is used as a conductive channel.

Such MESFETs are called high electron mobility transistors (HEMTs).
), modulation doped FET (MODFET), selectively doped FET (SDFET>, two-dimensional electron gas FET
(TEGFET). Hereinafter, these new MESFETs will be represented by the name HEMT, and these are expected to provide better high frequency characteristics than ordinary MESFETs.

On the other hand, according to the studies of the present inventors, ordinary MESFET
Conventional device structures do not necessarily take full advantage of the characteristics of compound semiconductors, which limits device characteristics. This will be explained in detail below.

FIG. 3 shows the basic structure of a conventional GaAs-MESFET. Reference numeral 21 denotes a semi-insulating GaAs substrate, on which an n-type GaAs operating channel layer 22 is formed, and a Schottky gate electrode is formed on the surface of this operating channel layer 22. 23 is formed. 24 and 25 are source and drain ohmic electrodes. In such a MESFET, when the gate length becomes short, the traveling speed of electrons at the gate end becomes saturated, causing current saturation. The mutual fundance (Ql), which is an important parameter indicating the device characteristics of such a MESFET, is expressed by the following formula (%) where 2 is the gate width, Vs is the saturation velocity of electrons, ε is the dielectric constant of the semiconductor, and W (Va) is the width of the depletion layer under the gate electrode when the gate voltage Va is applied as shown in FIG. Normally-off MESF is important as a logic element
Considering ET, the thickness d1 and impurity concentration No of the operational channel layer are determined by the following equation.

(q/2ε)ND-dt-φB...(2) However,
φB is the height of the Schottky barrier of the gate electrode, and q is the absolute value of the electron charge. V with normally-off MESFET
a-077) In case (7) Ql C, W in equation (1) is (2
) can be obtained by substituting d in the equation.

That is, gm-z-vs/Ziτfu2$a...(3)(3)
As is clear from the equation, gl is proportional to ND raised to the 1×2 power.

Figure 5 shows I X 10' a/sea as ■8,
and g assuming 2 x 10' aA/sec
It shows the relationship between - and No. The solid line is the theoretical value, and the black circle is the experimentally reported result. The experimental results are in good agreement assuming Vs -2X 10' a/sec.

Fig. 3 shows the basic structure of the HEMT, in which 31 is a high-resistance GaAs layer that does not substantially contain impurities, 32 is an n-type AβGaAs layer doped with impurities, 33 is a Schottky gate electrode, 34. 35 are source and drain ohmic electrodes. 36 and 37 are low resistance layers of the source and drain.

For such a HEMT, Ql is approximately given by the following equation.

gi -z -VB -ε/d...(4
) Here, d is n-type AnGaAs as shown in FIG.
This is the thickness of layer 32. Considering a normally-off HEMT, if the relationship between gs and the impurity layer temperature 2 of the AlGaAs layer 32 is determined in the same way as in a normal MESFET, it will be as shown by the broken line in FIG.

In the second figure, the Q■ of HEMT obtained in experiments is shown by the glancing angle and white square marks. For HEMT, Vs =
Normal MESF assuming I x 10' a/sec
Only Ql that is on the straight line of ET or smaller than it has been obtained. Possible reasons for this include the effect of parasitic resistance, the current flowing around to the substrate side, and the like.

It is clear from FIG. 5 that the Ql of a normal MESFET can be made much higher than the current level by increasing the impurity concentration of the operating channel layer.
This means that it reaches a value higher than expected for MT. Furthermore, a high Ql is also important for high frequency characteristics, as will be described later, and therefore indicates that it is possible to obtain a MESFET with characteristics superior to those of a HEMT.

However, in a normal MESFET, if an attempt is made to increase the impurity concentration of the operating channel layer while maintaining the conventional device structure, two problems arise. One problem is that when the active channel layer is made sufficiently thin in order to set the threshold voltage of the device to an appropriate value, electrons within the active channel layer seep out to the substrate side by diffusion. This effectively lowers the carrier concentration in the active channel layer, which becomes an obstacle to increasing Q- to a sufficiently large value. Another problem is that when the impurity concentration of the active channel layer is increased, the breakdown voltage of the Schottky gate electrode formed thereon is lowered, and the leakage current of the gate electrode is increased.

That is, it is known that when a Schottky gate electrode is formed in a GaAs layer with a high impurity concentration, the height of the barrier decreases due to the Schottky effect. According to this effect, the decrease in barrier height Δφ is Δφ−−T7Iτ
... is given by (5). Here, E is a Schottky electric field, and the maximum value of E in the MESFET increases in proportion to the impurity concentration No. This reduction in the height of the barrier increases the gate leakage current and reduces the logic amplitude in the logic element.

[Purpose of the invention]

The present invention solves the above-mentioned problems and makes the conventional MESFET
A new GaAs-ME exhibiting much superior performance compared to
The present invention aims to provide a structure of an SFET and a method for manufacturing the same.

[Summary of the invention]

G a As - M E S F E according to the present invention
T G; t, low resistance Ga heavily doped with impurities
One feature is that the As-operated channel layer has a structure in which a high-resistance AffiGaAs layer is laminated thereon as a buffer layer. As such a structure, GaAs/A
The barrier on the conduction band associated with the nGaAs heterojunction is used to confine electrons in the low resistance GaAs active channel layer. Another feature is that a Schottky gate electrode is formed on a low-resistance GaAs operating channel layer via a high-resistance GaA3 surface layer to prevent a reduction in the height of the Schottky barrier. As described later, low resistance GaA
s operating channel layer has carrier concentration lx10''/lx,
31X, and the high resistance GaAs surface layer has a carrier concentration of 1.
It is preferable that X 10''/ax3 or less.

The characteristics of the MESFET of the present invention can be further improved by providing a low resistance GaAs contact layer in a portion other than the gate electrode portion.

As is well known, a depletion layer is formed on the surface of the n-type GaAs layer due to the surface unit. This depletion layer increases parasitic resistance between the source and gate, impairing device characteristics. This parasitic resistance effect can be eliminated by providing a low resistance GaAs contact layer in a portion other than the gate electrode portion.

The method for manufacturing MESFET according to the present invention is based on semi-insulating Ga
After crystal-growing a high-resistance AaGaAs layer, a low-resistance GaAs operating channel layer, and a high-resistance GaAs surface layer in sequence on an As substrate, and forming a Schottky gate electrode made of a highly heat-resistant metal on the high-resistance GaAs surface layer, a gate electrode portion is formed. It is characterized in that a low resistance GaAs contact layer is selectively grown in other parts. In this case, in the crystal growth process,
It is necessary to make the heterojunction interface between the AffiGaAs layer and the GaAs layer steep, and to precisely control the thickness and impurity concentration of the low resistance GaAs operating channel layer and the high resistance GaAs surface layer. The MBE method or the MOCVD method is effective as a method that satisfies such requirements.

〔Effect of the invention〕

According to the invention, G a A S / A 42 G
The high concentration of electrons in the low-resistance GaAs operating channel layer can be confined within the a A S heterojunction, and a high Schottky barrier can be created by inserting a high-resistance GaAs surface layer under the gate electrode. Therefore, it is possible to realize a high-performance MESFET with high gm while maintaining good gate characteristics.

The MESFET according to the invention exhibits advantages particularly when used in logic elements. The cutoff frequency fT, which is one indicator of the high-speed operation characteristics of an element, is fr-g1/2πCg
s ... is given by (6), but using equation (1) with Ql, the gate input capacitance CgS is C0) - ε g/W ... (7)
Considering that, ft=ZVs/27(Lg-(8)).

However, Lg is the gate length. From equation (8), the cutoff frequency fT does not depend on the element structure unless the factor of Z/LO is removed. However, as a result of the presence of parasitic capacitance in an actual device, fT is lower than in equation (8). In this case, CgS
Even if Ql is large, the decrease in fT can be suppressed to a low level if Ql is large.

Since parasitic capacitance is large in logic circuits, elements with high gi are required. From this point of view, the advantages of the device of the present invention can be particularly fully utilized by configuring the device as a normally-off type suitable for a logic device.

As described above, the MESFET of the present invention is expected to have higher performance than the 1-IEMT, and is promising as various logic elements and microwave elements.

Furthermore, according to the method of the present invention, MOCVD or MBE
Using this method, a high-performance ~IESFET with good controllability can be realized. In particular, the MESFET of the present invention uses low resistance GaA
A high-resistance GaAs surface layer is provided on the surface of the s-operation channel layer, but after a Schottky gate electrode is formed on this surface layer, a low-resistance GaAs contact layer is selectively grown in the area other than the gate electrode. According to
A MESFET with small parasitic resistance effects can be obtained.

[Embodiments of the invention]

The present invention will be explained in detail below.

FIG. 1 shows the MESFET structure of one embodiment. To explain this according to the manufacturing process, first, semi-insulating G
High resistance AflG as a buffer layer on the aAs substrate 11
aAs layer 12, then low resistance GaAs working channel layer 1
3. The high-resistance GaAs surface layer 14 is sequentially formed using the MB2 method or M
Lamination is formed by OCVD method. These methods are used as crystal growth methods for AffGaAsll 2 and G
In order to make the aAs operation channel interlayer interlayer 3 steep, and the GaAs operation channel interlayer 3A3
This is to strictly control the thickness of the surface layer 14. High resistance, impurity concentration (carrier concentration) of 12GaAs layer 12 N
Ds, thickness J2s, and impurity concentration of channel 1113 (
Carrier concentration) No^ and thickness 2c are designed to satisfy the following formula.

Here, VTR is the threshold voltage of the element, and Ec is the maximum surface electric field within a range where the characteristics of the Schottky gate do not deteriorate. Ql when the gate voltage is zero is given by: Ec
The value of is considered to be about 5X10' V//II, so
Using this value, VTH-OV, J2 in case of No5-0
kO and Q when the minimum value of g, j2a is set to the minimum value
Calculating - results in the following table.

If Non is less than 1×101 days/3 carbon chips, the Schottky interface electric field will not reach Ec (b) even if there is no surface high resistance layer. Therefore, the structure of the present invention truly exhibits its effect when NDs is 1X101"/cm3 or more. The concentration Nos of the surface high resistance layer indicates that this layer is for weakening the surface electric field. Considering this, it is desirable that it is sufficiently smaller than No^.

However, when actually estimated using equations (9) to (11), it can be confirmed that if No. 11 is 1×10''/ag+3 or less, the device characteristics will not be significantly impaired.

It is possible to make the value of βB larger than in the previous table. In this case, although the margin of gate characteristics increases, Ql decreases and parasitic resistance between the source and the gate and between the gate and the drain may increase. Taking into account that electrons leak from the low resistance GaAs layer into the surface high resistance layer under the source and drain electrodes, the value of λB is 30
If the number of people is about 0 or less, the resistance value will be sufficiently small. In addition, for normally-on type elements, since the surface electric field becomes high, the thickness of the surface high resistance layer needs to be thicker than 8 as shown in the table above.In this case, the parasitic resistance Considering the trade-off between characteristic deterioration due to an increase in impurity concentration and characteristic improvement due to an increase in the impurity concentration of the operating channel layer,
It is also possible to set βB for up to about 500 people.

Next, a Schottky gate electrode 15 made of a highly heat-resistant metal such as tungsten or tungsten silicide.
is selectively formed on the high resistance GaAs surface layer 14. Next, low resistance GaA is formed by MBE method or MOCVD method.
An s-contact layer 16 is formed. In this case gate electrode 1
No single crystal grows on the high resistance GaAs polycrystalline layer 1.
7 is formed, and a low resistance GaAs contact 116 is selectively grown in a portion other than the gate electrode 15 area. It is known that the GaAs polycrystalline layer 17 on the gate electrode 15 has a sufficiently high resistance, and can be used as a source.

Isolation between drains is ensured. Finally, AuG
The device is completed by forming a source electrode 18 and a drain electrode 19 on the GaAs contact layer 16 using an e-based metal, and performing heat treatment to improve ohmic contact.

In the above manufacturing process, it is effective to use MBE method and MOCVD method properly. That is, the AffiGaAs layer 12 and the GaAs surface layer 14 on the GaAs active channel layer are formed by the MBE method, which allows easy control of composition and film thickness, and the GaAs contact layer 16 is formed by the MOCVD method, which allows selective growth to be relatively easy. It is preferable.

In the MESFET according to this embodiment, electrons, which are high concentration carriers in the low resistance GaAs operating channel 1I113, are
The IGaAs/GaAs heterojunction effectively confines it within the working channel 1113. The effect of this electron confinement will be explained using FIG. 2.

In FIG. 2, the G a As operating channel layer is
It is assumed that the active channel layer is doped to 2X 10"/cm3 and formed between -500 and 0. In A of the figure, this operational channel layer is doped to 1X 10"/cm' and is formed as a high-resistance p-type A2.゜-3Ga0ff This is the case where it is formed on the AS layer, and corresponds to the above embodiment. B, C
, D, and E are cases in which a similar operating channel layer is formed on a p-type GaAs layer, and the concentrations of the p-type GaAs layer are lX10''/as3 and 1X10''/ax3゜1, respectively.
X10111/cm3.1X10"'/cm" (
7) It is a case. In this way, when a GaAs active channel layer is formed on an AlGaAs layer, electrons are extremely effectively confined in the active channel layer, whereas GaAs
When formed on an As layer, a "sag" occurs in the electron distribution in the active channel layer, and electrons seep into the p-type GaAs layer. In the structure of the present invention, as shown above, GaA
Since the thickness of the s-operation channel layer is within a practical allowable range of several tens to 300 layers, the impurity concentration of the p-type GaAs layer is appropriately designed to suppress electron seepage, for example, as shown in Fig. 3. Even if track IIC is selected, the decrease in the electron concentration in the operating channel layer significantly affects the device characteristics and causes a decrease in gm. That is, according to the present invention, a MESFET with a high gl can be obtained by using a high resistance AJ2GaAs layer as a buffer layer and forming a low resistance GaAs operating layer thereon.
will be obtained.

Furthermore, according to the above embodiment, although the operating channel layer has a low resistance, the gate electrode is formed on it through a thin high resistance GaAs surface layer, so that sufficient Schottky barrier properties are obtained. maintained. Furthermore, in this case, by providing a low resistance GaAs contact layer in the source and drain regions, an increase in parasitic resistance can be effectively suppressed.

Further, according to the method of the above embodiment, the low resistance GaAs contact layer 16 is formed in a self-aligned manner with the gate electrode 15, thereby making it possible to sufficiently reduce the parasitic resistance between the source and the gate and between the drain and the gate. can do. Moreover, in this case, the polycrystalline Ga on the gate electrode 11115
The As layer 17 has a sufficiently high resistance, and even if it is left as is, an increase in leakage current between the source and drain can be prevented.

Note that the present invention is not limited to the above embodiments. For example, in the embodiments, description has been given mainly of a normally-off type MESFET, but the structure of the present invention can be similarly applied to a normally-on type MESFET. In that case, by optimally designing the impurity concentration and thickness of the GaAs active channel layer, the desired threshold and g
e can be obtained.

In addition, the portion of the AaGaAs layer that is the buffer layer is made of GaAs.
It is also possible to have a superlattice structure of and AffiAS.

In this case as well, the superlattice structure buffer layer functions to confine the electrons of the active channel layer therein. Furthermore, if a buffer layer with a superlattice structure is used, Ga
The effect of improving the film quality of the As layer and increasing the reliability of the device can also be expected.

Furthermore, in order to obtain the structure of the present invention, before forming the gate electrode, a low resistance GaAs contact layer is grown on the entire surface, and only the gate electrode formation area is removed by an etching process to form a recess structure, and the gate electrode is formed in this area. It is also possible to use a method of forming.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a MESFET structure according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the electron confinement effect by the Aj & GaAs layer, and FIG. 3 is a diagram showing the basic structure of a conventional MESFET. 4
The figure shows the basic structure of HEMT, and Figure 5 shows MESFE.
FIG. 3 is a diagram showing a comparison of the characteristics of T-type EMT using theoretical values and experimental values. 11...Semi-insulating GaAs substrate, 12...High resistance/! IF! GaAs layer (buffer layer)
, 13...Low resistance GaAs operating channel layer, 14...
- High resistance GaAs surface layer, 15... Schottky gate electrode, 16... Low resistance GaAs contact layer, 17
...GaAs polycrystalline layer, 18...source electrode, 19
...Drain electrode. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Diagnosis flifllL (A'') 1. Indication of the case ' - 1. Patent application 2 filed on March 27, 1985, Title of invention: Schottky gate field effect Transistor and its manufacturing method 3. Relationship with the person making the amendment Patent applicant Fumio Hase (one idiot) 4. Agent 17 Mori Building/i, 1-26-5 Toranomon, Minato-ku, Tokyo 105 Episode 11 03 (502) 3181 (Major Representative) (Zo: (5847) Patent Attorney Takeshi Suzue
Contents of Hikotan 7° correction (1) “Impurity concentration N” in page 9, lines 5 to 6 of the specification
"proportional to o" is changed to "If the threshold voltage of the element is kept constant, the impurity concentration N
Proportional to o to the 1/2 power.'' (2) "High resistance/1 GaAs layer 12" on page 14, line 10 is corrected to "high resistance GaAs surface layer 14."

Claims (7)

[Claims] (1) A Schottky characterized in that a low resistance GaAs operating channel layer and a high resistance GaAs surface layer are laminated in this order on a high resistance AlGaAs layer, and a Schottky gate electrode is formed on the high resistance GaAs surface layer. Gated field effect transistor. (2) The low resistance GaAs operating channel layer has a carrier concentration of 1×10^1^8/cm^3 or more, and the high resistance GaAs surface layer has a carrier concentration of 1×10^1^7/cm^3 or less. A Schottky gate field effect transistor according to claim 1. (3) The Schottky gate field effect transistor according to claim 1, wherein the Schottky gate electrode is made of a highly heat-resistant metal. (4) The Schottky gate field effect transistor according to claim 1, further comprising a low resistance GaAs contact layer on the high resistance GaAs surface layer other than the Schottky gate electrode portion. (5) The Schottky gate type according to claim 1, wherein the carrier concentration and thickness of the low resistance GaAs operating channel layer are set so that it is completely depleted when no gate voltage is applied. Field effect transistor. (6) crystal-growing a high-resistance AlGaAs layer, a low-resistance GaAs operating channel layer, and a high-resistance GaAs surface layer in this order on a semi-insulating GaAs substrate;
forming a Schottky gate electrode made of a highly heat-resistant metal on the high-resistance GaAs surface layer; and selectively growing a low-resistance GaAs contact layer on the high-resistance GaAs surface layer other than the Schottky gate electrode portion. A method for manufacturing a Schottky gate field effect transistor, comprising the steps of: (7) The high-resistance AlGaAs layer, the low-resistance GaAs operating channel layer, and the high-resistance GaAs surface layer are grown by molecular beam epitaxy, and the low-resistance GaAs
7. The method of manufacturing a Schottky gate field effect transistor according to claim 6, wherein the s-contact layer is grown by metal organic vapor phase epitaxy.