JPS61220432A - Etching method - Google Patents

Etching method

Info

Publication number
JPS61220432A
JPS61220432A JP6066385A JP6066385A JPS61220432A JP S61220432 A JPS61220432 A JP S61220432A JP 6066385 A JP6066385 A JP 6066385A JP 6066385 A JP6066385 A JP 6066385A JP S61220432 A JPS61220432 A JP S61220432A
Authority
JP
Japan
Prior art keywords
mask
etching
polysilicon
gas pressure
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6066385A
Other languages
Japanese (ja)
Inventor
Sadayuki Okudaira
奥平 定之
Shigeru Nishimatsu
西松 茂
Takeshi Ninomiya
健 二宮
Ryoji Hamazaki
浜崎 良二
Shinichi Taji
新一 田地
Kazunori Tsujimoto
和典 辻本
Kiichiro Mukai
向 喜一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6066385A priority Critical patent/JPS61220432A/en
Publication of JPS61220432A publication Critical patent/JPS61220432A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To regulate the cross sectional etching shape and to prevent the pattern dimension from decreasing due to the side face etching, by providing with a mask with given openings on silicon or polysilicon, and by plasma-treating it in SF6+NH3 to form selectively a coating on the mask. CONSTITUTION:On polysilicon 3 lying on SiO2 5, a photo resist mask 1 is formed. At this time, in an atmosphere in which NH3 over 0.06 Pa is added into SF6 of 0.1 Pa, microwave plasma etching in magnetic field forms the new mask 1 on the mask 2 without removing the polysilicon 3. The film forming rate is higher on the side face than on the plane portion, and is higher as the NH3 gas pressure increases. Moreover, under an SF6 gas pressure of 0.1 Pa, the mask 1 is deposited under a less NH3 gas pressure, and over 0.1 Pa, NH3 mixing ratio must be made higher. After the sample is treated under conditions to deposite the mask 1, decreasing the NH3 adding quantity etches the polysilicon or single crystalline silicon 3 into a desired cross sectional etching shape, with the result that treating quality of wiring material can be improved.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はエツチング方法に関し、特に多結晶シリコンお
よびシリコンの断面形状制御に好適なエツチング方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an etching method, and particularly to an etching method suitable for controlling the cross-sectional shape of polycrystalline silicon and silicon.

〔発明の背景〕[Background of the invention]

従来のエツチング方法として特開昭59−39048に
記載のように絶縁膜上のマスク層に炭素、フッ素。
As a conventional etching method, carbon and fluorine are used as a mask layer on an insulating film, as described in Japanese Patent Laid-Open No. 59-39048.

水素を含む混合ガスによるプラズマによって、試料表面
にC−F結合を有するポリマーを堆積させる方法が提案
されている。しかしシリコンあるいは多結晶シリコンな
どのような導体に関しては配慮されておらず、また堆積
物もC−F結合を有するポリマー以外の点について配慮
されていなかった。
A method has been proposed in which a polymer having C--F bonds is deposited on the surface of a sample using plasma using a mixed gas containing hydrogen. However, no consideration was given to conductors such as silicon or polycrystalline silicon, and no consideration was given to deposits other than polymers having C--F bonds.

〔発明の目的〕[Purpose of the invention]

本発明の目的はますます微細化する半導体製造における
加工技術において、エツチング断面形状の制御、サイド
エツチングによるパターン寸法の減少の防止、さらには
りソグラフイ技術では不可能になる領域でのマスクパタ
ーンのブローディング技術を提供することにある。
The purpose of the present invention is to control etching cross-sectional shapes, prevent reduction in pattern dimensions due to side etching, and prevent mask pattern broadening in areas that are impossible with beam lithography technology in semiconductor manufacturing processing technology that is becoming increasingly finer. The goal is to provide technology.

〔発明の概要〕[Summary of the invention]

ドライエツチング技術においてはマスク寸法どおりのエ
ツチング加工ができることが必要であるが、実際にはエ
ツチング中にマスク寸法が小さくなることや、アンダカ
ットがあるため、仕上り寸法はマスク寸法より小さくな
ることが多い、その対策としてあらかじめ寸法目減り分
だけマスク寸法を太くしておくことで仕上り寸法を所定
の寸法にするなどの工夫が行われていた。しかしサブμ
m寸法の素子製造となるとマスクパターン間のスペース
幅が、たとえば0.6μm以下となり、光りソグラフイ
でパターニングできない限界に近づき、マスク寸法をブ
ローディングすることはできなくなった。したがってエ
ツチングにおいては寸法目減りのないマスク寸法どおり
の加工法が絶対に必要な状況になった。しかし上記のと
おり完全なドライエツチング法は未だ開発されていない
In dry etching technology, it is necessary to be able to perform etching according to the mask dimensions, but in reality, the mask dimensions become smaller during etching and there are undercuts, so the finished dimensions are often smaller than the mask dimensions. As a countermeasure, measures have been taken such as making the mask dimension thicker by the amount of dimension reduction in advance so that the finished dimension is a predetermined dimension. But sub μ
When manufacturing m-dimensional elements, the space width between mask patterns becomes, for example, 0.6 μm or less, which approaches the limit beyond which patterning can be performed by photolithography, and it is no longer possible to widen the mask dimensions. Therefore, in etching, it is absolutely necessary to have a processing method that matches the mask dimensions without any reduction in dimensions. However, as mentioned above, a complete dry etching method has not yet been developed.

そこでマスクにのみ堆積するデポジション方法を検討し
た。従来のプラズマによるポリマーの堆積法では選択的
にレジストマスクにのみ堆積することがほとんど不可能
であり、単なる炭素、水素。
Therefore, we investigated a deposition method that deposits only on the mask. With conventional plasma-based polymer deposition methods, it is almost impossible to selectively deposit only on the resist mask, and only carbon and hydrogen can be deposited selectively.

酸素などの混合ガスによるプラズマでは期待できなかっ
た。シリコンおよび多結晶シリコンの垂直エツチングに
有効なSF、とNH,の混合ガスにおいて、NH,Iを
過剰に混合すると、レジストマスクに選択的に堆積が起
り、シリコンおよび多結晶シリコンには堆積もエツチン
グも起こらないことが見出された。
This could not be expected with plasma using a mixed gas such as oxygen. In a mixed gas of SF and NH, which is effective for vertical etching of silicon and polycrystalline silicon, if NH and I are mixed excessively, deposition will occur selectively on the resist mask, and deposition and etching will occur on silicon and polycrystalline silicon. It was also found that this does not occur.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の一実施例を説明する。プラズマを発生させ
る装置は本実施例において有磁場マイクロ波プラズマエ
ツチング装置を用いたが、他のプラズマエツチング装置
、反応性イオン(またスパッタ)エツチング装置を用い
ることもできる。有磁場マイクロ波プラズマエツチング
においてSF。
An embodiment of the present invention will be described below. Although a magnetic field microwave plasma etching apparatus is used in this embodiment as a plasma generating apparatus, other plasma etching apparatuses or reactive ion (or sputter) etching apparatuses may also be used. SF in magnetic field microwave plasma etching.

ガスをエツチングガスとした場合第2図に示す断面形状
が得られる。第2図でマスク材料はホトレジスト(AZ
1350J)  1であるが、エツチング前には点線2
に示す寸法であった。被エツチング材料は多結晶シリコ
ン3であるが、エツチング前は点線4に示す状態であっ
た。多結晶シリコンの下地は酸化シリコンSi0.5で
ある。第2図エツチング断面形状はマスクの下がエツチ
ングされる。
When the etching gas is used as the etching gas, the cross-sectional shape shown in FIG. 2 is obtained. In Figure 2, the mask material is photoresist (AZ
1350J) 1, but dotted line 2 before etching
The dimensions were as shown in . The material to be etched is polycrystalline silicon 3, which was in the state shown by the dotted line 4 before etching. The base of the polycrystalline silicon is silicon oxide Si0.5. In the etched cross-sectional shape of FIG. 2, the bottom of the mask is etched.

いわゆるアンダカット状態を示しており、第1図におい
てaはアンダーカットによる寸法シフト量を示し、bは
マスク寸法からの寸法シフト量である。第2図に示した
断面形状が得られるときの有磁場マイクロ波プラズマ条
件はSF、ガス圧力0、IPa、マイクロ波パワー20
0Wである。第3図はアンダーカットがないように、S
F、0.IPaにNH,0,06Pa添加したときのエ
ツチング断面形状である。第3図で多結晶シリコン3は
マスク1の寸法どおりにエツチングされているようにみ
えるが、実際にはエツチング前のマスク寸法2より減少
している。減少量はオーバーエツチング時間によって変
わるが、本実施例ではエツチング時間の30%オーバエ
ッチ(約40秒)により、約0.2μmだけマスク幅が
減少する。
This shows a so-called undercut state, and in FIG. 1, a indicates the amount of dimensional shift due to the undercut, and b indicates the amount of dimensional shift from the mask dimension. The magnetic field microwave plasma conditions to obtain the cross-sectional shape shown in Figure 2 are SF, gas pressure 0, IPa, and microwave power 20.
It is 0W. Figure 3 shows the S
F, 0. This is the etched cross-sectional shape when NH and 0.06Pa are added to IPa. In FIG. 3, it appears that the polycrystalline silicon 3 has been etched to match the dimensions of the mask 1, but in reality, the dimensions of the polycrystalline silicon 3 are smaller than the dimensions of the mask 2 before etching. Although the amount of reduction varies depending on the overetching time, in this embodiment, overetching by 30% of the etching time (about 40 seconds) reduces the mask width by about 0.2 μm.

上記のように通常のエツチング方法においては。In the normal etching method as mentioned above.

マスク寸法の減少あるいはマスク下部へエツチングがく
い込むアンダーカット現象があり、エツチング前のマス
ク寸法どおりの加工寸法を得ることが困難な場合が多い
There is an undercut phenomenon in which the mask size decreases or the etching digs into the lower part of the mask, and it is often difficult to obtain processing dimensions that match the mask dimensions before etching.

本発明においてはSF、 0.I Paに0.06Pa
以上のNH3ガスを添加し、第1図の断面形状が得られ
た0本実施例においては、多結晶シリコン3はエツチン
グされず、エツチング前のマスク2に堆積した新らたな
マスク1が形成されている。ここで堆積膜の特徴は平面
部より側面部の膜形成速度が大きい、この現象は表面の
材料の差異によって選択的に堆積する現象であり、SF
、+NH,混塁ガスの場合多結晶シリコンあるいはシリ
コン単結晶とホトレジストマスクの場合に特徴的な現象
である。たとえば酸化シリコン、タングステンなどの他
材料とホトレジストの場合には全面に堆積して選択的に
マスクを太らせることはできない。
In the present invention, SF, 0. 0.06 Pa to I Pa
In this example, the cross-sectional shape shown in FIG. 1 was obtained by adding the above NH3 gas, the polycrystalline silicon 3 was not etched, and a new mask 1 deposited on the mask 2 before etching was formed. has been done. The characteristic of the deposited film here is that the film formation rate is faster on the side surface than on the flat surface, and this phenomenon is a selective deposition phenomenon due to differences in surface materials.
, +NH, mixed base gas This is a characteristic phenomenon in the case of polycrystalline silicon or silicon single crystal and a photoresist mask. For example, when using photoresist with other materials such as silicon oxide or tungsten, it is not possible to selectively thicken the mask by depositing it on the entire surface.

多結晶シリコンあるいはシリコン単結晶上のホトレジス
トに選択的に堆積させるSF、+NH,混合ガスについ
ては、SF、ガス圧力が0.1Paのときには0.06
Pa以上のNH3ガス添加で起り、NH3ガス圧力が高
いほど堆積速度が大きい、またSF、ガス圧力が0.1
Paより低い場合にはNH3ガス圧力が上記SF、とN
H,の比率が低くなっても堆積しやすくなる。たとえば
SF。
For selectively depositing SF, +NH, and mixed gas on photoresist on polycrystalline silicon or silicon single crystal, SF is 0.06 when the gas pressure is 0.1 Pa.
It occurs when NH3 gas is added above Pa, and the higher the NH3 gas pressure, the higher the deposition rate.
When the NH3 gas pressure is lower than Pa, the above SF and N
Even if the ratio of H is lowered, it becomes easier to deposit. For example, SF.

0.05Paのときには0.02P a以上で堆積が起
こる。
When the pressure is 0.05 Pa, deposition occurs above 0.02 Pa.

逆にSF、ガス圧力が0.1Paより高い場合にはNH
,混合比率を高くする必要がある0以上のごとくにして
マスクにのみ選択的に堆積できることによって、マスク
のブローディング加工が可能となり、リソグラフィ技術
でマスクを開孔できる限界(たとえば0.6μmの開孔
が現在の光プロセスで最小といわれている)よりもさら
に小さな開孔(光りソグラフイプロセスにより0.6μ
mに開孔した試料に本特許方法を適用すれば、0.6μ
m以下の開孔)にすることができる。
On the contrary, SF, if the gas pressure is higher than 0.1 Pa, NH
By selectively depositing only on the mask with a mixing ratio of 0 or more, which requires a high mixing ratio, it is possible to perform mask widening, and it is possible to overcome the limit of openings in the mask using lithography technology (for example, 0.6 μm openings). The hole is even smaller (0.6μ by the optical lithography process) than the hole that is said to be the smallest in the current optical process.
If this patented method is applied to a sample with a hole of 0.6μ
It is possible to make the opening size smaller than m.

以下この新らたに堆積したマスクにより、マスクの減少
の少い条件でエツチング加工すると、初期のマスク寸法
より大きな寸法に加工できる。また開孔部であれば、第
4図に示すように初期マスク寸法2より小さな開孔部6
のエツチングが可能となる。この方法を用いるとエツチ
ング方法がアンダーカットを起こす条件であっても、第
5図に示すように多結晶シリコン3の仕上り寸法dは初
期のマスク寸法2に制御することが可能となる。
If etching is then performed using this newly deposited mask under conditions that reduce the amount of the mask, it is possible to process the mask to a size larger than the initial mask size. In addition, if it is an opening, as shown in FIG.
Etching is possible. By using this method, even if the etching method causes undercutting, the finished dimension d of the polycrystalline silicon 3 can be controlled to the initial mask dimension 2, as shown in FIG.

本堆積膜の材質が何であるか明確ではないが。Although it is not clear what the material of this deposited film is.

本堆積物はSF、ガスまたはSF、に添加量の少いNH
,混合ガスによって、ホトレジストマスクより大きな速
度でエツチングされる特性を有している。したがって、
堆積させる条件で試料を処理したのちに、NH,ガス添
加量を減少させると。
This deposit is SF, gas or SF, with a small amount of NH added to it.
, and has the characteristic of being etched at a higher rate than a photoresist mask by a mixed gas. therefore,
After processing the sample under the deposition conditions, the amount of NH and gas added is reduced.

第6図a、b、aに示したエツチング断面形状のごとく
、制御の仕方により所望のエツチング断面形状を得るこ
とができる。多結晶シリコンあるいはシリコン単結晶を
以上のように制御して、エツチング断面形状を得ること
ができたことにより、たとえば実際のLSI製造におい
て、配線間の電気的短絡を防止することができる。すな
わち第7図aに示すごとく通常垂直に近いエラチン加工
された多結晶シリコン3の眉間絶縁膜(たとえばSin
、、P53Gなど)7が形成され、その上に第2番目の
配線材料8(たとえば多結晶シリコン。
As shown in the etched cross-sectional shapes shown in FIGS. 6a, b, and a, a desired etched cross-sectional shape can be obtained by controlling the method. By controlling polycrystalline silicon or silicon single crystal in the manner described above to obtain an etched cross-sectional shape, it is possible to prevent electrical shorts between wiring lines, for example, in actual LSI manufacturing. That is, as shown in FIG. 7a, the glabellar insulating film (for example, Sin
, , P53G, etc.) 7 is formed, on which a second wiring material 8 (eg polycrystalline silicon) is formed.

タングステン、シリサイド、アルミニウム外ど)が形成
されて、第2番目の配線材料8をエツチング加工したと
き、眉間絶縁膜形成のときにくびれた部分に第2配線材
料のエッチ残り9が生じ、配線間の電気的短絡の原因と
なる0本特許方法を用い、あらかじめ多結晶シリコンの
エッチ断面形状をたとえば第6 vAaのようにしてお
けば、上記第7図すのように、眉間絶縁膜7にくさびが
生じないため、第2配線材料がエツチングさすに残る部
分(第7図aの9)がないので良好なエツチング加工が
可能になる。
tungsten, silicide, aluminum etc.) is formed, and when the second wiring material 8 is etched, an etched residue 9 of the second wiring material is formed in the constricted part when the insulating film is formed between the eyebrows. If the etched cross-sectional shape of the polycrystalline silicon is set to 6 vAa in advance using this patented method, a wedge can be formed in the glabella insulating film 7 as shown in Figure 7 above. Since no portion of the second wiring material remains after etching (9 in FIG. 7a), a good etching process is possible.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、光りソグラフイで不可能な微細な開孔
マスクを作成することが可能となり、たとえば相関絶縁
膜に開孔するコンタクトホールあるいはスルーホールな
どを微細に作成することが可能となり、またテーパエツ
チングを行うことにより、配線材料のエツチング加工で
しばしば問題となる配線間の電気的短絡問題を激減する
ことが可能となり、半導体製造における歩留りを著しく
向上させると同時に微細加工の質的向上をさせる効果が
ある。
According to the present invention, it is possible to create a fine aperture mask that is impossible with photolithography, and for example, it is possible to create fine contact holes or through holes in a correlative insulating film. By performing taper etching, it is possible to drastically reduce the problem of electrical short circuits between wirings, which often occur when etching wiring materials, and at the same time significantly improve the yield in semiconductor manufacturing and improve the quality of microfabrication. effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明においてマスクに選択的堆積した状態を
示す断面図、第2図はSF、ガスのみを用いた多結晶シ
リコンのエツチング断面図、第3図はSF、とNH,混
合ガスを用いたアンダーカットのないエツチング断面図
、第4図は選択堆積後のエツチング断面図、第5図は選
択堆積後のアンダーカット条件でのエツチング断面図、
第6図は選択堆積後に堆積物と多結晶シリコンを同時あ
るいは制御したエツチング断面図、第7図は多層配線の
断面図である。 1・・・エツチング後のマスク、2・・・エツチング前
のマスク、3・・・多結晶シリコン、4・・・エツチン
グ前・・・層間絶縁膜、8・・・第2配線材料、9・・
・第2配線材料のエツチング残り。 茶 1  図 第 Z 図 ′IfJ3  図 宴 4 図 菖5図 ¥J 6 図 (12−)(b)(c) 葛 7 図
Fig. 1 is a cross-sectional view showing selective deposition on a mask in the present invention, Fig. 2 is a cross-sectional view of polycrystalline silicon etched using only SF and gas, and Fig. 3 is a cross-sectional view of polycrystalline silicon etched using SF, NH, and a mixed gas. FIG. 4 is an etched cross-sectional view after selective deposition, and FIG. 5 is an etched cross-sectional view under undercut conditions after selective deposition.
FIG. 6 is a cross-sectional view of etching deposits and polycrystalline silicon simultaneously or in a controlled manner after selective deposition, and FIG. 7 is a cross-sectional view of a multilayer wiring. DESCRIPTION OF SYMBOLS 1...Mask after etching, 2...Mask before etching, 3...Polycrystalline silicon, 4...Before etching...Interlayer insulating film, 8...Second wiring material, 9.・
- Etching residue of second wiring material. Tea 1 Figure Z Figure 'IfJ3 Illustration 4 Iris 5 Figure ¥J 6 Figure (12-) (b) (c) Kudzu 7 Figure

Claims (1)

【特許請求の範囲】 1、シリコンもしくは多結晶シリコン表面上に所定開口
を有するマスク層を形成する工程とプラズマ処理する工
程によつて、マスク層に選択的に被膜を形成することを
特徴とするエッチング方法。 2、プラズマ処理するときのガスをフッ素、窒素、水素
を含むガスにすることを特徴とする特許請求の範囲第1
項記載のエッチング方法。 3、フッ素を含むガスとしてSF_6ガス、窒素と水素
を含むガスとしてNH_3ガスとすることを特徴とする
特許請求の範囲第1項乃至第2項記載のエッチング方法
[Claims] 1. A film is selectively formed on the mask layer by a step of forming a mask layer having a predetermined opening on the surface of silicon or polycrystalline silicon and a step of plasma treatment. Etching method. 2. Claim 1, characterized in that the gas used for plasma treatment is a gas containing fluorine, nitrogen, and hydrogen.
Etching method described in section. 3. The etching method according to claims 1 and 2, characterized in that the gas containing fluorine is SF_6 gas, and the gas containing nitrogen and hydrogen is NH_3 gas.
JP6066385A 1985-03-27 1985-03-27 Etching method Pending JPS61220432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6066385A JPS61220432A (en) 1985-03-27 1985-03-27 Etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6066385A JPS61220432A (en) 1985-03-27 1985-03-27 Etching method

Publications (1)

Publication Number Publication Date
JPS61220432A true JPS61220432A (en) 1986-09-30

Family

ID=13148798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6066385A Pending JPS61220432A (en) 1985-03-27 1985-03-27 Etching method

Country Status (1)

Country Link
JP (1) JPS61220432A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266157A (en) * 1990-10-04 1993-11-30 Sony Corporation Dry etching method
US5314576A (en) * 1992-06-09 1994-05-24 Sony Corporation Dry etching method using (SN)x protective layer
US5391244A (en) * 1992-02-14 1995-02-21 Sony Corporation Dry etching method
US5397431A (en) * 1992-07-24 1995-03-14 Sony Corporation Dry etching method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266157A (en) * 1990-10-04 1993-11-30 Sony Corporation Dry etching method
US5391244A (en) * 1992-02-14 1995-02-21 Sony Corporation Dry etching method
US5314576A (en) * 1992-06-09 1994-05-24 Sony Corporation Dry etching method using (SN)x protective layer
US5397431A (en) * 1992-07-24 1995-03-14 Sony Corporation Dry etching method

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