JPS61220381A - Manufacture of metal-semiconductor-metal photodiode - Google Patents
Manufacture of metal-semiconductor-metal photodiodeInfo
- Publication number
- JPS61220381A JPS61220381A JP60061225A JP6122585A JPS61220381A JP S61220381 A JPS61220381 A JP S61220381A JP 60061225 A JP60061225 A JP 60061225A JP 6122585 A JP6122585 A JP 6122585A JP S61220381 A JPS61220381 A JP S61220381A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- substrate
- resist
- recessed sections
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 11
- 239000002184 metal Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 11
- 230000008878 coupling Effects 0.000 abstract description 10
- 238000010168 coupling process Methods 0.000 abstract description 10
- 238000005859 coupling reaction Methods 0.000 abstract description 10
- 238000010884 ion-beam technique Methods 0.000 abstract description 5
- 238000003486 chemical etching Methods 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 13
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 11
- 230000005684 electric field Effects 0.000 description 10
- 239000010410 layer Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- SEPQTYODOKLVSB-UHFFFAOYSA-N 3-methylbut-2-enal Chemical compound CC(C)=CC=O SEPQTYODOKLVSB-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000000098 azimuthal photoelectron diffraction Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
金属・半導体・金属(メタル・セミコンダクタ・メタル
、MSN )ホトダイオードであって、メタルエツジに
電界集中を起すことのないようにするために基板に凹凸
を設けて電極を形成するにおいて、前記した電界集中を
なくし、かつ、結合効率の改善されたMSMホトダイオ
ードをセルファライン法で製造する方法である。[Detailed Description of the Invention] [Summary] A metal/semiconductor/metal (MSN) photodiode in which an electrode is formed by providing irregularities on the substrate in order to prevent electric field concentration from occurring at the metal edge. This is a method of manufacturing an MSM photodiode using a self-line method, which eliminates the above-mentioned electric field concentration and has improved coupling efficiency.
本発明はMSMホトダイオードの製造方法に関するもの
で、さらに詳しく言えば、ガリウム砒素(GaAs)基
板に凹凸を形成した後にセルファライン(自己整合)に
よって電極を凹部内に形成することにより、電界集中が
なく、結合効率の改善されたMSMホトダイオードを製
造する方法に関するものである。The present invention relates to a method for manufacturing an MSM photodiode. More specifically, the present invention relates to a method for manufacturing an MSM photodiode, and more specifically, by forming irregularities on a gallium arsenide (GaAs) substrate and then forming electrodes in the recesses by self-alignment, electric field concentration is eliminated. , relates to a method of manufacturing an MSM photodiode with improved coupling efficiency.
MSMホトダイオードを形成する場合、くし形電極を、
半導体にプレナールで金属を蒸着することによって形成
することが知られている。第3図はかかるMSMホトダ
イオードの断面図であって、同図において、31はGa
As基板、32は^l電極をそれぞれ示し、Af電極3
2は例えば3μmの幅のものが3μm間隔で配置されて
いる。かかるMSNダイオードは、PINダイオードや
APD (アバランシュ・ホトダイオード)に比べF
ETと集積し易い利点があり、オプトエレクトロニクス
集積回路(OBIC)に利用されている。When forming an MSM photodiode, the comb-shaped electrodes are
It is known that it can be formed by depositing metal on a semiconductor using prenal vapor deposition. FIG. 3 is a cross-sectional view of such an MSM photodiode, in which 31 is a Ga
As substrate, 32 indicates ^l electrode, Af electrode 3
2 have a width of 3 μm, for example, and are arranged at intervals of 3 μm. Such MSN diodes have lower F than PIN diodes and APDs (avalanche photodiodes).
It has the advantage of being easy to integrate with ET, and is used in optoelectronic integrated circuits (OBICs).
しかし、第3図に示すMSMホトダイオードにおいては
、i電極22のエツジ(縁部分)に電界集中が発生する
問題が見出された。そこで、本発明者は第4図の断面図
に示されるMSMホトダイオードを開発した。なお第3
図において、31はGaAs基板、32はAl電極、3
3はGaAs基板31に形成された凹部を示す。かかる
MSMホトダイオードにおいて、電界集中の問題は改善
され、また光の吸収係数αの逆数程度に半導体をほり込
んで凹部33を形成し、この凹部にシッットキ電極(A
β電極33)を形成することにより、吸収係数の逆数の
深さにおいては電界強度を強くすることができ、光励起
キャリアを高速に加速すること、従って高速応答の光検
出器を提供することが可能となった。However, in the MSM photodiode shown in FIG. 3, a problem was found in which electric field concentration occurred at the edge of the i-electrode 22. Therefore, the present inventor developed an MSM photodiode shown in the cross-sectional view of FIG. Furthermore, the third
In the figure, 31 is a GaAs substrate, 32 is an Al electrode, 3
3 indicates a recess formed in the GaAs substrate 31. As shown in FIG. In such an MSM photodiode, the problem of electric field concentration has been improved, and a recess 33 is formed by drilling the semiconductor to a depth approximately equal to the reciprocal of the light absorption coefficient α, and a Schittky electrode (A
By forming the β electrode 33), it is possible to increase the electric field strength at a depth that is the reciprocal of the absorption coefficient, and it is possible to accelerate photoexcited carriers at high speed, thereby providing a photodetector with high speed response. It became.
第4図に示したMSMホトダイオードの製造においては
、Alt電極32の形成にマスク合せが必要であり、マ
スク合せが正しくなされないと図示の如くにへβ電極が
形成されない問題がある。また、Af電極はGaAs基
板の受光面の一部を遮って形成されるので、光照射を受
ける領域は図に矢印で示す部分に減少され、結合効率が
悪くなる問題がある。さらに本発明者が行った実験によ
ると、 へβ電極のエツジにおける電界集中の除去も完
全ではないことが判明した。In manufacturing the MSM photodiode shown in FIG. 4, mask alignment is required to form the Alt electrode 32, and if the mask alignment is not performed correctly, there is a problem that the β electrode will not be formed as shown. Furthermore, since the Af electrode is formed by blocking a part of the light-receiving surface of the GaAs substrate, the area that receives light irradiation is reduced to the area shown by the arrow in the figure, resulting in a problem of poor coupling efficiency. Furthermore, according to experiments conducted by the present inventor, it was found that the electric field concentration at the edge of the β electrode was not completely eliminated.
本発明はこのような点に鑑みて創作されたもので、従来
よりは簡単な工程で、電極のエツジに電界集中が発生す
ることのない、そして結合効率の改善されたMSMホト
ダイオードを製造する方法を提供することを目的とする
。The present invention was created in view of these points, and provides a method for manufacturing an MSM photodiode that does not cause electric field concentration at the edge of the electrode and has improved coupling efficiency, using a simpler process than conventional methods. The purpose is to provide
第1図(alないしくC)は本発明の方法を実施する工
程におけるMSNホトダイオードの要部の断面図である
。FIGS. 1A to 1C are cross-sectional views of essential parts of an MSN photodiode in the process of carrying out the method of the present invention.
先ず、GaAs基板11に凹部12を形成する。First, a recess 12 is formed in a GaAs substrate 11.
次いで、Alを全面に蒸着してAll膜13を形成し、
引続き全面にレジストを塗布し平坦な表面をもったレジ
スト膜14を形成する。Next, Al is deposited on the entire surface to form an All film 13,
Subsequently, a resist is applied to the entire surface to form a resist film 14 having a flat surface.
イオンビームエツチングによりGaAs基板の表面が露
出されるまでレジスト!11114とA1[113をエ
ツチングし、引続き凹部12内に残ったレジストを除去
する。Resist until the surface of the GaAs substrate is exposed by ion beam etching! 11114 and A1[113 are etched, and then the resist remaining in the recess 12 is removed.
かくして、従来例よりも少ない工程で、マスクを用いる
ことな(Al電極を形成してMSMホトダイオードが作
られるものである。In this way, an MSM photodiode can be manufactured in fewer steps than in the conventional example, without using a mask (by forming an Al electrode).
上記方法においては、マスク合せはGaAs基板11に
凹部12を形成するための図示しないレジスト膜のバタ
ーニングにおいてのみ必要であり、第1図(C)に示さ
れるA1電極13は、マスク合せをすることなしにセル
ファラインで形成される。また、AI電極13は、Ga
As基板11の表面の受光部を遮ることがないから結合
効率が改善されるのである。In the above method, mask alignment is necessary only in patterning a resist film (not shown) for forming recesses 12 in GaAs substrate 11, and the A1 electrode 13 shown in FIG. 1(C) is used for mask alignment. It is formed with Selfa Line without any problems. Further, the AI electrode 13 is made of Ga
Since the light receiving portion on the surface of the As substrate 11 is not blocked, the coupling efficiency is improved.
再び第1図を参照すると、GaAs基板11上に図示し
ないホトレジスト(以下レジストという)の膜を形成し
、それを露光、現像し、例えばケミカルエツチングまた
はイオンビームエツチングで凹部12を形成する。凹部
12は、深さ、幅共に3μm。Referring again to FIG. 1, a film of photoresist (hereinafter referred to as resist) (not shown) is formed on a GaAs substrate 11, exposed and developed, and recesses 12 are formed by, for example, chemical etching or ion beam etching. The recess 12 has a depth and width of 3 μm.
また間隔も3μ鋼になるよう形成する。前記したドライ
エツチングで凹部12の表面がダメージを受けている場
合には続いてケミカルエツチングを行ってそのダメージ
を除去する。前記したレジスト膜の露光においてはマス
ク合せが必要であるが、本発明の方法の実施においてマ
スク合せはこの工程においてのみなされる。Also, the spacing is formed to be 3μ steel. If the surface of the recess 12 is damaged by the dry etching described above, chemical etching is subsequently performed to remove the damage. Mask alignment is required in the exposure of the resist film described above, but in implementing the method of the present invention, mask alignment is performed only in this step.
次に、第1図山)に示されるように、全面に3000人
の膜厚に電極形成金属例えばAlを蒸着する。Next, as shown in Fig. 1, an electrode-forming metal such as Al is vapor-deposited to a thickness of 3000 mm over the entire surface.
この蒸着は自公転方式で行うので、凹部の側壁上にもほ
ぼ同じ膜厚のAlが堆積される。引続き、全面にレジス
ト(例えばAzなる商品名のレジスト)を基板表面の膜
厚が3μm程度になるよう塗布する。レジストの塗布は
スピンコード方でなされるので、凹部12内がレジスト
で埋められるだけでなく、レジスト膜14の表面もほぼ
平坦になる。Since this vapor deposition is performed in a rotation-revolution manner, Al is deposited with approximately the same thickness on the side walls of the recess. Subsequently, a resist (for example, a resist with the trade name Az) is applied to the entire surface so that the film thickness on the substrate surface is about 3 μm. Since the resist is applied by a spin cord method, not only the inside of the recess 12 is filled with the resist, but also the surface of the resist film 14 is made substantially flat.
次いで、イオンビームを用いるエツチングでレジスト膜
14の表面から基板表面が露出するまでエツチングする
。このエツチングのためのイオンビームの条件は、レジ
スト、電極用金属の種類などを考慮して適宜設定する。Next, etching is performed using an ion beam until the surface of the substrate is exposed from the surface of the resist film 14. The ion beam conditions for this etching are appropriately set in consideration of the resist, the type of electrode metal, etc.
次いで例えばアセトン系の液を用いて凹部12内に残っ
ているレジストを除去すると、第1図(C)に示される
構造が得られる。Next, the resist remaining in the recesses 12 is removed using, for example, an acetone-based solution, resulting in the structure shown in FIG. 1(C).
この構造社おいて、AI電極13は基板の受光面を遮る
ことがないので結合効率が改善され、かつAl電極のエ
ツジの電界集中がないことが実験により確認された。At this company, it has been confirmed through experiments that the coupling efficiency is improved because the AI electrode 13 does not block the light-receiving surface of the substrate, and there is no electric field concentration at the edge of the Al electrode.
本発明の応用例は第2図の断面図に示され、同図におい
て、21は半絶縁性GaAs基板、22はバッファ一層
、23は本発明の方法により形成されたMSMホトダイ
オード、24はFET活性層、25.26.2.7はそ
れぞれソース、ゲート、ドレイン電極を示し、図示の装
置において、FISTのバッファ層をMSMホトダイオ
ードの動作層として用いることによりFETの集積化が
可能となる。An application example of the present invention is shown in the cross-sectional view of FIG. 2, in which 21 is a semi-insulating GaAs substrate, 22 is a buffer layer, 23 is an MSM photodiode formed by the method of the present invention, and 24 is an active FET. The layers 25, 26, 2, 7 represent the source, gate, and drain electrodes, respectively, and in the device shown, FET integration is possible by using the buffer layer of the FIST as the active layer of the MSM photodiode.
以上述べてきたように本発明によれば、従来に比ベマス
ク合せの数を減らしセルファラインで、電界集中がなく
、結合効率の改善されたMSMホトダイオードが製造さ
れることになり、それは0BICの集積化にきわめて有
効である。As described above, according to the present invention, an MSM photodiode with no electric field concentration and improved coupling efficiency can be manufactured using a self-line with a reduced number of mask combinations compared to the conventional method, and it is possible to manufacture an MSM photodiode with improved coupling efficiency by reducing the number of mask combinations compared to the conventional method. It is extremely effective for
第1図(a)ないしくC)は本発明の方法を実施する工
程おけるMSMホトダイオードの要部の断面図、第2図
は本発明実施例の応用例の断面図、第3図と第4図は従
来のMSMホトダイオードの断面図、
第1図、第2図において、
11はGaAs基板、
12は凹部、
13はAl電極、
14はレジスト膜、
21は半絶縁性GaAs基板、
22はパンファ一層、
23は本発明にかかるMSMホトダイオード、24はF
ET活性層、
25、26.27はソース、ゲート、ドレイン電極であ
る。
第1!i!i7FIGS. 1(a) to 4(c) are cross-sectional views of essential parts of an MSM photodiode in the process of carrying out the method of the present invention, FIG. 2 is a cross-sectional view of an application example of the present invention, and FIGS. The figure is a cross-sectional view of a conventional MSM photodiode. In FIGS. 1 and 2, 11 is a GaAs substrate, 12 is a recess, 13 is an Al electrode, 14 is a resist film, 21 is a semi-insulating GaAs substrate, and 22 is a single layer of breadlayer. , 23 is an MSM photodiode according to the present invention, 24 is an F
In the ET active layer, 25, 26, and 27 are source, gate, and drain electrodes. 1st! i! i7
Claims (1)
法と間隔で凹部(12)を形成する工程、電極(13)
形成用の金属膜を全面に被着しその上にホトレジスト(
14)を塗布する工程、前記基板表面が露出するまでホ
トレジスト(14)と金属膜(13)とをエッチングし
、しかる後に凹部内に残存するホトレジストを除去する
工程を含むことを特徴とするメタル・半導体・メタルホ
トダイオードの製造方法。Step of forming recesses (12) with predetermined dimensions and intervals on the substrate (11) that will become the active layer of the photodiode, electrode (13)
A metal film for formation is deposited on the entire surface, and a photoresist (
14), etching the photoresist (14) and the metal film (13) until the substrate surface is exposed, and then removing the photoresist remaining in the recesses. Method of manufacturing semiconductor/metal photodiodes.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60061225A JPS61220381A (en) | 1985-03-26 | 1985-03-26 | Manufacture of metal-semiconductor-metal photodiode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60061225A JPS61220381A (en) | 1985-03-26 | 1985-03-26 | Manufacture of metal-semiconductor-metal photodiode |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61220381A true JPS61220381A (en) | 1986-09-30 |
Family
ID=13165051
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60061225A Pending JPS61220381A (en) | 1985-03-26 | 1985-03-26 | Manufacture of metal-semiconductor-metal photodiode |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61220381A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0651448A1 (en) * | 1993-10-28 | 1995-05-03 | Hitachi Europe Limited | Improved metal-semiconductor-metal photodetector |
-
1985
- 1985-03-26 JP JP60061225A patent/JPS61220381A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0651448A1 (en) * | 1993-10-28 | 1995-05-03 | Hitachi Europe Limited | Improved metal-semiconductor-metal photodetector |
US5512763A (en) * | 1993-10-28 | 1996-04-30 | Hitachi, Ltd. | Metal-semiconductor-metal photodetector |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2833588B2 (en) | Photodetector and method of manufacturing the same | |
JPS6146078B2 (en) | ||
KR100306414B1 (en) | Photodetector | |
US5242839A (en) | Method of manufacturing an integrated photoelectric receiving device | |
US4403397A (en) | Method of making avalanche photodiodes | |
US20070057299A1 (en) | Systems and methods having a metal-semiconductor-metal (msm) photodetector with buried oxide layer | |
JPS6058686A (en) | Photodetector and method of producing same | |
EP0104094A1 (en) | Method of producing a semiconductor device, using a radiation-sensitive resist | |
US4364164A (en) | Method of making a sloped insulator charge-coupled device | |
JPS61220381A (en) | Manufacture of metal-semiconductor-metal photodiode | |
JPH0330391A (en) | Photoelectron device on semi-insulation substrate and manufacture thereof | |
US5416030A (en) | Method of reducing leakage current in an integrated circuit | |
JPS6213829B2 (en) | ||
JPS61191082A (en) | Semiconductor light receiving element | |
RU2676185C1 (en) | Shf photo detector manufacturing method | |
JP2742358B2 (en) | Semiconductor photodetector and method of manufacturing the same | |
KR0175441B1 (en) | Method for fabricating avalanche photodiode | |
JP2914236B2 (en) | Method for manufacturing semiconductor device | |
JPH02253666A (en) | Semiconductor photodetector | |
JP2766761B2 (en) | Semiconductor photodetector and method of manufacturing the same | |
JPH0766978B2 (en) | Photoelectric conversion element and manufacturing method | |
KR950002206B1 (en) | Semiconductor laser manufacturing method | |
JPH0793455B2 (en) | Avalanche photodiode manufacturing method | |
JPS61137371A (en) | Manufacture of semiconductor device | |
JPS61288475A (en) | Manufacture of photo detector |