JPS61220034A - Microprocessor - Google Patents

Abstract

PURPOSE:To speed up an action by installing a micro cache memory in a microprocessor and preparing the instruction for reading an instruction in the memory and the one for executing said instruction. CONSTITUTION:While a microcounter 13 is counting up until an end MCM instruction appears, following instructions are read in the microprocessor 11 through the load MCM instruction of an external memory 12, and are written in the micro cache memory MCM 15 according to an address specified by a micro cache memory counter MCMC 16. At this time, since the MCMC 16 counts up sequentially values from an initial value 0 in increasing order, the instruction at the top address is first written in the MCM 15. When the execution MCM instruction is executed in this state, an FF 20 which shows an MCM mode flag and is normally inoperable is made operable. Then the output of the MCM 15 is selected by a selecting circuit 17 according to the output of the FF 20, and the next instruction is read out of the MCM 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microprocessor with a microcache, and particularly to its architecture.

[Technical background of the invention and its problems]

Conventionally, methods such as "instruction preloading" and "catch, memory" are widely known as means for executing microprocessor instructions at high speed. The preloading of the above instruction means that the instruction code to be used next is read in advance while the instruction is being executed.
By loading the file in advance, it is possible to speed up the process. t
In addition, the method of using cache and memory improves speed by storing once-read instructions internally, so that when the same instruction is executed again, it does not need to be read again.

However, even if there is a function for preloading instructions, it is not always possible to read the next instruction while the instruction is being executed, and the execution of the current instruction may be delayed due to preloading of instructions. .

On the other hand, with the method of using cache and memory, the amount of instruction code that can be stored is limited because the cache and memory capacity is limited, and when you try to execute the instruction again, the instruction code may have changed to a different instruction code. There are many drawbacks that do not necessarily lead to higher operating speeds. In addition, since the address of the stored instruction code also needs to be memorized, a memory for storing the address and a comparison circuit to match the addresses are also required, which increases the amount of hardware and reduces the cost. It is not suitable for microprocessors.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide a microprocessor that can operate at higher speeds and that does not require an increase in the amount of hardware.

[Summary of the invention]

That is, in the present invention, in order to achieve the above object, a memory (micro cache) is used to store instruction sequences within a microprocessor.

By providing an instruction to read this microcage crystal memory instruction and an instruction to execute it in external memory, the programmer can freely specify the instruction sequence he or she wants to execute. It is.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 11 is a microprocessor;
2 is an external memory, and the microprocessor 11 includes a program counter (PC) 23 (second register) that specifies the program address of the external memory 2, and an instruction manual buffer 1 into which instructions from the external memory 2 are input.
4. A microcache memory (fl) 15 in which a sequence of instructions for operating the microprocessor 11 is stored, this MCM
a micro cache memory counter (MCMC) J 6 (first register) that specifies the address of MCMC 15; a selection circuit 17 that selects the output of MCM J 5 or the output of the instruction manual buffer 14;
an instruction decoder 18 to which the output of the instruction decoder 18 is supplied, and an instruction execution unit 19 to which the output of the instruction decoder 18 is supplied and executes the instruction.
, the output of the instruction execution unit 19 is supplied, and the MCM I
F/F 7' (F/F) 26 which indicates whether or not to read an instruction from S to the selection circuit 17 and instruction execution unit 19 as a microcache memory mode flag.
etc. are stored.

On the other hand, the external memory 12 contains, as instructions for operating the microprocessor 11, a load MCM instruction for loading an instruction sequence into the MCM 15, and an extract MCM instruction for executing instructions stored in the MCM 15 from the beginning. establish. The above load MCM instruction loads the instruction following the instruction into the MCM 15, and its end is the end MCM.
indicated in the command. Execute MCM instruction is MCM
15 is executed from the beginning, and the end MC
When the M instruction is executed, the instruction following the Evski, -) MCM instruction is executed. Note that the instructions loaded into the MCM 15 include the program counter f (PC
7) instruction is allowed, and this PC fetch instruction is
When executed in M15, P is written instead of the instruction code.
Excue indicated by Cl3) Read and execute the next instruction after the MCM instruction.

Since PCl3 is counted up each time this is executed, there may be multiple PC fetch instructions,
-) The instruction codes following the MCM instruction are read in order,
Execution moves to the next instruction with the end MCM instruction.

Next, the operation will be explained. By the load MCM command of the external memory 12, the next instruction is read into the microprocessor 11 while counting up PCl3 until the end MCM command is received, and written to the MCM 15 according to the address specified by MCMC1g.At this time, the MCMCI
6 counts up sequentially from the initial value "0", so instructions are written to MCM 15 in order from the top address of MCM 15. When the writing is completed, PCl3 starts the next MCM instruction after the end MCM instruction. Pointing to the address, the instruction is executed from the address indicated in PCl3. In this state, Efski, -) MC
When the M instruction is executed, the flip-flop 20 indicating the MCM mode flag, which is normally inactive, becomes active, and the selection circuit 12 selects the fi MCM based on the output of the flip-flop 20. 15 outputs are selected. Therefore, the next instruction is read from MCM 15. At this time, MCMCI g is Evski, -) MC
It is initialized to "0#" at the beginning of the M instruction and is counted up every time the instruction is read.

Instructions are sequentially read from the first address of the MCM 1 5, decoded by the instruction decoder 18, and executed by the instruction execution unit 19. Then, when the end MCM command is executed in the MCM mode state, the MCM code is extracted and the program in the external memory 12 is executed by the PCl3. On the other hand, when a PC fetch instruction is executed in the MCM mode, the instruction (or its derivation) is read as a parameter from the external memory 12 at the address indicated by PCl3 and executed by the microprocessor 11. At this time, the value of PCl3 is counted up by the number of instructions read. Subsequent orders are from MC.
It is read from MCM J5 at the address indicated by MC16 and executed.

Note that if there is a jump instruction among the instructions in MCM 1 l, and in the case of a relative address jump, the next address in MCM J j to be executed is determined by adding the 1/Young relative value to the value of MCMCI6.

On the other hand, in the case of absolute addressing, calling a subroutine, or returning from a subroutine, the instruction is executed after exiting the MCM mode. Here, since the PC fetch instruction when not in MCM mode and the load MCM instruction in MCM mode have no meaning, the load MCM instruction and the end MCM instruction are made the same instruction code, and the PC fetch instruction and the executable -to MCM instruction are set to the same instruction code.
The CM instructions may have the same instruction code.

According to such a configuration, a microcache memory 15 is provided in the microprocessor 11, an instruction for reading an instruction and an instruction for executing this instruction are prepared in the external memory, and the grog-tsuma can freely specify a sequence of instructions that it wants to execute. Since the above-mentioned microcache memory can be used without waste, instructions can be executed faster than a method that preloads instructions, and instructions that need to be executed faster than a method that uses cache memory. can only be carried out reliably.

Further, the increase in hardware amount is also relatively small.

FIG. 2 shows a comparison between the instruction execution time of the microphone 112f processor having an instruction preloading function and the instruction execution time of the microprocessor shown in FIG. (&
) The figure shows a method for preloading instructions, and the figure (b) shows the instruction execution time according to the present invention.

Now, suppose that the program to be executed clears the memory to @'0'', and for example, the following program is executed.

5TART: INCAREG step ICLRAR
EG step f2 DECCREG step f3 JNZ 5TART, *TERAGUI In this program, in step 1, AREG (the register containing the memory address to be cleared to '0') is incremented by one, and in step 2, the address indicated by AREG is cleared.Step In 3, select 1 CREG containing the number to be cleared.
If CREG- is not @"O" in Stella f4, the process returns to Stella f1.

(,) In the figure, the shaded area indicates the instruction prefetch time h. Here, the reason why the pre-reading of the instruction in step f3 is executed in step 2 is because in step 2, writing to the memory is executed and the bus is occupied. Furthermore, since the instruction at step f1 jumps from step 4, it is not possible to read the instruction in advance.

Assume that each instruction can be fetched in 4 cycles,
Assuming that changing register values in steps 1 and 3 takes 2 cycles, writing to memory takes 4 cycles, and jumping takes 6 cycles, it takes a total of 30 cycles unless preloading of instructions is performed. By using the instruction preload function, the cycle can be shortened to 26 cycles.

On the other hand, by using the configuration shown in FIG. 1, no instruction fetch cycle is required, so 14 cycles are required.

Of course, time is required to load the load MCM instruction at the beginning of the program, but this can be ignored if the program loops many times.

〔Effect of the invention〕

As described above, according to the present invention, a microprocessor can be obtained which can increase the operating speed and does not require an increase in the amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a microprocessor according to an embodiment of the present invention, and FIG. 2 shows the program execution time of a microprocessor that preloads instructions and the program execution time of the microprocessor shown in FIG. FIG. 11...Microprocessor, 12...External memory, 13...Program counter (second register fi)
, 15... Micro cache memory, 16... Micro cache memory counter (second register),
17... Selection circuit, 18... Instruction decoder, 19.
...Instruction execution section, 20...Flip 70 knobs.

Claims (2)

[Claims] (1) A microcache memory that stores instruction codes, a first register that sets addresses for writing and reading instruction codes into this microcache memory, an instruction to read instruction codes into the microcache memory, and an instruction to read this instruction. an external memory that stores instructions to be executed; a second register that sets a read address of the external memory; a flip-flop that indicates whether or not instructions to be executed are read from the microcache memory; a selection circuit that selects an instruction code stored in the microcache memory or data stored in the external memory based on the output of the instruction decoder; an instruction decoder that identifies the output of the selection circuit; 1. A microprocessor comprising: an instruction execution section that executes instructions using a microprocessor. (2) The microprocessor according to claim 1, wherein the external memory further stores an instruction indicating the end of loading and an instruction indicating the end of the instruction sequence to be executed.