JPS61219158A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to set measurements of the plane surface of a wiring pattern small by a method wherein, after the lower wiring layer including the wiring layer as a pillar conductive layer is formed by patterning, the pillar conductive layer is formed by performing etching using an etching mask in the wire width direction of said wiring. CONSTITUTION:A wiring film 2a, having film thickness equal to the total film thickness of the lower wiring layer and a pillar conductive layer, is formed on the main surface of a substrate 1, the resist film 3d of the lower wiring pattern is formed by coating on the surrace of said wiring film 2a, and the wiring film 2a is selectively removed by performing an etching using said resist film 3d as a mask. Then, the resist film 3e of a pillar conductive pattern is formed by coating in the direction orthogonally intersecting with the longitudinal direction of the wiring film 2a, namely, the width direction of the wiring. The equivalent component of the film thickness of the interlayer insulating film is selectively removed by performing etching on the wiring film 2 using the resist film 3e as an etching mask, and the lower wiring layer 2 is formed. Also, said resist film 3e is removed, and a pillar conductive layer 4 is formed on the lower wiring layer 2 using the remaining film thickness component.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a method for manufacturing a semiconductor device, and in particular to an improvement in a method for forming a pillar conductive layer as a connection between upper and lower wiring layers in multilayer wiring in a semiconductor device. This is related.

[Conventional technology]

In conventional semiconductor devices with this type of multilayer wiring structure, the upper part is formed using the so-called pillar formation method.
The main manufacturing steps of the connection method between the lower wiring layers are shown in FIGS. 4(a) to 4(g).

In the conventional method shown in FIG. 4, first, a wiring film 2a is formed on the main surface of the silicon semiconductor substrate 1 and has a thickness equal to the total thickness of a lower wiring layer and an interlayer insulating film, which will be described below.
A resist film 3a is formed by sputtering using an aluminum alloy film or the like, and a resist film 3a is patterned and coated on the surface corresponding to the pillar that will be the conductive part connected to the upper wiring layer (FIG. 3(a)). This Regis [3
Using an at-etching mask, the wiring film 2a is selectively etched away by a thickness corresponding to the interlayer insulating film, and the remaining film thickness is used to form a pillar conductive layer 4 on the wiring film 2a.
form. In other words, the pillar conductive layer 4 is selectively formed so as to remain with a predetermined amount of protrusion on the arrangement 111i2a (
Figure (b)).

Subsequently, after removing the resist film 3a once, a resist film 3b patterned into a predetermined lower wiring pattern is again coated on the wiring film 2a including the formed pillar conductive layer 4 portion. Formally the same figure (C
)), and by selectively etching away the wiring film 2a other than the pillar conductive layer 4 portion using this resist film 3b as an etching mask, the lower wiring layer 2.
That is, a lower wiring layer 2 having four portions of pillar conductors is formed (FIG. 4(d)).

In this case, after once removing the resist film 3b, a silicon oxide film, a phosphorus glass film, etc. An interlayer insulating film 5 such as the above is formed, and a resist film 3C is again formed to cover the entire surface of the interlayer film 5 (see (e) in the figure), and these resist films 3C and interlayer insulating film 5 are respectively Under conditions such that the etching rates are equal, reactive ion etching (RIE) is not performed until at least the surface portion of the pillar conductive layer 4 is exposed (FIG. 1(f)), and then,
After removing the resist film 3C, an upper wiring layer 6 is formed by patterning, and this upper wiring layer B is connected to the lower wiring layer 2 through the pillar conductive layer 4 (FIG. 3(g)).

At this time, if the thickness of the interlayer insulating film 5 is greater than or equal to the total thickness of the lower wiring layer 2 and the pillar conductive layer 4, the resist film 3c can also be removed at the same time by reactive ion etching. The step of removing the film 3c can be omitted.

[Problem that the invention seeks to solve]

However, in the case of the method for forming a pillar conductive layer according to the conventional example, when the lower wiring layer is etched, the wiring film serving as the lower wiring is coated with a patterned resist film.

It is necessary to cover at least the entire pillar conductive layer, and for this reason, the planar dimensions of the lower wiring layer must be set larger than the planar dimensions of the pillar conductive layer, leading to miniaturization of devices and high density integration. This was a major hindrance to the development of

In view of these drawbacks in the conventional method, the present invention
The purpose of this invention is to provide a method for forming a pillar conductive layer having a line width that is approximately the same as that of the lower wiring layer.

[Means for solving problems]

In order to achieve the above object, the method of the present invention uses a wiring film as a lower wiring layer and a pillar conductor 1! After forming a wiring layer as a layer, etching and removing each of these wiring layers, and forming a lower wiring layer including the wiring layer of the pillar conductive layer into a predetermined pattern.

On this forming layer, an etching mask with a predetermined pillar conductive layer pattern is provided in the direction perpendicular to the longitudinal direction of the wiring, that is, in the line width direction, and the wiring layer of the pillar conductive layer is etched into the knee 2.
This process forms a pillar conductive layer on the lower wiring layer.

[For production]

Therefore, in the method of this invention, after patterning the lower wiring layer including the wiring layer as a pillar conductive layer,
Since the pillar conductive layer is formed by etching using an etching mask in the width direction of the wiring, the width of the pillar conductive layer formed on the lower wiring layer is
It can be formed to a size that roughly matches the line width of the lower wiring layer, and as a result, the planar dimensions of the wiring pattern can be set small.

〔Example〕

Hereinafter, one embodiment of the method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 to 3.

FIGS. 1(a) to 1(e) are perspective views sequentially schematically showing the manufacturing steps at the main stages of the method of this embodiment. The same reference numerals indicate the same or equivalent parts.

In the method of the embodiment shown in FIG. 1, first, a wiring film 2 is formed on the main surface of the silicon semiconductor substrate 1 and has a thickness equal to the total thickness of a lower wiring layer and a pillar conductive layer, which will be described below.
A is formed of an aluminum alloy film or the like by a sputtering method, and a resist film 3d for a lower wiring pattern is formed on the surface thereof (FIG. 3(a)), and this resist film 3.1 is used as an etching mask. , wiring film 2a
is selectively etched away ((b) in the same figure).

Then, after removing the resist film 3d, a pillar conductive film is again formed on the wiring film 2a formed in accordance with the lower wiring pattern in a direction perpendicular to the longitudinal direction of the wiring, that is, in the width direction of the wiring. A resist film 3e is formed to cover the pattern ((C) in the same figure), and this time, using this resist film 3e as an etching mask, the wiring film 2a is selectively etched away by a thickness corresponding to the interlayer insulating film. Then, the resist film 3e is removed to form a lower interconnection layer 892 (FIG. 4(d)), and the pillar conductive layer 4 is formed on the lower interconnection layer 2 using the remaining film thickness. In other words, the pillar conductive layer 4 is selectively formed in a predetermined portion on the lower wiring layer 2 so as to remain with a predetermined protrusion amount (FIG. 2(e)).

Therefore, on the wiring film 2a formed into the lower wiring pattern in this way, the lower wiring can be removed by controlled etching removal using an etching mask in the width direction perpendicular to the longitudinal direction of the wiring. Calculate the width of the pillar conductive layer 4 with respect to the line width of layer 2.1. (It can be considered. In this case, when etching, the line width of the lower interconnection layer 2 is actually somewhat thinner than the width of the pillar conductive layer 4 due to side etching, so 5 this side etching amount is small. It is desirable to employ a highly directional etching method, so that each of these layers can be formed to have the same line width as C as a whole.

Also, Figure 2 shows the planar dimensions of the pillar conductive layer pattern according to the conventional method (FIG. 2(e)) and the same planar dimensions (FIG. 2(e)) according to the method of this embodiment. That is, as is clear from these figures, if the overlay accuracy dimension when forming a resist pattern as an etching mask is dimension d, then in the case of the method of the embodiment, the difference is equivalent to 1 dimension 2d compared to the case of the conventional method. In other words, the line width on the lower wiring layer can be made smaller by an amount corresponding to the dimension 2d.

Furthermore, in the method of the embodiment shown in FIG. 1, the same conductive material is used for the lower wiring layer and the pillar conductive layer.
By using different materials for each of these layers and selectively setting the etching conditions for each layer, side etching is reduced, film thickness can be easily controlled, and the r-section wiring layer has high precision.

A pillar conductive layer can be formed. An example in this case is shown in FIG.

That is, in the method of the embodiment shown in FIG. 3, a wiring film 2α having a thickness equivalent to the original film thickness as a lower wiring layer is formed of a predetermined conductive material, and then a wiring film 7a as a pillar conductive portion is formed. , and a resist film 3d of a lower wiring pattern is formed on these surfaces (FIG. 1(a)),
Using this resist film 3d as an etching mask, each wiring film 7a and 2a is successively and selectively etched away. After the resist film 3d is removed once, the wiring films 2a, ?, are formed in accordance with these lower wiring patterns. a), as in the previous example, again in the direction perpendicular to the longitudinal direction of the wiring, that is, in the width direction of the wiring.

After coating the pillar conductive part pattern with a resist film 3e, this resist film 3e is used as an etching mask, and etching is performed so that the etching speed of the wiring film 7a is as high as possible compared to the wiring film 2a. Set the conditions and
In order to selectively remove only the wiring film 7a in the same figure (b).
)), thereby forming the desired lower wiring layer 2. Then, a pillar conductive layer 7 is formed.

Therefore, in the method of the embodiment shown in FIG. 3, as described above, the lower wiring layer 2. Moreover, the pillar conductive layer 7 can be formed while maintaining the desired line width and film thickness accurately, and the point at which etching of the wiring film 7a is completed can be easily detected, thereby improving accuracy.

Furthermore, in the method of the embodiment shown in FIG. 3, when it is not possible to obtain a large etching rate ratio between the wiring film 2a and the wiring film 7a, an intermediate conductive layer having an etching speed lower than that of the wiring film 7a is interposed between these films. By letting
Similar effects can be obtained, and in this case, the same conductive material may be used for the wiring film 2a and the wiring film 7a.

〔Effect of the invention〕

As detailed above, according to the method of the present invention, a wiring film as a lower wiring layer and a wiring layer as a pillar conductive layer are formed in advance, and each of these wiring layers is removed by etching.
After forming the lower wiring layer including the wiring layer of the pillar conductive layer into a predetermined pattern, an etching mask with a predetermined pillar conductive layer pattern is placed on the formed layer in the line width direction perpendicular to the longitudinal direction of the wiring. Since the wiring layer of the pillar conductive layer is formed and removed by etching, thereby forming the pillar conductive layer on the lower wiring layer, the line width of the pillar conductive layer formed at a predetermined position on the lower wiring layer is The line width of the lower wiring layer can be molded to a size that matches C with good reproducibility, and as a result, the planar dimensions of the wiring pattern can be set small, allowing for miniaturization and high-density integration of semiconductor devices. It is useful for

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are perspective views sequentially schematically illustrating the main steps of the manufacturing process according to an embodiment of the method for manufacturing a semiconductor device according to the present invention. FIGS. 2(a) and (b) are explanatory diagrams showing a comparison of the wiring plane patterns of the conventional example and this embodiment, and FIGS. 3(a) and (b)
4(a) are perspective views sequentially schematically showing the manufacturing process at the main stages according to the above and other embodiments, and FIG.
) to g) are sectional views sequentially showing the manufacturing process at the main stages according to the conventional method as above. 1... Silicon semiconductor substrate, 2a □ and 2.
... Wiring film and lower wiring layer, 3a to 3e...
- Resist film, 7a and 4.7... Wiring film and pillar conductive layer, 8... Upper wiring layer. Agent Masuo Oiwa Figure 1 Figure 1 Figure 1 Figure 2 (CI) (b) Figure 3 Figure 4 procedural amendment (voluntary) 11 [11”: 2 'JJ 2i times

Claims (4)

[Claims] (1) In a method for connecting upper and lower wiring layers in a semiconductor device having multilayer wiring, a wiring film as a lower wiring and a wiring film as a pillar conductive part for connection with an upper wiring are formed on the main surface of a semiconductor substrate. A process of sequentially forming a wiring film as a lower wiring, an intermediate conductive layer, and a wiring film as a pillar conductive part for connection with the upper wiring, and then forming each layer obtained in the previous process into a lower wiring pattern. At the same time, selectively etching is removed to form a lower wiring layer, or a lower wiring layer having an intermediate conductive layer on the upper surface, together with the pillar conductive wiring film, and then, in a previous step, the lower wiring layer is aligned with the lower wiring pattern. An etching mask for a pillar conductive part pattern is provided on each layer formed by the above process in a direction perpendicular to the longitudinal direction of the wiring, and the wiring film serving as the pillar conductive part is selectively etched away, thereby changing the line width of the lower wiring. 1. A method of manufacturing a semiconductor device, the method comprising at least the step of forming a pillar conductive layer substantially equal to . (2) The wiring film as the lower wiring and the wiring film as the pillar conductive part for connection with the upper wiring, or the wiring film as the lower wiring, the thin intermediate conductive layer, and the pillar conductive part for connection with the upper wiring The first aspect of the present invention is characterized in that the same conductive material is used for each of the wiring films, and each of these films is selectively controlled to be removed and formed.
A method for manufacturing a semiconductor device according to section 1. (3) In the case where a wiring film as a lower wiring and a wiring film as a pillar conductive part for connection with the upper wiring are formed in sequence, the wiring film of the lower wiring and the wiring film of the pillar conductive part In the present invention, different conductive materials are used, and at least the wiring film of the lower wiring is etched under conditions that it acts as an etching stopper during etching formation of the wiring film of the pillar conductive part. A method for manufacturing a semiconductor device according to scope 1. (4) In the case where a wiring film as a lower wiring, an intermediate conductive layer, and a wiring film as a pillar conductive part for connection with the upper wiring are formed in sequence, the wiring of the intermediate conductive layer and the pillar conductive part Different conductive materials are used for the films, and at least the intermediate conductive layer is etched under conditions that it acts as an etching stopper during etching formation of the wiring film of the pillar conductive part. A method for manufacturing a semiconductor device according to scope 1.