JPS61218226A - Pulse signal counter - Google Patents

Abstract

PURPOSE:To measure a sudden pulse data quantity by extracting number of times of overflows stored in a storage section and a count at the fine count. CONSTITUTION:When a pulse data increasing suddenly is inputted to a counter 1, an event pulse signal is outputted to a time counter 3 synchronously with an inputted fault signal by a control section 4, which controls the operation of a time counter 3 so as to allow the counter 3 to count a clock number having a prescribed period and stores the result to an address 5-2 of a storage section 5. The clock number counted in this way represents the measurement of the time among event pulses, that is, the time between fault signals. The fault signal times stored in the address 5-2 of the storage section 5 are summed, the result is made equal to the period time of the reset pulse signal, the number of times of overflows and the count at the final count stored in an address 5-1 corresponding to the summed time are extracted to measure the data quantity increasing suddenly at the reset time.

Description

[Detailed Description of the Invention] [Summary] A pulse signal counting device for counting pulse signals, comprising:
If a reset type counter that uses the number of counts within a certain period as data overflows, the amount of data will be lost, so instead of counting the pulse data, measure the overflow time and calculate the amount of pulse data that has overflowed from that measurement time. can be measured statistically.

[Industrial application field]

The present invention relates to a pulse signal counting device that counts pulse signals, and more specifically, to a pulse signal counting device that can count pulse signals that suddenly increase and overflow.

2. Description of the Related Art In fields such as communications and information processing, pulse signal counting devices are used to count the amount of pulse signals, one of which is a reset type counter. When counting pulse signals with this reset type counter, the count number within a fixed period is used as data, but if the amount of pulse signals suddenly increases, the count number overflows and the amount of data becomes unknown.

Therefore, there has been a need for a pulse signal counting device that can accurately measure the amount of pulse signals even if the amount of pulse signals suddenly increases and the count overflows.

[Conventional technology]

Conventionally, the pulse signal amount was measured using the professional method shown in Figure 3.

The pulse signal counting device shown in the figure is used.

In the figure, a reset type pulse counter 1 counts the number of input pulse signals, is reset by a reset signal outputted at regular intervals from a reset control section 2, and outputs the count amount before reset as a count value.

The operation will be explained in more detail with reference to the time chart of the conventional counting device shown in FIG.

Normally, a constant amount of pulse signals are always input to the pulse counter 1, as shown at 81 in FIG. 4A.

The pulse counter 1 selects the input pulse signal as shown in 411B, is reset by a reset signal output from the reset control section 2 at a predetermined period t1, and outputs a counter amount B1 within the period t1.

As shown at 42-1 in FIG. 4, when the pulse signal suddenly increases, the pulse counter 1 has a counting capacity a1.
When it overflows, the count starts again from 0, and the fourth
As shown in FIG. C, how many times does the reset signal overflow during the period in which the reset signal is input, and the count is repeated from 0? In this case, the counter amount at the time the reset signal is input is C
The count amount is indicated by the circle mark in the figure, and the actual pulse data within the period of the reset signal is unknown.

[Problem that the invention seeks to solve]

This conventional pulse signal measuring device has a problem in that when a suddenly increased pulse signal is input and the counting capacity of the pulse counter is exceeded, the amount of data becomes unknown as described above.

The present invention was created in view of these points.
It is an object of the present invention to provide a pulse signal counting device that can count the data amount of pulse signals that are suddenly input with a simple configuration.

[Means for solving problems]

FIG. 1 shows a block diagram of a pulse signal counting device of the present invention. In FIG. 1, l is a pulse counter that counts input pulse signals and outputs an abnormal signal when the count overflows, 6 is a clock signal generator that generates a clock signal with a constant period, and 3 is a clock signal generator 6. 5 is a storage unit that stores the count values output from pulse counter 1 and time counter 3 in addresses 5-1 and 5-2; 4 is a pulse counter 1 reset signal; A control unit is shown which outputs an event pulse in synchronization with the abnormal signal output from the pulse counter 1, and causes the time counter 3 to count the clock signal, and the present invention has these components. ing.

[Effect]

Measurement of pulse data input in the normal state is performed by the control unit 4.
The reset signal output from the pulse counter 1
is reset, and the pulse data can be known from the count data at the time of reset.

When pulse data that suddenly increases is input to pulse counter 1, it exceeds the counting capacity of pulse counter 1, and when the capacity is exceeded, pulse counter 1 starts counting from 0 again, and starts counting from 0 several times during the reset period. The count is repeated and the number of times is stored in the address 5-1 of the storage section 5.

Further, the pulse counter 1 outputs an abnormality signal to the control unit 4 when the capacity is exceeded. The control unit 4 generates an event pulse signal in synchronization with the input abnormal signal and outputs it to the time counter 3. The time counter 3 counts the number of clocks having a predetermined cycle outputted from the clock signal generating section 6 during the period in which the abnormal signal is generated under the control of the event pulse signal. This count number is stored at address 5-2 of storage section 5. The count number of this clock measures the time between abnormal signals.

The abnormal signal times stored in 5-2 of the storage unit 5 are totaled in a time equal to the cycle time of the reset signal, and the number of overflows and the final count stored in address 5-1 within the total time are calculated. The sudden amount of pulse data within the takeout and reset signal time is known.

〔Example〕

FIG. 2 is a time chart of the pulse counting device of the present invention, and the operation of FIG. 1 will be explained with reference to the same figure. Second
As shown in A2-1 of Figure A, when pulse data that suddenly increases is input to, for example, a 4-bit, 7-bit pulse counter 1, the counting capacity becomes 255 pieces, as shown in Figure 2B. If the number is 256 or more, it will overflow and counting will become impossible, so the 256th number will be counted again as O, and the above counting will be repeated several times until a reset signal is input. -1 address.

On the other hand, when the pulse counter 1 overflows, that is, every 256th pulse, the abnormal signal shown in FIG.
Output to. The control unit 4 outputs an event pulse signal to the time counter 3 in synchronization with the input abnormal signal, controls the operation of the time counter 3, and maintains a predetermined period between event pulse signals as shown in the second figure. The number of clocks is counted and stored at address 5-2 in the storage section 5.

This counted number of clocks measures the time between event pulses, that is, the time between abnormal signals.

The abnormal signal time stored in the address 5-2 of the storage unit 5 is totaled to be equal to the period time of the reset pulse signal,
The number of overflows and the count amount of the final count stored in the address 5-1 corresponding to the total time are taken out to measure the amount of data that suddenly increases during the reset time.

〔Effect of the invention〕

As described above, according to the present invention, pulse data that is suddenly increased and input can be measured with an extremely simple circuit configuration, and is extremely useful in practice.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a pulse signal counting device of the present invention, Fig. 2 is a time chart of a pulse signal counting device of the present invention, Fig. 3 is a block diagram of a conventional pulse signal counting device, and Fig. 4 is a block diagram of a conventional pulse signal counting device. In the figure which is a time chart of the pulse signal counting device, 1 is a pulse counter, 2 is a reset control section, 3 is a time counter, 4 is a control section, 5 is a storage section, 5-1 and 5-
2 is an address of a storage section, and 6 is a clock signal generation section. Be careful, I believe in you.
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Claims (1)

[Claims] A pulse counter (1) that counts input pulse signals and outputs an abnormal signal of counting operation, a clock signal generator (6) that generates a clock signal with a constant period, and a time counter that counts the clock signal. (3) and a storage unit (
5) and the time counter (3) by the abnormal signal.
1. A pulse signal counting device comprising: a control section (4) for controlling the counting operation of the pulse signal counting device (4);