JPS61216520A - Programmable logical apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to programmable logic devices and, more particularly, to programmable logic devices using techniques for high speed programming and matching operations of array program data and logic paths of a logic device.

BACKGROUND OF THE INVENTION Digital systems, such as computers, are typically constructed from a number of integrated logic and storage integrated circuits or chips. The goal of microelectronic integration is to construct the memory and logic circuits of a system using the smallest number of integrated circuits possible, and to reduce cost, increase system processing speed, and increase reliability. It's about improving.

Although useful memory can be designed relatively easily,
Certain problems exist for integrated circuit manufacturers in logic circuits. That is, the manufacturer cannot afford to produce an integrated logic circuit that can fully meet the specific needs of every customer. Instead, it can afford to produce a general-purpose logic circuit that can perform as many roles as possible. VLS I
You can also design circuits. For example, a microprocessor can represent logical functions in the form of software and is used in conjunction with a storage device. Also, standard peripherals can integrate many logic circuits in a digital system. However, random logic circuits are still required to interface with the components of this system.

Several schemes are used to provide these random logic circuits. One solution is standard logic circuits such as transistor-transistor logic (TTL).

Because TTL integrated circuits integrate only a relatively small number of commonly used logic functions, TTL integrated circuits can be used in a wide range of applications. Its drawback is the number of commonly used logic functions. The disadvantage is that a large number of TTL integrated circuits are typically required for certain applications, which increases power consumption and board space, and increases the overall cost of the digital system. be.

Other alternative circuits include fully custom-made so-called custom integrated logic circuits, such as gate arrays, and partially custom-made so-called semi-custom integrated logic circuits. Custom logic circuits, or more precisely logic circuits made to meet the needs of a particular application, have a specific circuit structure and can greatly reduce the number of components required for a given system. . However, custom-made logic devices require a very long process time and a great deal of effort.
This increases the cost of manufacturing these circuits and may slow down production of the terminal system.

Semi-custom gate array circuits are modified because the circuits are typically identical except for a few final i steps that are custom made according to the system's design specifications. It is cheaper and faster to do blush t1 wound 2ψ
Yo,)ゎ11. ” + -L- Because custom-made gate array circuits have less component density, they require a larger gate array circuit to provide a given amount of random logic compared to the custom-made circuits described above. shall be.

This programmable logic device lies between the extremes of general-purpose devices on the one hand, and between custom-made and semi-customized gate array circuits on the other hand. This programmable logic device is a flexible structure that can be programmed by the user through fuses or switches on the chip to perform specific functions for a given application. . Programmable logic devices are bought "unsold" like standard logic gates, but may soon become custom circuits such as gate array circuits.

To use this programmable logic, system designers must understand how the hardware will perform.
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Enter into the programming device of a bloody programmable logic device. An unprogrammed programmable logic device is inserted into the device, and the device translates the equations appropriate to the device to operate the programmable logic device that performs the desired logic function on the user's system. signals. Programmable logic devices typically include hundreds or thousands of fuses or switches, which are arranged in a matrix to facilitate their manufacture and programming.

Programmable logic devices traditionally program one bit at a time in serial fashion.

The main reason for this approach is that programmable logic devices have traditionally been widely made in bipolar technology, which requires large currents on the order of 30 mA to program multiple bits of data. Programming many bits in parallel wastes a lot of power.

In recent years, programmable logic devices based on erasable programmable read-only memory (EPROM) cells formed in CMOS (complementary MOS') technology have been introduced. . Such devices use 70-digit gate transistors as programmable logic device switches, which are programmed by hot electron effects. EPROM cells are erased by exposure to ultraviolet light, a time-consuming process. E
Another disadvantage of PROM-based programmable devices is that the backing of the device is prohibitively expensive, which drives up its cost because the quartz window for passing ultraviolet light is expensive. There is.

At least one EPROM-based programmable logic device on the modern market is explicitly used for "byte" programming, where eight programmable connections can be programmed simultaneously. be done. In these devices, in order to effectively program a large number of cells in parallel, each bit requires a current of 2IIIA to 10mA to program, which still wastes a large amount of power. That is clear. Data is programmed by selecting a column address and a row address and outputting the 8 bits of data to be programmed to the output of the device. A reasonable upper limit for preferred parallel programs is currently 8 bits in this technology.

The time required to program programmable logic devices is an important issue. Programmable logic devices using bipolar technology will achieve typical program times in the range of 0.5 seconds to 5 seconds for a 1-bit to 8-bit arrangement. Also, EPROM-based programmable logic devices have typical processing times ranging from about 40 seconds to 100 seconds for a 1-bit to 8-bit array, if "single-bit" programming is used. program time will be achieved. If “byte”
When the unit program is used, then ＾−+ ν2 l
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Another problem with known programmable logic devices concerns matching of output logic paths. A typical programmable logic device comprises a programmable array followed by a sense amplifier, a logic gate, and an output driver that is effectively placed at the output of the device. The exact configuration is configured depending on the particular device. A typical programmable logic device output structure includes an array, a sense amplifier, an OR gate, and an output register connected to the device's output pins. The output data at the output pin is the result of a certain product term in the array, as is the case for a certain memory.
rm) or does not have a one-to-one relationship with the data in the row. A typical method for determining whether an output device is operating correctly is to test by programming an array with a certain bit pattern to determine whether the output logic circuit is operating. If the bipolar fuse is destroyed and the program is obsolete, it is impossible to verify the operation of the output of the P-o-bear. It is also known to provide a test input to an OR gate to test its functionality, but this does not allow checking the operation of the sense amplifier or other OR gate inputs.

Although it is known to provide the function of high-speed fuse verification, to the best of Applicant's knowledge, the known technique uses a sense amplifier for isolated verification, thereby eliminating the need for normal user signals. Several different reference signal paths are provided from the path through the normally used sense amplifiers. Therefore, known techniques cannot verify the operation of commonly used sense amplifiers that may not work due to manufacturing defects. Still further, by using separate sense amplifiers with possibly different and different detection thresholds, different results can be derived. That is, a fuse-checked sense amplifier may detect a cell in an open, circuit condition, whereas a conventional logic sense amplifier may detect a cell in a closed circuit condition. 1
OBJECTS OF THE INVENTION It is therefore a principal object of the invention to provide a programmable logic device that is programmed at very high speed.

Another object is to provide a programmable logic device capable of fast verification of programmed data using conventional sense amplifiers.

Another object is to provide a programmable logic device having the ability to verify the operation of the device output logic device.

Yet another object is to provide an improved programmable logic device that can reduce power consumption and is reprogrammable by the manufacturer and the user.

Another object is to provide a programmable logic device using electrically erasable memory cells to store programmed data.

[Structures of the Invention] A novel program using electrically and electrically erasable memory cells that can be programmed or erased at high speed;
Possible logical devices are disclosed. In a preferred embodiment, the memory cells of the programmable logic device are Fowler-Nordheim memory cells.
It has a floating gate transistor which acts as a sensing element which is programmed and erased by the tunneling effect of eim. According to the invention, the programmable logic device comprises a serial register latch circuit (hereinafter referred to as an SRL circuit) connected to the product term line of the logic array to be programmed.

Input program data is serially input to the SRL circuit by a programming device at a relatively high clock frequency. The SRL circuit is used to store all data that is programmed into a particular column of cells in the device array. The column address information is used to select that particular column for programming data. Then, a 10 mm lung programmer is applied to the array to program all the cells in the column to open. Therefore, for a cell array of 3.2 columns and 64 rows, all 64 cells in one column of 32 columns are programmed simultaneously.

The present invention also provides an S
The use of the RL circuit is useful for checking array data at high speed. The state of each cell in its selected column can be sensed using conventional sense amplifiers, loaded into the SRL circuit in parallel, and then shifted out serially for external verification.

The present invention further allows each sense amplifier and output logic gate to be functionally effective and independent of the data in the array. Test data, such as a distinct array pattern, is serially loaded into the SRL circuit. Under the control of the logic test enable input, the SR
The data in the L circuit is output to the sense amplifier input. This distinct array pattern is then detected and amplified via conventional output logic circuitry comprising sense amplifier logic gates and output buffers and read out from the output pins of the device. Thus, data can be serially clocked out of the device and checked against logical outputs received on the output pins of the device. Thus, the present invention allows the output logic to be effectively independent of the data programmed in the array of devices.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention comprises a new programmable logic device that is used for high speed programming and verification using electrically erasable and programmable memory cells. The following description is set forth to enable any person skilled in the art to make and use the invention, and is directed to certain specific applications and their requirements. In the following description, so that the invention can be understood,
Many specific circuit details are described, including circuit diagrams, array cell circuits, and signal timing diagrams.

It will be clear that the invention may be practiced without reference to these certain specific circuit details. In other words, well-known circuit details and steps have not been described in detail so as not to obscure the present invention.

In FIG. 1, a simplified block diagram illustrating some of the principle features of the invention is disclosed. A typical array 10 includes a 32 column, 64 row, or 64 product term array of programmable memory cells. The cells are individually programmable during program mode depending on the state of the bit being programmed present in the cell.

According to the present invention, a 64-stage serial shift register latch circuit 30 is provided for each stage 1 of the SRL circuit.
-64 corresponds to that of array 10, respectively, rows 1-64
It is connected to the array IO as if it were connected to the array IO. Column decoder 20, which selects one of 32 columns, is used to select a particular column of the array during a program cycle.

The SRL circuit 30 includes a clock port 32, a serial data input port 34, a "logical ring test enable" port 36, and a serial data output port 38.

Each of the 64 individual stages of the SRL circuit has an array 1
0 to each of the 64 product terms. The 32 columns of array 10 are connected to the output of a column decoder 20 which selects one of the 32 columns. The address of the column to be programmed during a particular program cycle is selected by the state of column address gate bus 22. The clock frequency of the clock signal applied to the SRL circuit is, for example, I
It is MHz. Therefore, program data may be serially shifted into the SRL circuit at the clock frequency from a program device or a test head device which is an external device of the logic device. It takes less than 9 seconds to load 64 bits of data into the SRL circuit at a clock frequency of IMHz. When the SRL circuit is loaded with program instructions or data, the contents of the SRL circuit are
For example, during a program cycle of lO milliseconds, the array lO
is programmed into the 64 cells of the selected column. At this time, it is repeated for each column of the program column 10.

In this way, the present invention is arranged! 0 program can be executed very quickly. This compares to the 20 seconds or more required to program "one bit" in an EPROM-based programmable logic device.
The entire four-row cell array can be programmed in less than 1'/2 seconds.

The preferred embodiment of the invention uses CMOS technology. Here, the storage element of each cell comprises an electrically erasable and programmable floating gate field effect transistor using Fowler-Nordheim tunneling. Since these floating gate transistors require essentially no current to program, this technique can be extended to any number of rows. Thus, by using a programmable logic device using the present invention, programming time can be greatly reduced by orders of magnitude. The present invention includes a function for quickly verifying the contents of the array IO. The SRL circuit may be used to check the state of each cell of the array in a particular selected column. This data is loaded into the SRL circuit and can be serially shifted out of the SRL circuit via the "serial data output" port 38. As will be apparent to those skilled in the art, this programming device can easily be used to compare the content of the output data of the selected column with the desired data.

Another concept of the invention is illustrated in FIG. During logic test mode, data is serially loaded into the SRL circuit. Under the control of certain test inputs ("logic test enable"), data present in the SRL circuit is transmitted to the input of the sense amplifier. At this time,
The "distinct alignment pattern" is detected via conventional output logic and read out at the output pins of that device. Data can then be serially clocked out from the SRL circuit and checked against the logic output received on the output pin of the device. .

The technique allows the output logic level to be a reliable level using conventional sense amplifiers without the need to program an array pattern into the device.

This technology allows manufacturers to effectively
00% output logic circuit can be tested,
This is a very powerful feature.

FIG. 2 is a longitudinal cross-sectional view of an electrically erasable memory cell used in a preferred embodiment.

The cell includes a select transistor and a floating gate type transistor, such as a sense or memory transistor. This floating gate device converts the sense transistor into an enhancement
Forer-Nordheim tunneling is used to erase or increase the charge stored in the 70-ting gate for operation in either mode or depletion mode. Forer above
In order to create the Nordheim tunneling effect, the floating gate region 5 is insulated from the drain region N+ region 3 by a very thin oxide layer of, for example, 100 nm.

The selection transistor is formed by a polysilicon region 1 separated from N'''' regions 3 and 4 by an oxide layer. The polysilicon region l contains N implanted into the active area.
The gate electrode of the selection transistor has a source and a drain with N+ regions 3 and 4 formed by type impurities.

Programmable Logic Device - Normal Mode FIG. 4 is a logical block diagram illustrating the programmable logic device of the present invention in a normal user mode in FIG. 3. A preferred embodiment comprises an integrated circuit made using some CMOS technology. The physical layout of the circuit logic blocks of this programmable logic device is illustrated in FIG. In this way, the 32 to 64 cell arrangement in Figure 1 is
Two 32-by-32 sub-arrays 102 and 104 are shown in FIG. Higher aN-kaihi 1ri 11 Shinji 1) Kashi ζ 1-711 [-mu, r-l collection π-blind r↓
The array is separated into two half arrays using a column driver driven in the direction. This effect is mitigated by the four polysilicon column line delays. - Figure 4 (A), Figure 4 (B) and Figure 4 (C) are normal mode (Figure 4 (A)), editing mode (Figure 4 (B)) and logic test mode (Figure 4 (B)), respectively. 4(C) shows the functional pin layout of the device in FIG. 4(C). This preferred embodiment has eight used inputs (P2-P9
) and 8 user programmable bidirectional pins (
It is housed in a 20-pin package with PI3-Pi9). The Pi and pH pins are connected to the clock signal (CL
K) and an output enable signal (OE) to the logic circuit.

For normal operation, when the size of the AND matrix available to the user is 32 cases and 64 rows,
The actual size of the matrix will be larger due to some other features of the device. FIG. 6 shows the actual array shape used in this preferred embodiment.

Columns 0-32 contain the user area of the array. Column 33-
59 and 62 contain reserved array space. row 6
The length of zero is 82 bits and column 60 defines the output logic structure of the programmable logic device.

During normal user mode, pins P2-P9 are input ports and are connected to the column drivers via bus 106. In FIG. 3, each column of arrays 102 and 104 is connected to column driver 1 via buses 103 and 105.
Connected to 01.

One end of each row of cells or each product term in the array is connected to current limiting and row pull-up circuits 108 and 110.

The other ends of the rows of the array are connected to sense amplifiers +12 and 114 via buses 111 and 113, respectively. The sense amplifiers 112 and 114 connect to the SRL circuit 1 having a stage count of 32 bits via buses 1 and 117, respectively.
20 and 122. 18 than other columns in the array
In order to accommodate the column 60 of the array having more bit stages, SRL circuits 120a and 12 with 9 bit stages are used.
2a is selectively and serially connected to the SRL circuits 120 and 122, and also in parallel to the sense amplifier! 16 and 118.

SRL circuits 120 and 122 each have an output logic macro cell (hereinafter referred to as "OLMC") 124.12.
6.128.130.132, +34.136 and 13
Connected to B. Each OLMC output is connected to each output driver 1
42.144.146.148, I50.152.15
4 and 156. 9-bit SRL circuit 12
0a and I22a are connected to multiplexer 140.

8 pits.

The bus 160 is connected to the output of the output driver and the multiplexer! 40, and the multiplexer 140 is further connected to the column driver 101. Output drivers are also connected to output ports P12-P19.

Program sequence decoder 109, which normally does not operate in user mode, is illustrated in FIG.

FIG. 5 is a simplified block diagram of a typical OLMCl 24. In normal user mode, an 8-bit bus 125 is connected to the outputs of eight sense amplifiers associated with eight product terms in the oLMC. OLMC
can individually set the output signal of each device to an active high level or an active low level, either in a combined (asynchronous) manner or in a registered (synchronous) manner. A common output enable (OE) can be connected to all outputs, or separate inputs or product terms can be used to provide individual output enable control.

The various configurations of the programmable logic device are controlled by programming bits within the 82-bit architecture control word. architecture 7
The control bit ACO and the 8-bit AC1 bit command their output, which is the common OE terminal (pin 11), to be always wired on and wired off (as well as the input). Reifuna) A3” Yazu passed away■
To give an order. The architecture control bits also determine the source of the feedback terminal of the array via multiplexer 124i and select the output, either the combined output or the registered output, via multiplexer 124f. . Eight XOR bits each determine the polarity of each device output. The operation of the OLMC is obvious to those skilled in the art and no additional details are necessary.

The programmable logic devices illustrated in FIGS. 3 and 5 normally operate in user mode, where the device's I1
Data input/output to the 0 port is via the device's logic bus and is operated by a particular logic device that is activated to obtain the desired logic operation on the input signal.

The programmable logic device and array AND gate array is made using nonvolatile, reprogrammable EEPROM technology, and the AND gate array is replaced with a bipolar type fuse. The basic cell of the array comprises two transistors, a select transistor and a sense transistor, to form a user programmable "AND" matrix formed by 32 input lines and 64 product terms. , the cell is formed by repeating 2048 times.

- In FIG. 7, a simplified block diagram of four cells of a product term comprising sub-arrays 102 and 104 is disclosed. Line 233 comprises one of the 64 product terms and line 235 comprises the product term ground line for product term line 233. During normal user mode, line 235 is on the ground side of the device.

In the preferred embodiment, each product term is connected in parallel between the product term 233 and the product term ground line 235.
It has several cells. transistors 205 and 210
has one cell 200 connected to a product term 233. Transistor 210 comprises the "select" transistor or gate of the cell. In the normal user mode, each select transistor is gated by input data and selectively each sense transistor is connected to the product term ground line. For example, the input driver 215 is
Gated by an input signal 218, the true and complement column driver signals on lines 217 and 216 are connected to select transistors 221 and 210, respectively.
drive the gate. Thus, for example, if line 21
If the input signal on 8 is high level, selection transistor 221 is turned on and selection transistor 210 is turned off.

“Selection” in a product term in device edit mode
The function of the gate is to isolate the predetermined sense transistor from the high level programming voltage. For example, while in edit mode, only one cell out of 32 in a row will have its entire array set to the same state and will not receive any given input, except for "bulk" erases or programs, as described below. selected at the specified time. This selection is performed by column decoders 202, one of which is connected to the gate of each selection transistor of each cell. Pins 3-7 and 18 provide inputs to the column decoder and select one of the 32 columns to be edited during a particular edit cycle.

The second transistor in each cell provides the data storage (or sense) element for the cell.

The transistor comprises an electrically erasable floating gate field effect transistor. When the device is in enhancement mode, the gate threshold turn-on voltage is approximately +8 volts;
The gate threshold turn-on voltage is approximately -5 volts when the device is in depletion mode. Thus, for the cell 200 shown in FIG. 7, during normal user operation, the so-called interrogation voltage (+2.5 volts) at the matrix control gate ("MCG");
When floating gate transistor 205 is programmed into depletion mode, it is conductive, whereas when operating, it is not conductive. in this way,
While the programmable logic device is in normal user mode, the state of the sense transistor for each cell determines whether the corresponding input line for that column is connected to the product term.

While the programmable logic device is in edit mode, the input driver 215 is isolated from the array (by a switch not shown) by the E D 'r signal;
The column decoder is activated.

On the other hand, during normal operation of the programmable logic device, column decoder 220 is not activated and has no effect on device operation.

Product term line 233 is connected to the input of sense amplifier 250. Sense amplifier 250 includes inverters 251 and 252 and transistors 253-255. Load 256 forms a DC leakage bus from the sense amplifier input node 257 to ground.

The output 258 of sense amplifier 250 is connected to transistor 24
node 268 of stage 260 of the SRL circuit through
, whose transistor 240 is rendered conductive by the "verify" signal. The ground line 235 of the product term is
Stage 26 of the SRL circuit via transistor 225
0 node 271 and its transistor 225
becomes conductive by the P0M'' signal.

Stage 260 of the SRL circuit includes an inverter 263.2
64, 266 and 267, and transistors 262 and 265.
65 are a clock signal "5CLK" and an inverted clock signal "SCLπ," respectively.

becomes conductive. Therefore, when 5CLK is high, the data to stage 260 at input 261 is inverted and transmitted to node 269. At this time, 5CLK is at a low level and transistor 265 is non-conductive. When 5CLK goes low level,
Transistor 262 is turned off and 5CLK is at a high level, so transistor 265 is turned on.

At this time, the input of stage 260 is isolated and the inverted data is transmitted through the input to inverter 260.
It is inverted at 6. Therefore, while the clock signal is applied, the data applied to node 261 is transferred to output node 2.
71. As long as transistor 262 is non-conductive, the operation of inverter 267 causes data to be latched at this node 271. Shift register latch circuits are known in the art, and a typical reference is E.J. McCluskey (E.J.

McCluskey), 1984 1
The paper entitled ``A Survey of Designs for Test Capability Scanning Techniques'' was published in ``rVLsI Design'' in February.

Product term ground line 235 also connects transistor 275
to row pull-up circuit 280, and transistor 275 is rendered conductive by the "program" signal. Pull-up circuit 280 is a high impedance voltage source used to generate a programming voltage, e.g., +20 volts, that is high enough to program the floating gate transistors comprising the matrix cells. be. Such pull-up circuits are known in the prior art.

Programmable Logic Device Edit Mode FIG. 8 is a simplified block diagram of a programmable logic device in edit mode. When a certain super voltage, for example 20 volts, is applied to pin 2 of the device, a super voltage sense circuit comprising comparator 302 detects the super voltage and outputs a logic signal "EDT". The signal at pin 2 is also connected to a voltage transfer gate 304 which is at a high level, and the gate 304 is connected to the signal “P/
” and in response to the state of “Dingπ” at pin 11,
For example, a gate operation is performed to turn the program voltage VPP of 20 volts "on" or "off". As before, pump clock signals φ and φ are internal oscillator outputs;
Its internal oscillator output is connected to a diode-capacitor pump circuit for generating a high level voltage. The high level voltage is used as a gate signal output to the control gate 304 for passing the high level voltage. The “EDT” signal, which is at an active level, is also connected to driver 215 and
is the active level.3 by the “EDT” signal.
Set to state control. Therefore, the super voltage on pin 2
The programmable logic device goes from normal user mode to edit mode with different functions on all pins illustrated in FIG. 4(B). Inputs to pins 3-7 and 18 are used as select bits for column decoder 109 during edit mode. Further, in response to a control bit to gate 304,
Vl) is applied to the row pull-up column decoder and matrix controlled gate oscillator 306.

The reference numbers used in FIG. 8 indicate elements that correspond to the reference numbers shown in FIG.

Therefore, the individual sense amplifiers for each product term are represented by amplifier sections 114, 118, 116a and +12. The stages of the SRL circuit are 32 stages of SRL.
Sections 122 of the circuit are grouped into sections 121 of the 18-stage SRL circuit and 120 of the 32-stage SRL circuit.

Multiplexers 140a and 140b are dependent on architecture logic 310 to selectively convert serial data into 18
It outputs to section 121 of the bit's SRL circuit or to the circuitry around its succinct link 121. Therefore, column 60
Section 121 of the SRL circuit is bypassed except when SRL is accessed.

A "bulk erase" cycle is performed in this edit mode, which programs each floating gate transistor of the array cell to enhancement mode. To bulk "erase" or bulk program a user's array cells, a logical "CLR" signal is generated by select column 63. logic circuit 3
The gate of 18 is turned on by the "CLR" signal and data at the 5DIN port, and in response to the data at the 5DIN port, the bulk erase control signal "BE" is turned on.
or a bulk program control signal "BP". The CLR signal forces both 5CLK or (σLK) high, thereby opening the SRL circuit for immediate transmission of data at the 5DIN port through all stages of the SRL circuit.
Because specific data at the same logic level is loaded into the SRL circuit, there is no need to clock the data through registers.

To bulk erase that cell, that particular data is loaded into the SRL circuit and the "MCG" line is boosted to +20 volts. When logic signal [ goes low level, logic signal B is applied to make the MCG signal +20 volts.
E is connected to MCG oscillator 306. Then, in order to program all memory cells to an erased state, i.e., an enhancement mode state,
A normal program cycle is executed.

If the bulk erase cycle is completed, a program cycle can be performed. A particular column is activated and either causes its particular sense transistor to be programmed into a depletion mode or inhibits programming that would leave that particular sense transistor in an enhancement mode. Specific data is loaded into the SRL circuit for this purpose.

After the data is loaded into the SRL circuit, the "PGM" signal at the gate of transistor 225 is made an active signal, rendering gate transistor 225 conductive. To connect the row pull-up circuit to the product term ground, the "program" signal becomes a high level signal of, for example, +20 volts. If the data signal at node 271 is low, then the ground line 2 of the product term
35 is clamped to ground. This is because the "row pull-up circuit" has a high impedance voltage source and cannot supply enough current to boost its voltage level above ground potential. During the program cycle, the MCG signal is pulled to ground potential. Therefore, if that selected column cell has an voltage applied to both its gate and drain,
No voltage is induced that causes the Lennel effect.

Result It has a Ding-Sumi position. Also, between the gate and drain, the floating gate transistor of the cell is still in enhancement mode, as the electrode from the floating gate is removed.

If there is a data signal at node 271 that is at a "high" level during edit mode, the ground line of that product term will not be clamped to ground and will be at a high level, e.g., 20 volts -VT from the row pull-up source. A programming voltage of is applied to the drain of the selected floating gate transistor. Electrons flow from the floating gate to the drain by tunneling, thereby programming the transistor into debulsion mode. This programming voltage is applied for, for example, 10 milliseconds, which is the length of some conventional progera pulses.

To summarize the operation of the array during an edit mode program cycle, the "MCG" signal is taken to ground potential and transistor 225 is turned on by the "PGM" signal applied to its gate. Of the 32 cells on the side of the product term, only one cell is activated by applying a select signal to the selected transistor of that cell to cause its selected transistor to become conductive. It is said that Data in the SRL circuit is applied to the product term ground line. If the data signal is low, the product term ground line is at ground potential and the transistor is still in enhancement mode, requiring an increased gate voltage level to make the transistor conductive. be done. During normal circuit operation, the normal cell interrogation voltage is set low enough so that the floating gate transistor does not become conductive when it is in enhancement mode. On the other hand, if the data signal at the node 271 of the stage of the SRL circuit is at a "high" level, the electrons are sufficiently An electric field is applied between the gate and drain, thereby depleting the cell.
Program to mode.

Verification of Programmed Data Another novel concept in the disclosed programmable logic device is the ability to perform high speed verification of data stored on matrix cells. During this verification cycle, the same sense amplifiers used in the normal user operating mode of the device are used to detect the state of the array cells and perform parallel loading of the SRL circuits. During this mode, transistor 2
The "verify" signal applied to the gate of 40 (FIG. 7) is the active signal, so that transistor 240 is conductive and the output 258 of sense amplifier 250 and SR
Nodes 268 of corresponding stages of the L circuit are connected. At the same time, since the "PGM" and "5CLK" signals are at a low level, each stage of the SRL circuit is isolated from each other and from the ground line of each product term. When the “TU scratch signal is at high level,” node 26
The data signal at 8 is transmitted to the output node 271 of the SRL circuit stage.

During a program cycle, only one cell in each row of the array or line of product terms is selected at any given time during the match cycle. Accordingly, the data contents of the entire selected column of the matrix may be loaded in parallel into the stages of the interrogation SRL circuit of the matching cycle.

At this time, in order to turn off transistor 240 and isolate the sense amplifier from the SRL circuit, the "verify" signal is
becomes low level. At this time, the contents of the SRL circuit are SR
By making the L clock signal 5CLK an active signal, the device's 5DOUT port (pin 1
．． 2) may be serially shifted and output. For testing programmable logic devices, one field is used to perform comparisons between desired data.

Logic Circuit Matching Another new feature of programmable logic devices is that
It is a logic circuit verification function that provides virtually 100% testing of the functionality of the output logic circuits on the device in a non-destructive manner.

To perform matching, at least one cell in each product term must be in the conductive state. A "bulk program" operation may be used with all floating gate transistors in depletion mode. This operation is accomplished by loading the appropriate data into the 5DIN port of the device in an operation similar to that described for the bulk erase cycle. In the disclosed embodiment, column 63 is selected and all column decoders are set to 2 in user clear mode to select all columns.
It becomes high level which is 0 volts. In other words, “MCG”
The signal drops to ground potential. A normal program cycle is then executed.

If an array is bulk programmed to a conductive or "programmed" state, a well-defined array pattern is serially loaded into the SRL circuit, as described above for the program cycle.

This desired pattern may be varied to match certain logic paths through the sense amplifiers and output circuits. In order to match all logical paths, it is usually necessary to use multiple distinct alignment patterns.

By removing the supervoltage signal from pin 2, the operating mode of the device changes from the edit mode to the logic verification mode. The logic verification mode is selected by applying a super voltage to pin 3 of the programmable logic device, such that the "PGM" signal applied to the gate of transistor 225 becomes an active signal. Therefore, transistor 225 becomes conductive, and node 271 of the SRL circuit stage is connected to ground line 235 of the product term.

There is no need to program array cells with test bit patterns to verify logical paths. Since at least one data storage transistor of a cell in a particular product term is conducting, node 27 of the SRL circuit
A logic state at 0 appears at the input of sense amplifier 250 when transistor 225 is conducting. In this mode, transistor 240 is turned off.

In this manner, logic paths may be matched and numbered by comparing the "distinct array pattern" and the data at the output pins of the programmable logic device.

To summarize the sequence of steps for logic verification, at least one sense transistor per product term is programmed into depletion mode. At this time, the edit mode of the programmable logic device is set and the SRL circuit is loaded with the desired pattern. next,
Applying a super voltage to super voltage pin 3 of the programmable logic device takes the programmable logic device from edit mode to logic test mode.

The logical verification feature also allows for functional testing after the device has been programmed without changing the user data programmed into the array. At least one cell is programmed to depletion key for each available product term during a program cycle. Therefore, the distinct bit pattern loaded into the SRL circuit is transmitted through the conduction cells during the logic check mode and applied to the input of the product term sense amplifier. In this way, the output logic circuit may be tested, for example in an electric field, without reprogramming the device.

DEVICE WAVEFORM TIMING Referring to FIGS. 9-11, waveform timing charts illustrating the signal sequences for loading the contents of the array into the programming/verifying SRL circuit and verifying the operation of the output logic circuit are illustrated. . To load data into the SRL circuit, pin 20 is used as shown in Figure 9A.
vccp, where the signal VCC at is, for example, 5 volts.
EDIT applied to pin 2 after some time delay TDD to set the supply of vCC which is 20 ms
The edit mode of the device □ is set by boosting the signal from zero to the edit/verification supply level VE, which is, for example, 20 volts. During the loading sequence of the SRL circuit and also during the array program/verify sequence, vC
The C signal and EDIT signal are held at high level.

After the EDIT signal is established, 5DIN data is applied to pin 9, the serial data input port, for the device to be in edit mode. The 5D1N signal is illustrated at C in FIG. 9, and the 5DrN signal is loaded into the SRL circuit at a clock frequency determined by the 5CLK clock signal, illustrated at D in FIG. time interval T
D and PWV respectively indicate the pulse sequence delay and the verification pulse width, which is in the range of up to 1 microsecond, for example 5 microseconds. In this way, for each clock pulse, the summer bit data changes from S bits to N bits.
A load operation up to the fMth bit is shown.

E in FIG. 9 shows that the contents of the SRL circuit are serially output from the device via pin 12, which is the serial data output port. As shown at D and E in FIG. 9, when valid data exists at the rising edge of the 5CLK clock signal, that data is serially output. The (N-64)th to (N+M-64)th serial data are shown in E of FIG.

When the desired data is loaded into the SRL circuit, the 10th
As shown in the figure, the array column of a selected device is S
It may also be programmed in response to the contents of the RL circuit. 1st
As shown in A and B of the θ diagram, the VCC signal and EDIT
The signals are at boosted levels, VCCP and VE, respectively. Next, a valid column address RAGO-RAG5 is input to the column address gate (“RAG”) port, pins I8 and 3-7, to select the column of the matrix to be programmed with the contents of the SRL circuit. ing. In edit mode, the P/
In response to the state of the V'' control signal, data is retrieved from the SRL circuit during a program cycle, and/or the contents of a matrix are loaded into the SRL circuit for verification during a program cycle. D in FIG.
The figure shows the P/V signal in the "verification" state.

When a valid column address is input and the program/verify state is determined, for example, 10
The programming steps of the matrix are executed by bringing the STπ signal low for a program pulse width PWp, which is milliseconds. If the verification state is selected, the STR signal is only required to be brought to a low state for a verification pulse width of, for example, 5 microseconds, in order to load the data of the matrix into the stages of the SRL circuit. . D and C of FIG.
It shows the interrelationship between the V signal and the rτ signal.

When matrix data is loaded into the SRL circuit,
To isolate the SRL circuit from its product term sense amplifier, the contents of the SRL circuit may be output after the r-through signal has been brought to its high level state, for example. 5D of equipment
Regarding clock synchronization of OUT port data output
Illustrated at F and G in Figure 0. VCC signal and EDIT
The signals are still in their high state during this operation.

1st! The figure shows intermediate signal waveforms in the logic test mode. As shown in FIG. 11A, this mode is selected by boosting the LTE signal at pin 3 to +15 volts. As shown in FIG. 11B, PGM
The signal becomes high level, and the SRL circuit connects transistor 2.
25 to the ground line 235 of the product term.

Both the program signal and the verification signal go low and are output to the output logic circuit.

Logic circuitry internal to the programmable logic device is used to generate the "Verify", "PGM" and "Program Gate control signals applied to the gates of transistors 225, 240 and 275 in FIG. These signals are r under π signal,
P/v" signal, RAG signal, VCC signal, and EDIT signal. Therefore, in order to obtain the "program" signal and "PGM" signal, which are at high level, for example, the P/v signal must be at high level. Therefore, it is necessary that the 1st signal is at a low level.The circuits that output the appropriate "Verify", "Program" and "PGM" signals are omitted for the sake of brevity. , because experts in the field can easily design such circuits.

It is understood that the embodiments described above are merely illustrative of the many possible specific embodiments in which the principles of the invention may be employed. Many other variations in accordance with these principles can be readily devised by those skilled in the art starting from the six passages disclosed by the present invention.

[Effects of the Invention] As detailed above, according to the present invention, since the memory cell is equipped with an electrically erasable floating gate transistor, programming or erasing can be performed at a higher speed than in the conventional example. It is possible to realize a programmable logic device that can perform the following steps.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing a programmable logic device which is an embodiment of the present invention, and FIG. 2 is a block diagram showing an electrically erasable memory device used in the logic device of FIG. 3 is a block diagram of a programmable logic device operating in normal user mode, which is an embodiment of the present invention; and FIG. 4A is a block diagram of a programmable logic device which is a preferred embodiment of the present invention. FIG. 4(B) is a diagram showing the functional layout in normal mode of a 20-pin package used in a programmable logic device, which is a preferred embodiment of the present invention. FIG. 4C shows the functional layout in the logic test mode of a 20-pin package used in a programmable logic device according to a preferred embodiment of the present invention. Figure 5 is a block diagram of the output logic microcell used in the programmable logic device of Figure 3;
FIG. 7 is a diagram illustrating the configuration of an array used in the programmable logic device of FIG. 7, and FIG. FIG. 8 is a block diagram of a programmable logic device according to a preferred embodiment of the present invention in edit mode; FIG. 9 is a block diagram of a programmable logic device according to a preferred embodiment of the present invention. FIG. 1O is a timing chart for loading program data into a shift register latch circuit; FIG. Timing Chart FIG. 11 is a timing chart of a programmable logic device according to a preferred embodiment of the present invention in logic test mode. 1... Polysilicon region, 2.3.4... N2 region, 5... Floating gate region, 10... Array, 20... Column decoder for selecting one column from 32 columns, 22
...Column address gate bus, 30...Serial register latch circuit (SRL circuit), 32...Clock port, 34...Serial data input port 36...Logic test enable port, 38... ...Serial data output port, 101...Column driver, 102.104...Sub array, 108.110...Current limit and row pull-up circuit,
112.114,116,118... sense amplifier,
120.122... Serial register latch circuit (SRL circuit) with 32-bit stages, 120a, 122a... Serial register latch circuit (SRL circuit) with 9-bit stages, 124.126, 128, 130, 132, 134.1
36,138...Output logic microcell (OLMC)
, 124i, 124r = multiple converter, 140... multiple converter, 142.144, 146, 148, 150. ．． 152.
154, 156... Output driver, 200... Cell, 202... Column decoder, 205... Floating gate transistor,
210... Selection transistor, 215... Input driver, 220... Column decoder, 221... Selection transistor, 225... Transistor, 233... Product term line, 235... Product term line. Earth line, 240...Transistor, 250...Amplifier, 251.252...Inverter, 253.254,255...Transistor, 256...
...Load, 260...SRL circuit stage, 262.265...Transistor, 263.264, 266.267...Inverter, 2
75...Transistor, 280...Pull-up circuit, 302...Comparator, 304...High level voltage transfer gate, 306...
Matrix control gate oscillator, 310... architecture logic circuit, 318... logic circuit. Patent Applicant: Lattice Semiconductor Corporation

Claims (23)

[Claims] (1) a plurality of input lines, a plurality of product terms, a matrix of programmable cells selectively connecting each of the input lines to each of the product terms, and connecting the product terms to terminals of the device; a programmable logic device comprising an output logic circuit and an electrically erasable floating gate transistor capable of operating in either an enhancement mode or a depletion mode; The programmable cell includes an electrically erasable floating gate transistor using Fohler-Nordheim tunneling to transfer charge to and from the drain of the interrogation signal. A programmable logic device characterized in that when applied to the gate of a gated transistor, the transistor becomes conductive or non-conductive. (2) The programmable cell of claim 1, wherein the programmable cell further comprises a cell selection transistor whose state is controlled by each input line signal. logical device. (3) The programmable device according to claim 2, further comprising means for programming the floating gate transistor comprising the cell into either enhancement mode or depletion mode. logical device. 4. A programmable logic device according to claim 3, wherein said means for programming is used to program in parallel each cell connected to a selected input line. (5) The means for performing said programming comprises serial shift register means comprising a plurality of serially connected stages connected to corresponding product terms; A patent characterized in that it comprises means for loading stages of shift register means and means for applying a program voltage to said cells depending on the state of said data in each stage of said shift register means. A programmable logic device according to claim 4. (6) The means for programming comprises bulk erase means for simultaneously programming each floating gate transistor comprising a cell into an enhancement mode.
Programmable Logic Devices as described in Section. (7) The bulk erase means includes means for applying a high-level program voltage to the gate of the floating gate transistor, means for bringing each selection transistor into a conductive state, and a means for applying a high-level program voltage to the gate of the floating gate type transistor, and a means for making each of the selection transistors conductive. 7. A programmable logic device according to claim 6, further comprising means for connecting each drain of said floating gate transistor to earth. (8) A programmable logic device comprising a matrix of multiple rows and multiple columns of programmable cells for simultaneously programming cells in selected columns of said matrix to a predetermined state. A programmable logic device comprising programming means and collation means for detecting in parallel the states of cells comprising a selected column in said array. (9) The programming means is a serial program comprising a plurality of serially connected stages.
Shift register means and means for serially shifting into said shift register program data indicative of the state of each cell of a selected row to be programmed. A programmable logic device according to scope 8. (10) The programming means further comprises connection means for selectively connecting the stages of the shift register to the columns of cells of the matrix during a programming cycle of the device. Range 9th
Programmable Logic Devices as described in Section. (11) The collation means comprises the shift register means and a loading means for loading data indicating the state of a cell in a selected column into a corresponding stage of the shift register. A programmable logic device according to claim 9. (12) Each of said cells of said matrix includes a first transistor means used to select a cell for programming in response to a column address selection signal, and a first transistor means used for storing programmed information thereof. 9. A programmable logic device as claimed in claim 8, characterized in that it comprises second transistor means. (13) The programmable logic device further comprises an output circuit for connecting the rows of the matrix to an output port of the device, and the verification means further comprises means for verifying operation of the output circuit. 9. A programmable logic device as claimed in claim 8. 14. A programmable logic device according to claim 13, wherein said output verification means includes means for loading a distinct array pattern. (15) the output circuit comprises a sense amplifier for detecting the state of each cell in a selected column of the matrix; the collation means comprises a plurality of serially connected stages connected to each sense amplifier; Serial shift register means comprising serially connected stages, said collation means comprising means for outputting the contents of said stages of said shift register to said sense amplifier. 15. The programmable logic device of claim 14. (16) An improved programmable logic device used for high speed programming and verification comprising a matrix of programmable cells selectively connecting an input line to each product term and a plurality of sense amplifiers. an output circuit with each sense amplifier connected to each product term and an output logic device connected to an output port of the device and one input line in response to some predetermined program data pattern; and a cell verification means used to verify the programmed state of the cells connected to the selected input line. A programmable logical device that (17) said programming means includes serial shift register latch circuit means comprising a plurality of serially connected stages, each said stage being selectively connected to a corresponding one of said product terms; 17. The programmable logic device of claim 16, wherein program data is serially input to said serial shift register latch circuit means via a serial input data port of the device. (18) said programmable logic device further comprising a serial data output port, said collation means communicating with said serial register latch circuit means data indicative of the state of each cell in a selected column of said matrix; means for loading a corresponding stage of said serial register latch circuit means and then means for serially shifting the contents of the output of said serial register latch circuit means of a serial data port of said device; 18. A programmable logic device according to claim 17, comprising: (19) The programmable logic device further comprises output circuit matching means comprising means for inputting a distinct constellation pattern into an output circuit connected to a selected product term of the output matrix, thereby 17. The programmable logic device of claim 16, wherein the device output bit pattern output as is compared to a desired bit pattern. (20) A plurality of input lines, a plurality of product term lines, and each array of the programmable switch element array are connected to a predetermined line among the input lines and the product term line, an array of programmable switching elements provided for selectively connecting said input line to said product term depending on the state; and a plurality of detection means each connected to each said product term to determine the state of said product term. a plurality of detection means used to detect the sense amplifier; an output logic circuit used to connect the output of the sense amplifier to a terminal of the device; and a plurality of detection means used to verify the operation of the detection means and the output logic means. 1. An improved programmable logic device comprising: means for verifying a program. (21) said matching means comprises means for outputting a distinct array of bit patterns to an input of said detection means, whereby said bit patterns are detected in their operating state via said sense amplifier and said output logic; 21. A programmable logic device as claimed in claim 20, characterized in that the programmable logic device is transmitted in a dependent manner. (22) The verification means is used to verify the operation of the sense amplifier and the output logic circuit means without requiring the switch element to be programmed. Programmable logical device. (23) The verification means comprises a plurality of serially connected stages, each of the plurality of serially connected stages being selectively connected to the corresponding detection means in response to a control signal, and 23. A programmable logic device according to claim 22, further comprising means for loading stages of said shift register means.