JPS61216464A - Monolithic integrated element of photodiode and transistor - Google Patents
Monolithic integrated element of photodiode and transistorInfo
- Publication number
- JPS61216464A JPS61216464A JP60057806A JP5780685A JPS61216464A JP S61216464 A JPS61216464 A JP S61216464A JP 60057806 A JP60057806 A JP 60057806A JP 5780685 A JP5780685 A JP 5780685A JP S61216464 A JPS61216464 A JP S61216464A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- transistor
- epitaxial growth
- buried
- buried layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052796 boron Inorganic materials 0.000 abstract description 11
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 11
- 239000011574 phosphorus Substances 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 description 22
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 230000008685 targeting Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は受光ダイオードとトランジスタの集積素子に関
する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an integrated device of a light receiving diode and a transistor.
（従来の技術）
従来、受光ダイオードとその光検出電流を増幅するため
のトランジスタを四−チップ内に形成するモノリシック
型の集積素子において、受光ダイオードの光検出電流を
大きくとるためには、光検出活性層を対象とする光の波
長に応じである値以上に厚くとる必豊かあるが、トラン
ジスタのエミッタ直下のコレクタ領域の厚さは、スイッ
チング速度を速くするためにはある値以下に薄くする必
要がある。このように同一基板上にこの基板と異なる導
電型の光活性領域とコレクタ領域とを厚さをかえて形成
する方法としては、従来二′Ｎ埋込拡散法が行なわれて
いた。とζろが、前記二重埋込拡散法では、トランジス
タ部のコレクタ領域の厚さを、必要な専さに抑えておき
ながら受光ダイオード部の光活性領域の厚さを充分厚く
することは困難である。この仁とを図面を用いて説明す
る。(Prior art) Conventionally, in a monolithic integrated device in which a photodetector diode and a transistor for amplifying its photodetection current are formed in a four-chip device, in order to increase the photodetection current of the photodetector diode, photodetection Although it is necessary to make the active layer thicker than a certain value depending on the wavelength of the light targeted at it, the thickness of the collector region directly under the emitter of the transistor needs to be thinner than a certain value in order to increase the switching speed. There is. As a method for forming a photoactive region and a collector region of different conductivity types on the same substrate with different thicknesses, the 2'N buried diffusion method has conventionally been used. However, with the double buried diffusion method described above, it is difficult to increase the thickness of the photoactive region of the photodetector diode sufficiently while suppressing the thickness of the collector region of the transistor to the required thickness. It is. This will be explained using drawings.
第２図は従来の受光ダイオードとトランジスタのモノリ
シック集積素子の一例の断面図である。FIG. 2 is a cross-sectional view of an example of a conventional monolithic integrated device of a light receiving diode and a transistor.
Ｐ型シリコン基板ｌｌｃ、まずアンチモン（ｓｂ）を拡
散してＳｂ埋込層２を形成し、充分基板１側にｓｂを押
し込んだ後、他の領域に８ｂ埋込層３を形成する。その
後で、Ｎ−のエピタキシャル成長層４を形成する。次に
受光ダイオード部とトランジスタ部を電気的に絶縁する
Ｐ 絶縁拡散層５と受光ダイオードのＮ＠電極用コンタ
クト拡散層６蓬びにトランジスタのコレクタ用コンタク
ト拡散層７を形成する。その後、受光ダイオードのＰ＋
層８とトランジスタのＰｆｆｉペース９を形成し、最後
にトランジスタのＮ型エミッタ１０を形成する。On the P-type silicon substrate llc, first, antimony (SB) is diffused to form an Sb buried layer 2, and after sb is sufficiently pushed into the substrate 1 side, an 8B buried layer 3 is formed in another region. After that, an N- epitaxial growth layer 4 is formed. Next, a P insulating diffusion layer 5 for electrically insulating the light receiving diode section and the transistor section, a contact diffusion layer 6 for the N@ electrode of the light receiving diode, and a contact diffusion layer 7 for the collector of the transistor are formed. After that, P+ of the photodiode
The layer 8 and the Pffi paste 9 of the transistor are formed, and finally the N-type emitter 10 of the transistor is formed.
上述のように形成した従来法の集積素子の受光ダイオー
ド部Ｐとトランジスタ部のｓｂ埋込層の濃度プロファイ
ルの一例を第３図に示す。第３図の中でＮｐ及びＮｒが
それぞれ受光ダイオード部及びトランジスタ部の埋込層
２．３の濃度プロファイルである。第３図はＮ−エピタ
キシャル層厚が６μｍの場合を示し、受光ダイオード部
の埋込層２のｓｂの濃度プロファイルのピーク値が、ト
ランジスタ部よシも３μｍ基板側にせシさがりている。FIG. 3 shows an example of the concentration profile of the sb buried layer of the light receiving diode section P and the transistor section of the conventional integrated device formed as described above. In FIG. 3, Np and Nr are the concentration profiles of the buried layer 2.3 of the light receiving diode section and the transistor section, respectively. FIG. 3 shows a case where the thickness of the N-epitaxial layer is 6 μm, and the peak value of the concentration profile of sb in the buried layer 2 of the light-receiving diode portion is lowered by 3 μm toward the substrate side than the transistor portion.
従って、エピタキシャル層表面から９μｍのＳｂ濃度プ
ロファイルのピーク位置までが受光ダイオードの光活性
領域□として利用できる。Therefore, the area from the surface of the epitaxial layer to the peak position of the Sb concentration profile of 9 μm can be used as the photoactive region □ of the light receiving diode.
（発明及解決しようとする問題点）
ところが、短波長の光、例えばガリウムアルミニウムヒ
素発光ダイオードの光（ピーク波長０，６６ｎｍ）を対
象とする場合には、受光ダイオードの光活性領域は９μ
ｍ程度あれば、入射光の大部分のエネルギーを有効に光
電流として利用できるが、ビーク波長０．７７ｎｍの発
光ダイオードを光源としたときＫは、入射光を充分に利
用するには光活性領域が２０μｍ必要である。しかしな
がら、前述の従来法では、トランジスタ部のコレクタ領
域厚さを６μｍＫ保ったままで、受光ダイオード部の光
活性領域の厚さを２０μｍＫすることは不可能である。(Problems to be Invented and Solved) However, when targeting short wavelength light, for example, light from a gallium aluminum arsenide light emitting diode (peak wavelength 0.66 nm), the photoactive area of the light receiving diode is 9 μm.
If K is about 100 m, most of the energy of the incident light can be effectively used as photocurrent, but when a light source is a light emitting diode with a peak wavelength of 0.77 nm, K is the photoactive region required to fully utilize the incident light. is required to be 20 μm. However, in the conventional method described above, it is impossible to increase the thickness of the photoactive region of the photodetector diode portion to 20 μmK while maintaining the thickness of the collector region of the transistor portion to 6 μmK.
本発明の目的は、従来の欠点を除去し、受光ダイオード
部の光活性領域を充分厚く形成して光検出電流を大きく
シ、トランジスタのエミッタ直下の」レクタ領域の淳さ
を薄くしてスイッチング速度を速くすることのできる受
光ダイオードとトランジスタの集積素子を提供すること
にある。The purpose of the present invention is to eliminate the conventional drawbacks, to increase the photodetection current by forming the photoactive region of the photodetector diode sufficiently thickly, and to increase the switching speed by reducing the thickness of the rector region directly under the emitter of the transistor. An object of the present invention is to provide an integrated device of a light receiving diode and a transistor that can speed up the process.
（問題点を解決するための手段）
本発明の受光ダイオードとトランジスタのモノリシック
受光素子は、第１導電型の半導体基板と、該半導体基板
上に形成された第２導電型の第１エピタキシヤル成長島
と、該第１エピタキシャル成長層と前記半導体基板の接
合部に形成され＠１エピタキシャル成長層よシも比抵抗
の低い第２導電型の第１埋込層と、前記第１エピタキシ
ャル成長層上に形成された第２導電型の第２エピタキシ
ャル成長層と、該第２エピタキシャル成長層と前記第１
エピタキシヤル成長場の接合部に形成され第２エピタキ
シャル成長層よシも比抵抗が低゛くかつ前記第１埋込層
が形成されてない上層部に形成された＃Ｉ２細込層と、
前記第１埋込層上の第２エピタキシャル成長層中に形成
されたＰ−Ｎ接合型受光ダイオードと、前記第２埋込層
上の第２°エピタキシヤル成長層中に形成されたトラン
ジスタと、前記受光ダイオード部とトランジスタ部を電
気的に絶縁する第１導電型の絶縁領域とを含んで構成さ
れる。(Means for Solving the Problems) A monolithic light receiving element of a light receiving diode and a transistor of the present invention includes a semiconductor substrate of a first conductivity type and a first epitaxial growth of a second conductivity type formed on the semiconductor substrate. an island, a first buried layer of a second conductivity type formed at a junction between the first epitaxial growth layer and the semiconductor substrate and having a lower resistivity than the @1 epitaxial growth layer, and a first buried layer formed on the first epitaxial growth layer. a second epitaxial growth layer of a second conductivity type; the second epitaxial growth layer and the first epitaxial growth layer;
an #I2 fine layer formed at the junction of the epitaxial growth field, having a resistivity lower than that of the second epitaxial growth layer, and formed in the upper layer where the first buried layer is not formed;
a P-N junction type light receiving diode formed in a second epitaxial growth layer on the first buried layer; a transistor formed in a second epitaxial growth layer on the second buried layer; It is configured to include a first conductivity type insulating region that electrically insulates the light receiving diode section and the transistor section.
（実施例）
□次に１本発明の実施例について図面を用いて説明する
。(Example) Next, an example of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
比抵抗２０〜４０Ω−αのｒ型シリコン基板１１にＳｂ
を拡散して層抵抗２０．５０／口の第１８ｂ埋込層１２
を形成し、次にホウ素の）を拡散して層抵抗１８Ω／口
のホウ素埋込層１３を形成し、次にリン（乃を拡散して
層抵抗２０Ω／口のリン埋込層１４を形成する。その後
、比抵抗２Ω−α、厚さ１４μｍのＮ型第１エピタキシ
ャル成長層１５を形成する。次に層抵抗２０゜５Ω／口
の第２８ｂ埋込層１６を形成する。その後、前述の第２
８ｂ埋込層の形成が完了した第１エピタキシャル成長層
１５上に第１エピタキシャル成長層と同じ比抵抗（２Ω
−ｃｍ）で厚さ６μｍの第２エピタキシャル成長層１７
を形成する。Sb on the r-type silicon substrate 11 with a specific resistance of 20 to 40 Ω-α
18b buried layer 12 with a layer resistance of 20.50/hole
, then diffuse boron () to form a boron buried layer 13 with a layer resistance of 18 Ω/hole, and then diffuse phosphorus (boron) to form a phosphorus buried layer 14 with a layer resistance of 20 Ω/hole. Thereafter, an N-type first epitaxial growth layer 15 with a specific resistance of 2 Ω-α and a thickness of 14 μm is formed.Next, a 28b buried layer 16 with a layer resistance of 20°5 Ω/hole is formed. 2
8b The same resistivity as the first epitaxial growth layer (2Ω
-cm) and 6 μm thick second epitaxial growth layer 17
form.
次に、受光ダイオード部とトランジスタ部を電気的に絶
縁する丸めの絶縁ホウ素拡散層１８とダイオードのＮ側
電極用並びにトランジスタの；レクタ電極用のコンタク
トリン拡散層１９を形成する。なお絶縁ホウ素拡散層１
８と埋込ホウ素層１３は、それぞれ拡散せシ下シとせシ
上、ＤＫよシ連結される。また、トランジスタ部のコン
タクトリン拡散層１９は拡散せシ下ＤＫよシ第２８ｂ埋
込層１６と連結される。またダイオード部のコンタクト
リン拡散層１９とリン埋込層１４はそれぞれ拡散せり下
シとせシ上シによシ連結される。Next, a round insulating boron diffusion layer 18 for electrically insulating the light receiving diode section and the transistor section and a contact phosphorus diffusion layer 19 for the N-side electrode of the diode and the rector electrode of the transistor are formed. Note that the insulating boron diffusion layer 1
8 and the buried boron layer 13 are connected to the bottom and top of the diffusion lines and the DK, respectively. Further, the contact phosphorus diffusion layer 19 of the transistor portion is connected to the 28b buried layer 16 below the diffusion layer DK. Further, the contact phosphorus diffusion layer 19 and the phosphorus buried layer 14 of the diode portion are connected by the lower diffusion groove and the upper groove, respectively.
前述の絶縁ホウ素拡散並びにコンタクトリン拡散工程の
完了後ホウ累拡散によシダイオードのＰ＋層２０とトラ
ンジスタのベース領域２１を同時に形成し、その後リン
拡散によシエミッタ２２を形成する。なお、ダイオード
部のＰ 層２０及びトランジスタ部のベース２１の表面
撫度はＩ Ｘ １０ｆ−ｃ１１″″Ｓで、Ｐ−Ｎ接合深
さは素子裏面から１μｍである。After completing the above-described insulating boron diffusion and contact phosphorus diffusion steps, the P+ layer 20 of the diode and the base region 21 of the transistor are simultaneously formed by boron diffusion, and then the emitter 22 is formed by phosphorus diffusion. Note that the surface roughness of the P layer 20 of the diode section and the base 21 of the transistor section is Ix10f-c11''''S, and the P-N junction depth is 1 μm from the back surface of the element.
上記実施例の受光ダイオードの内部量子効率は、波長０
．７４μｍ並びに０．９４μｍの場合、それぞれ９０％
、３０％である。これに対して、従来法の一例の受光ダ
イオードの内部量子効率は、それぞれ７４％、１７％で
あル、本発明によれば、トランジスタ部のスイッチング
特性を劣化させることなしに受光ダイオードの内部量子
効率を大幅に改善できる。The internal quantum efficiency of the light receiving diode of the above example is
．． 90% for 74μm and 0.94μm respectively
, 30%. On the other hand, the internal quantum efficiency of the photodiode according to the conventional method is 74% and 17%, respectively. According to the present invention, the internal quantum efficiency of the photodiode can be reduced without deteriorating the switching characteristics of the transistor section. Efficiency can be significantly improved.
（発明の効果）
以上説明したように１本発明によれば、受光ダイオード
部の光活性領域を充分厚く形成でき、トランジスタのエ
ミッタ直下のコレクタ領域の厚さを薄くでき、光検出電
流を大きくシ、トランジスタのスイッチング速度を速く
することのできる受光ダイオードとトランジスタの七ノ
リシック集積素子を得ることができる。(Effects of the Invention) As explained above, according to the present invention, the photoactive region of the photodetector diode can be formed sufficiently thick, the collector region directly under the emitter of the transistor can be thinned, and the photodetection current can be greatly shunted. , it is possible to obtain a seven-nolithic integrated device of a photodiode and a transistor that can increase the switching speed of the transistor.
第１図は本発明の一実施例の断面図、第２図は従来の受
光ダイオードとトランジスタのモノリシック集積素子の
一例の断面図、第３図は従来の受光ダイオードとトラン
ジスタのそノリシック集積素子の受光ダイオード部とト
ランジスタ部のアンチモン埋込層の濃度プロファイルを
一例を示す濃度分布図である。
１・・・・・・Ｐ型シリ；ン基板、２・・・・・・ｓｂ
埋込層、３・・・・・・ｓｂ埋込層、４・・・・・・Ｎ
−エピタキシャル成長層、５・・・・・・Ｐ 絶縁拡散
層、６・・・・・・コンタクト拡散層（受光ダイオード
Ｎ側電極用）、７・・・・・・コンタクト拡散層（トラ
ンジスタのコレクタ用）、８・・・・・・Ｐ 層、９・
・・・・・Ｐ型ベース、１０・・・・・・Ｎ型エミッタ
、−１１・・・・・・Ｐ型シリコン基板、１２・・・・
・・第１８ｂ埋込層、１３・・・・・・ホウ素埋込層、
１４・・・・・・リン埋込層、１５・・・・・・Ｎｌｉ
第１エピタキシャル成長層、１６・・・・・・第２Ｓｂ
埋込層、１７・・・・・・Ｎ型第２エピタキシャル成長
層、１８・・・・・・絶縁ホウ素拡散層、１９・・・・
・・コンタクトリン拡散層、２０・・・・・・Ｐ”層、
２１・・・・・・ＰＭベースｓ ２２・・・・・・Ｎ’
ｇｚミッタ。
・ｌ〕パ、−一
＼ＪンFIG. 1 is a cross-sectional view of an embodiment of the present invention, FIG. 2 is a cross-sectional view of an example of a conventional monolithic integrated device of a light receiving diode and a transistor, and FIG. 3 is a cross-sectional view of an example of a conventional monolithic integrated device of a light receiving diode and a transistor. FIG. 3 is a concentration distribution diagram showing an example of concentration profiles of antimony buried layers in a light receiving diode section and a transistor section. 1...P type silicon substrate, 2...sb
Buried layer, 3...sb Buried layer, 4...N
-Epitaxial growth layer, 5...P Insulating diffusion layer, 6...Contact diffusion layer (for photodetector diode N-side electrode), 7...Contact diffusion layer (for transistor collector) ), 8...P layer, 9.
... P type base, 10 ... N type emitter, -11 ... P type silicon substrate, 12 ...
... 18th b buried layer, 13... boron buried layer,
14...phosphorus buried layer, 15...Nli
First epitaxial growth layer, 16...2nd Sb
Buried layer, 17... N-type second epitaxial growth layer, 18... Insulating boron diffusion layer, 19...
...Contact phosphorus diffusion layer, 20...P'' layer,
21...PM base s 22...N'
gz mitta.・l〕Pa, -1\Jn
Claims (1)
た第２導電型の第１エピタキシャル成長層と、該第１エ
ピタキシャル成長層と前記半導体基板の接合部に形成さ
れ第１エピタキシャル成長層よりも比抵抗の低い第２導
電型の第１埋込層と、前記第１エピタキシャル成長層上
に形成された第２導電型の第２エピタキシャル成長層と
、該第２エピタキシャル成長層と前記第１エピタキシャ
ル成長層の接合部に形成され第２エピタキシャル成長層
よりも比抵抗が低くかつ前記第１埋込層が形成されてな
い上層部に形成された第２埋込層と、前記第１埋込層上
の第２エピタキシャル成長層中に形成されたＰ−Ｎ接合
型受光ダイオードと、前記第２埋込層上の第２エピタキ
シャル成長層中に形成されたトランジスタと、前記受光
ダイオード部とトランジスタ部を電気的に絶縁する第１
導電型の絶縁領域とを含むことを特徴とする受光ダイオ
ードとトランジスタのモノリシック集積素子。A semiconductor substrate of a first conductivity type, a first epitaxial growth layer of a second conductivity type formed on the semiconductor substrate, and a first epitaxial growth layer formed at a junction between the first epitaxial growth layer and the semiconductor substrate, A first buried layer of a second conductivity type with low resistance, a second epitaxial growth layer of a second conductivity type formed on the first epitaxial growth layer, and a junction between the second epitaxial growth layer and the first epitaxial growth layer. a second buried layer formed in an upper layer portion having a resistivity lower than that of the second epitaxially grown layer and on which the first buried layer is not formed; and a second epitaxially grown layer on the first buried layer. a P-N junction type light receiving diode formed therein, a transistor formed in a second epitaxial growth layer on the second buried layer, and a first transistor electrically insulating the light receiving diode part and the transistor part.
1. A monolithic integrated device of a light receiving diode and a transistor, characterized in that the device includes a conductive type insulating region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60057806A JPS61216464A (en) | 1985-03-22 | 1985-03-22 | Monolithic integrated element of photodiode and transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60057806A JPS61216464A (en) | 1985-03-22 | 1985-03-22 | Monolithic integrated element of photodiode and transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61216464A true JPS61216464A (en) | 1986-09-26 |
Family
ID=13066161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60057806A Pending JPS61216464A (en) | 1985-03-22 | 1985-03-22 | Monolithic integrated element of photodiode and transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61216464A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62202567A (en) * | 1986-02-28 | 1987-09-07 | Canon Inc | Optical sensor and manufacture of the same |
| JPS63122164A (en) * | 1986-11-11 | 1988-05-26 | Pioneer Electronic Corp | Optical sensor integrated circuit |
| US5252851A (en) * | 1991-01-30 | 1993-10-12 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit with photo diode |
| EP0576009A1 (en) * | 1992-06-25 | 1993-12-29 | Sanyo Electric Co., Limited. | Optical semiconductor device and fabrication method therefor |
-
1985
- 1985-03-22 JP JP60057806A patent/JPS61216464A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62202567A (en) * | 1986-02-28 | 1987-09-07 | Canon Inc | Optical sensor and manufacture of the same |
| JPS63122164A (en) * | 1986-11-11 | 1988-05-26 | Pioneer Electronic Corp | Optical sensor integrated circuit |
| US5252851A (en) * | 1991-01-30 | 1993-10-12 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit with photo diode |
| EP0576009A1 (en) * | 1992-06-25 | 1993-12-29 | Sanyo Electric Co., Limited. | Optical semiconductor device and fabrication method therefor |
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