JPS61216031A - Detection system for operand overlap - Google Patents

Abstract

PURPOSE:To detect an operand overlap by providing an address arithmetic unit with a two-input subtracting function and calculating the difference between the 1st and the 2nd operand addresses, and using a 0 detector for the high-order three bytes and a large/small comparator for the least significant byte. CONSTITUTION:When an SS type variable-length instruction is executed, the address computing element AA4 performs subtraction between the 1st and the 2nd operand addresses. The high-order three bytes of the result are inputted to the 0 decision device 23 and the least significant byte is inputted to the comparator. When the output of the 0 decision device 23 is 1, the high-order three bytes are all 0 and the 1st and the 2nd operand addresses are at a distance of <=256 bytes, so that three is the possibility of overlapping. When the output of the 0 decision device 23 is 0, both operand addresses are at a sufficiently long distance, so they never overlap each other. Further, the comparator 24 decides whether the difference between the 1st and the 2nd operand addresses is smaller than the length of the 2nd operand or not, and when the output of the 0 decision device 23 is 1 and the output of the comparator 24 is also 1, decision device 10 decides that the operands overlap each other.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the detection of operand overlap.

[Background of the invention]

As shown in FIG. 3, the operand overlap check when pipeline processing is performed will be explained below using the MYσ instruction, which is an SS type decimal instruction, as an example. ,
In the case of the MVσ instruction, the operands are processed from right to left. Therefore, the operand overlap (hereinafter abbreviated as σML) check is necessary when the unprocessed bytes of the compressed 2 operands are subjected to such heavy load that they are destroyed, as shown in Figure 4. . In Fig. 4.

a is the start address of the 1lE1 operand, b is the end address of the first operand, X is the start address of the second operand, Y is the end address of the @2 operand, and OV
L is obtained when X≦b≦Y.

Conventionally, a σVL check circuit has a configuration shown in FIG. In the figure, 1 is an index value register (hereinafter abbreviated as MAR) where an index value is held, 2 is a pace value register (hereinafter abbreviated as BAR) where a base value is held, and 3 is a pace value register (hereinafter abbreviated as BAR) where a base value is held.
is a displacement value register (hereinafter abbreviated as DR) in which a displacement value is held; the instruction is decoded in the decode stage (D1 stage), and the above BAR is stored at the end of the DI stage.

Data is placed in XAR and DR. In the M1 stage, the above BAR, XAR, and DR are added by the address arithmetic unit 4 (hereinafter abbreviated as FAA), and the obtained first operand final address is placed in the destination address register 6 (hereinafter abbreviated as DAR). be done. M1 above
At the same time as the stage, on the D2 stage, the above XAR, BAR
.

The data of the DRK second operand is set.

Furthermore, in the M2 stage, the above-mentioned XAR and BAR.

DR is added by AA, and lease address register 5 (hereinafter SA) is added as the final address of the second operand.
In the fifth-order A2 stage, which is placed in
The SAR and DAR are compared by the comparator 7, and the first comparison result is placed in the register 9. At the same time
&CO is set, BAR set at D2 stage,
DR is added by AA to find the start address of the second operand. Then, in the L2 stage, the first address of the second operand and the last address of the first operand in the DAR are compared by the comparator 8, and the comparison result by the comparator 8 and the first address held in the register 9 are compared. Based on the comparison result, the determination circuit 10 determines
VL is determined and 7-15 In this method, the operand address is compared twice, so a register is required to hold the first comparison data, and the comparator requires a large amount of hardware. There's a problem.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for detecting success-operand overlaps that significantly reduces the hardware required for detecting operand overlaps without degrading performance.

[Summary of the invention]

The present invention provides an address arithmetic unit with a two-man subtraction function, and calculates the difference between the second operand and the first operand in the next stage after the first and second operand addresses are determined by SS instruction processing. This book makes it possible to detect operand overlap by simply comparing once the upper three bytes of the subtraction result with the operand length of the least significant byte.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

The same parts as in FIG. 2 are designated by the same reference numerals. A detailed explanation will be omitted, and only the parts that are different from FIG. 2 will be explained. In this example.

Selectors 20 and 21 are placed at the input of AA, and the M stage (
(modification stage), each XAR
, BAR. o In the A2 stage, SAR, DAR are selected to perform the subtraction of the second operand and the first operand. Since the direction of subtraction differs depending on the instruction, the direction of subtraction is also controlled by the selectors 20 and 21. Further, in the case of OVL, since the upper three bytes of the subtraction result are O, the comparator is a 0 determiner 23 that determines that the upper three bytes are all O.

Comparator 24 that compares the lower 1 byte of the subtraction result with LEN
The operand length holding register 22, which consists of OVL, determines the range of OVL detection, which differs depending on the instruction and processing method.

Next, the operation of one embodiment of the present invention will be explained using the Mvσ instruction as an example.In the sD1 stage (decode stage), the instruction code is decoded, and the instruction code is X A R, BAR.

Data is sectored into each register of the DR. In the Ml stage, selectors 20 and 21 are XAR and BAR.

It is controlled to select the upper MAR.

The values of BAR and DR are added by AA to find the first operand address. The addition result is.

Set in DAR. At the same time, XAR, BAR.

The data of the DRK second operand is set.

The second operand address is calculated by AA in the next M2 stage. The above addition result is set as SAR. At the next stage (A2 stage) where the first and second operand addresses are determined, the selectors 20, 2
1 is each SAR.

Controlled to select DAR, AAKSAR・DA
The value of R is input. At this time, DR data is ignored,
A subtraction is performed between SAR and DARO. The upper 3 bytes of the above subtraction result go to the 0 determiner 23, and the least significant 1 byte goes to the comparator 24. If the output of the 0 determiner is 1, that is, the top 3
If all bytes are O, the distance between the first and second operand addresses is within 256 bytes!
This indicates that there is a possibility of overlap. When the output of the above 0 determiner is O.

In other words, if the upper three bytes are not O, this indicates that the two operand addresses are far enough apart that they do not overlap. Also.

The comparator 24 determines whether the difference between the first operand address and the second operand address is smaller than the second operand length, and the output of the 0 determiner 23 is 1.
and - if the output of the comparator 24 is 1, then the 1 determiner 1
0, it is determined that the operands overlap.

This method is also effective when the address space wraps around. The problem with processing the 1MVσ instruction when the address space wraps around is the first
The operand address is close to the maximum value of the address space.

This is the case when the second operand address takes a value close to the minimum value of the address space. in this case.

If the addresses are simply compared in size, the first operand address and the second operand address are significantly different, so it is determined that they do not overlap. However, in the one-line formula, the first operand address is subtracted from the second operand address, so the relative shift between the two operands is determined, and the operand address is calculated using the same method as when the address space does not wrap around.・Can detect overlaps. An example of this method has been explained using a data processing device that performs pipeline processing with a pitch of 1 machine cycle, but it is also possible to detect overlaps using a data processing device that performs pipeline processing with a pitch of 2 machine cycles or more. It can also be applied to data processing equipment.

〔Effect of the invention〕

As detailed above, there are two operations according to the present invention.

The overlap detection method can simplify the detection circuit without any performance deterioration compared to the conventional method, and is therefore advantageous in reducing costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. Fig. 2 is a block diagram showing a conventional example, Fig. 3 is an explanatory diagram showing the flow of σV L @ output processing in pipeline processing, and Fig. 4 is an explanatory diagram showing the case of σVL in M Vσ instruction. . 1... Index value register. 2...Pace value register. 4... Address calculator, 7.8... Comparator. 9... Work 1/Jister, 10... Judgment circuit. 20, 21...Selector. 22... Operand length register. 23...0 judger, 24...comparator. Figure 1 Figure 2

Claims (1)

[Claims] A 1- or 4-byte arithmetic unit, a detection circuit that detects that the upper 3 bytes of the arithmetic unit output are 0, and a difference between the lower 1 byte of the arithmetic unit output and the first operand length or second operand length. In a computer equipped with a comparator for comparison, when executing an SS type variable length instruction, the above arithmetic unit is used to calculate the difference between the first operand address and the second operand address, and the upper 3 bytes are 1. An operand overlap detection method, characterized in that operand overlap is detected by using a 0 detector and a magnitude comparator for the least significant 1 byte.