JPS61214825A - High frequency power amplifying circuit - Google Patents
High frequency power amplifying circuitInfo
- Publication number
- JPS61214825A JPS61214825A JP5713685A JP5713685A JPS61214825A JP S61214825 A JPS61214825 A JP S61214825A JP 5713685 A JP5713685 A JP 5713685A JP 5713685 A JP5713685 A JP 5713685A JP S61214825 A JPS61214825 A JP S61214825A
- Authority
- JP
- Japan
- Prior art keywords
- high frequency
- signal
- circuit
- level control
- frequency signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Transmitters (AREA)
- Control Of Amplification And Gain Control (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、TDMA通信地上局相互で行うルーラル通信
等における送信機等で用いられる高周波電力増幅回路に
関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a high-frequency power amplification circuit used in a transmitter or the like in rural communication between TDMA communication ground stations.
(従来の技術)
第8図は従来のこの種の高周波電力増幅回路のブロック
図である。この電力増幅回路で送信出力信号がバースト
スイッチングにより他の送信チャンネル或は、自局の受
信チャンネルに悪影響を及ぼす程にスペクトラムが拡が
るのを抑えるために、出力波形を制御する。スペクトル
の拡がりが少ない出力では、包絡線の立上がり及び立下
りがなだらかであり、第7図にこのような好ましい包絡
線の一例を示す。第8図の高周波電力増幅回路において
、λカレベル制御回路10は入力高周波信号121にレ
ベル制御信号104に応じて減衰を加え、減衰高周波信
号110を出力する。増幅器2は、減衰高周波信号11
0を電力増幅して高電力高周波信号102を出力する。(Prior Art) FIG. 8 is a block diagram of a conventional high frequency power amplifier circuit of this type. This power amplifier circuit controls the output waveform in order to prevent the spectrum of the transmission output signal from expanding to the extent that it adversely affects other transmission channels or the reception channel of the own station due to burst switching. In an output with little spectral spread, the envelope curve has gentle rises and falls, and FIG. 7 shows an example of such a preferable envelope curve. In the high frequency power amplifier circuit shown in FIG. 8, the λ level control circuit 10 attenuates the input high frequency signal 121 according to the level control signal 104, and outputs an attenuated high frequency signal 110. The amplifier 2 attenuates the high frequency signal 11
0 is power amplified and a high power high frequency signal 102 is output.
検波器3は、高電力高周波信号102を包絡線検波し、
包絡線信号103を出力する。基準包絡線信号発生回路
5は、第7図の波形の正側半分又は負側半分の如き直流
の基準包絡線信号105を発生する。基準包絡線信号1
05は包絡線信号103として望まれる波形である。比
較回路4は、包絡線信号103と基準包絡線信号105
との電波差の波形のレベル制御信号104を出力する。The detector 3 performs envelope detection of the high power high frequency signal 102,
An envelope signal 103 is output. The reference envelope signal generating circuit 5 generates a DC reference envelope signal 105 having a positive half or a negative half of the waveform shown in FIG. Reference envelope signal 1
05 is a waveform desired as the envelope signal 103. The comparison circuit 4 outputs an envelope signal 103 and a reference envelope signal 105.
A level control signal 104 having a waveform of a radio wave difference between the two and the same is output.
レベル制御信号104は、基準包絡線信号105に対す
る包絡線信号103の誤差を現わす。第8図の回路は、
このように閉ループを構成し、高電力高周波信号102
の包絡線が基準包絡線信号105の波形に相似になるよ
うに作動する。Level control signal 104 represents the error of envelope signal 103 relative to reference envelope signal 105. The circuit in Figure 8 is
In this way, a closed loop is constructed, and the high power high frequency signal 102
The waveform of the reference envelope signal 105 is similar to the waveform of the reference envelope signal 105.
第9図は入力レベル制御回路10の回路図である。従来
の入力レベル制御回路は、本図に示すように、入力端子
31と出力端子32との間に2つのピンダイオード15
が直列に接続してあった一本図の回路では、第3図に特
性図を示す如く、ある程度のバイアス値に達するまでは
ピンダイオード15はオンせずあるバイアス値に達した
場合に急にオンするというヒステリシスをもっている。FIG. 9 is a circuit diagram of the input level control circuit 10. As shown in this figure, the conventional input level control circuit has two pin diodes 15 between an input terminal 31 and an output terminal 32.
In the circuit shown in the figure, in which the pin diode 15 is connected in series, the pin diode 15 does not turn on until it reaches a certain bias value, and suddenly turns on when it reaches a certain bias value, as shown in the characteristic diagram in Figure 3. It has hysteresis to turn on.
そこで、入力レベル制御回路10への入力高周波信号1
21がヒステリシスの領域にかかると、ピンダイオード
15が急にオンとなり電力増幅器2への入力レベルが急
激に増加するので、電力増幅器2の出力102の波形は
第5図に示される如く高電力高周波信号102の包絡線
の立上り波形が急峻となりその結果出力102のスペク
トラムが拡がってしまう。Therefore, input high frequency signal 1 to input level control circuit 10
21 enters the hysteresis region, the pin diode 15 suddenly turns on and the input level to the power amplifier 2 rapidly increases, so the waveform of the output 102 of the power amplifier 2 becomes a high-power, high-frequency waveform as shown in FIG. The rising waveform of the envelope of the signal 102 becomes steep, and as a result, the spectrum of the output 102 expands.
(発明が解決しようとする問題点)
従来、このスペクトラムの拡がりを抑えるために、ヒス
テリシス領域を避けるように制御信号104のレベルを
調整していたが、ピンダイオード15を完全にオフにで
きないので、高電力高周波信号102の包絡線は第6図
のような波形となる。そこで、従来の回路ではバースト
オン時とバーストオフ時のキャリヤリーク比のダイナミ
ックレンジがとれなかった。このように、従来の高周波
電力増幅回路には、高周波信号のバーストスイッチング
時におけるスペクトラムの拡がりが大きいという問題点
があった。(Problem to be Solved by the Invention) Conventionally, in order to suppress the spread of this spectrum, the level of the control signal 104 was adjusted to avoid the hysteresis region, but since the pin diode 15 could not be completely turned off, The envelope of the high power high frequency signal 102 has a waveform as shown in FIG. Therefore, in conventional circuits, it was not possible to maintain a dynamic range of the carrier leak ratio during burst-on and burst-off. As described above, the conventional high frequency power amplifier circuit has a problem in that the spectrum spreads greatly during burst switching of the high frequency signal.
そこで、本発明の目的は、高周波信号のバーストスイッ
チング時におけるスペクトラムの拡がりが小さい高周波
電力増幅回路の提供にある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a high-frequency power amplifier circuit in which the spectrum spread is small during burst switching of high-frequency signals.
(問題点を解決するための手段)
前述の問題点を解決するために本発明が提供する手段は
、入力高周波信号にレベル制御信号に応じた減衰を与え
て減衰高周波信号を出力する入力レベル制御回路と、こ
の減衰高周波信号を増幅して高電力高周波信号を出力す
る増幅器と、この高電力高周波信号を検波してその高電
力高周波信号の包絡線信号を出力する検波器と、前記包
絡線信号として望まれる包絡線を表わす基準包絡線信号
を発生ずる回路と、前記包絡線信号と前記基準包絡線信
号との波形の相違を表わす前記レベル制御信号を生ずる
比較回路とからなる高周波電力増幅回路であって、前記
入力レベル制御回路は前記入力高周波信号の入力端子と
前記減衰高周波信号の出力端子との間に直列に接続した
シリコンダイオードとピンダイオードとを備えることを
特徴とする。(Means for Solving the Problems) In order to solve the above problems, the present invention provides an input level control system that applies attenuation to an input high frequency signal according to a level control signal and outputs an attenuated high frequency signal. a circuit, an amplifier that amplifies this attenuated high frequency signal and outputs a high power high frequency signal, a detector that detects this high power high frequency signal and outputs an envelope signal of the high power high frequency signal, and the envelope signal. A high frequency power amplification circuit comprising: a circuit for generating a reference envelope signal representing a desired envelope; and a comparison circuit for generating the level control signal representing a difference in waveform between the envelope signal and the reference envelope signal. The input level control circuit is characterized in that it includes a silicon diode and a pin diode connected in series between an input terminal for the input high frequency signal and an output terminal for the attenuated high frequency signal.
(実施例)
次に、本発明の実施例について、図面を参照して説明す
る。第1図は本発明の一実施例を示すブロック図である
。この実施例では、基準包絡線信号発生回路5が発生す
るなだらかな立上りおよび立下り波形をもつ基準包絡線
信号105に従って、電力増幅器2への入力101が入
力レベル制御回路1によって制御され、さらに増幅器2
の出力102は検波器3によって包絡線検波され、検波
器3の出力103は、比較回路4によって、基準包絡線
信号発生回路5の出力105と比較され、両者の誤差信
号がレベル制御信号104として入力レベル制御回路1
に入力されて動作するという閉ループを構成し、電力増
幅器2の出力信号102の包絡線波形が基準包絡線信号
発生回路5の出力信号105と相似となるように制御さ
れることによって、バーストスイッチング時における出
力102のスペクトラムの拡がりを抑えている。(Example) Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In this embodiment, the input 101 to the power amplifier 2 is controlled by the input level control circuit 1 in accordance with the reference envelope signal 105 having gentle rising and falling waveforms generated by the reference envelope signal generating circuit 5, and 2
The output 102 of the detector 3 is subjected to envelope detection, and the output 103 of the detector 3 is compared with the output 105 of the reference envelope signal generation circuit 5 by the comparison circuit 4, and the error signals of both are used as the level control signal 104. Input level control circuit 1
The envelope waveform of the output signal 102 of the power amplifier 2 is controlled to be similar to the output signal 105 of the reference envelope signal generation circuit 5, thereby forming a closed loop in which the output signal 102 of the power amplifier 2 is input to The spread of the spectrum of the output 102 is suppressed.
本実施例における入力レベル制御回路1は、第2図に回
路図で示すように点接触型のシリコンダイオード6と2
段のピンダイオード7とを入力端子31と出力端子32
間に直列に接続して構成しており、従来のピンダイオー
ド2段で構成された入力レベル制御回路10と比較して
、点接触型のシリコンダイオード6を追加することによ
って、第4図に特性図で示すようにヒステリシスが大幅
は軽減されている。The input level control circuit 1 in this embodiment includes point contact type silicon diodes 6 and 2, as shown in the circuit diagram in FIG.
The stage pin diode 7 and the input terminal 31 and output terminal 32
By adding a point contact type silicon diode 6, compared to the conventional input level control circuit 10 consisting of two stages of pin diodes, the characteristics shown in FIG. As shown in the figure, hysteresis has been significantly reduced.
このように、本実施例を用いれば、比較回路4からのレ
ベル制御信号104によって、ピンダイオードをオンか
らオフに近い状態まで制御できるので、高電力高周波信
号102は包絡線波形が第7図に示す如くになる。第7
図の如き包絡線波形の高電力高周波信号102は、スペ
クトラムの拡がることのない、なめらかな立上り、立下
り波形をもち、バーストオン時とバーストオフ時との出
力比のダイナミックレンジが十分にとれている。In this way, if this embodiment is used, the level control signal 104 from the comparator circuit 4 can control the pin diode from an on state to a nearly off state, so that the envelope waveform of the high power high frequency signal 102 is as shown in FIG. It will be as shown. 7th
The high-power high-frequency signal 102 with an envelope waveform as shown in the figure has smooth rising and falling waveforms without spectrum expansion, and has a sufficient dynamic range of the output ratio between burst-on and burst-off. There is.
(発明の効果)
以上説明したように、本発明によれば、高周波信号のバ
ーストスイッチング時におけるスペクトラムの拡がりが
小さく、ひいてはバーストオン・オフした時のキャリヤ
リーク比を大幅に改善した高周波電力増幅回路が提供で
きる。(Effects of the Invention) As explained above, according to the present invention, the high frequency power amplifier circuit has a small spread of the spectrum during burst switching of high frequency signals, and further improves the carrier leak ratio during burst on/off. can be provided.
第1図は本発明の一実施例を示すブロック図、第2図は
第1図実施例における入力レベル制御回路の具体例を示
す回路図、第3図は従来の入力レベル制御回路の制御信
号に対する出力レベルの特性を示す図、第4図は第2図
の入力レベル制御回路の制御信号に対する出力レベルの
特性を示す図、第5図及び第6図は従来の高周波電力増
幅回路における高周波出力の包絡線波形の例を示す図、
第7図は、第4図実施例における高周波出力の包絡線波
形の例を示す図、第8図は、従来の高周波電力増幅回路
の一例を示すブロック図、第9図は第8図の従来の高周
波電力増幅回路における入力レベル制御回路を示す回路
図である。
1.10・・・入力レベル制御回路、2・・・増幅器、
3・・・検波機、4・・・比較回路、5・・・基準包絡
線信号発生回路、6・・・シリコンダイオード、7,1
5・・・ビンダオード、8・・・制御信号印加回路、9
・・・コイル。
代理人弁理士 本 庄 伸 介
第1図
第3図 第4図
第5図
第6図
第7図
第8図FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of the input level control circuit in the embodiment of FIG. 1, and FIG. 3 is a control signal of a conventional input level control circuit. Figure 4 is a diagram showing the output level characteristics for the control signal of the input level control circuit in Figure 2. Figures 5 and 6 are the high frequency output of a conventional high frequency power amplifier circuit. A diagram showing an example of the envelope waveform of
7 is a diagram showing an example of the envelope waveform of the high frequency output in the embodiment shown in FIG. 4, FIG. 8 is a block diagram showing an example of a conventional high frequency power amplifier circuit, and FIG. FIG. 2 is a circuit diagram showing an input level control circuit in the high frequency power amplifier circuit of FIG. 1.10... Input level control circuit, 2... Amplifier,
3... Detector, 4... Comparison circuit, 5... Reference envelope signal generation circuit, 6... Silicon diode, 7, 1
5... Bindaode, 8... Control signal application circuit, 9
···coil. Representative Patent Attorney Shinsuke Honjo Figure 1 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8
Claims (1)
減衰高周波信号を出力する入力レベル制御回路と、この
減衰高周波信号を増幅して高電力高周波信号を出力する
増幅器と、この高電力高周波信号を検波してその高電力
高周波信号の包絡線信号を出力する検波器と、前記包絡
線信号として望まれる包絡線を表わす基準包絡線信号を
発生する回路と、前記包絡線信号と前記基準包絡線信号
との波形の相違を表わす前記レベル制御信号を生ずる比
較回路とからなる高周波電力増幅回路において、前記入
力レベル制御回路は前記入力高周波信号の入力端子と前
記減衰高周波信号の出力端子との間に直列に接続したシ
リコンダイオードとピンダイオードとを備えることを特
徴とする高周波電力増幅回路。an input level control circuit that applies attenuation to an input high frequency signal according to a level control signal and outputs an attenuated high frequency signal; an amplifier that amplifies this attenuated high frequency signal and outputs a high power high frequency signal; a detector for detecting and outputting an envelope signal of the high-power high-frequency signal; a circuit for generating a reference envelope signal representing an envelope desired as the envelope signal; and the envelope signal and the reference envelope signal. and a comparator circuit that generates the level control signal representing a difference in waveform between A high frequency power amplification circuit characterized by comprising a silicon diode and a pin diode connected to.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5713685A JPS61214825A (en) | 1985-03-20 | 1985-03-20 | High frequency power amplifying circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5713685A JPS61214825A (en) | 1985-03-20 | 1985-03-20 | High frequency power amplifying circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61214825A true JPS61214825A (en) | 1986-09-24 |
JPH0446491B2 JPH0446491B2 (en) | 1992-07-30 |
Family
ID=13047142
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5713685A Granted JPS61214825A (en) | 1985-03-20 | 1985-03-20 | High frequency power amplifying circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61214825A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63136429U (en) * | 1987-02-25 | 1988-09-07 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57211835A (en) * | 1981-06-23 | 1982-12-25 | Kokusai Electric Co Ltd | Automatic electric power controlling circuit for transmitter |
JPS5999851A (en) * | 1982-11-29 | 1984-06-08 | Nec Corp | Signal control circuit |
-
1985
- 1985-03-20 JP JP5713685A patent/JPS61214825A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57211835A (en) * | 1981-06-23 | 1982-12-25 | Kokusai Electric Co Ltd | Automatic electric power controlling circuit for transmitter |
JPS5999851A (en) * | 1982-11-29 | 1984-06-08 | Nec Corp | Signal control circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63136429U (en) * | 1987-02-25 | 1988-09-07 |
Also Published As
Publication number | Publication date |
---|---|
JPH0446491B2 (en) | 1992-07-30 |
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