JPS61214024A - Bit buffer device - Google Patents

Abstract

PURPOSE:To transmit data with high efficiency by switching the stage position of a shift register which delivers an output when the double reading or misreading is caused by a bit slip through a selection circuit. CONSTITUTION:If the count value Qm of a counter CNTR 4 is defined as (a) in a normal state, the output Qa of a shift register SR 2 is selected and delivered by a selector SEL 3. Here the input UPEN of the counter CNTR 4 is set at '1' with the count value Qm of the CNTR 4 set equal to (a+1) if a writing slip occurs. Thus the output of the SEL 3 is changed to Qa+1 from Qa of the register SR 2. Therefore the data DOUT' delivered with the timing set before said change of the output is also delivered with the timing obtained after the change. Thus the same data is read twice to the DOUT', and the misreading due to a bit slip at the writing side is corrected. As a result, the original data format is not broken although a bit error occurs.

Description

[Detailed Description of the Invention] [Summary] The read side of a bit buffer device is configured with a shift register, and when a bit is read twice or misread, that is, a bit slip occurs between the write side and the read side. , change the output stage of the shift register to delete or insert bits.

Correct bit slip by restoring the number of bits.

[Industrial application field]

The present invention relates to a pit buffer device, and particularly to a bit buffer that has a timing conversion function that can correct the bit, throat, and slip knobs and transfer data in a transmission system where the phases of a write clock and a read clock are asynchronous. Regarding circuits.

[Conventional technology]

Conventionally, there has been a bit buffer device that can convert the timing of data for jitter within one bit, but for jitter larger than that.

Most pit buffer devices suffer from bit slips, that is, data bits are missed or read twice.

FIG. 2 shows an example of the configuration of such a conventional bit buffer device.

In the figure, 21 to 27 are D-type flip-flops FF, 28 is an AND gate 129 and 30 are delay circuits DLY for delay time t1 and L2, respectively, DIN is bit-serial input data, DOUT is bit-serial output data, WCK is a write clock, RCK is a read clock, TCK is a transfer lock, WSLIP is a write slip detection signal, R3LIP is a read slip detection signal, and RES is a reset signal.

FF21. FF22. FF23 constitutes a bit buffer stage, FF24 to FF27 . AND gate 28. D
LY29. DLY30 constitutes a buffer control circuit with a hitslip detection function.

The operation is as follows. First, input data DIN is written into the FF 21 using the write clock WCK.

Next, after both WCK and read clock RCK rise, FF2
Transfer the output of 1 to FF22 and turn it into FF by secondary RCK.
23.

At this time, by the reset signal R3E generated after the delay time L2 set by the delay circuit D+, Y30.

Since FF24 to FF27 are reset, TCK is (
The clock has a pulse width of t++tz).

However, the rising edge of TCK lags behind WCK, and the jitter is within ±1 bit.

It will be faster than the next RCK. Therefore, in this case,
The data written with WCK is transferred with TCK, and the data written with WCK is transferred with RCK.
is read out.

When the jitter exceeds ±1 bit, it operates in a first-order manner. To explain using the operation example shown in FIG. 3, the input data DIN currently written to the FF 21 by WCK is assumed to be D3. Before the next TCK occurs.

In other words, before RCK rises, WCK rises again due to jitter.
The next input data D4 is written into the FF21.

Therefore, the data D3 written earlier is.

It is lost before being transferred to FF22. On the other hand.

Since WCK is input to FF25 before FF24 is reset, the "1" output of FF24 is written to FF25, and the
F25 outputs “1” and write slip signal WSL
Set IP to 1''. This allows detection of a bit slip condition occurring on the writing side.

Next, to explain using the operation example shown in FIG. 4, F
When the data read to F23 is D2, the secondary RCK is generated before TCK is generated, that is, before WCK rises.
If this occurs, the same data D2 will be read out to the FF 23 again. In this case, the same data will be read twice, but RCK is input to FF27 before FF26 is reset.

FF27 outputs “1” and read slip signal R3L
Since IP becomes "1", a bit slip state on the read side can be detected.

[Problem that the invention seeks to solve]

If such a hitslip occurs in the bit buffer, if data is being transmitted with frame synchronization, there is a possibility that all subsequent received data will have bit shifts and errors. There is. Therefore, it was necessary to take measures such as initializing frame synchronization based on the detected WSLIP and R3LIP.

Means for Solving Problem c] The present invention provides a conventional bit buffer device having a bit slip detection function, in which the register on the read side is configured with a shift register, and the bit slip causes double reading or reading failure. Sometimes, by switching the stage position of the output shift register using a selection circuit, the data bits are deleted or inserted and the bits are corrected.

[Effect]

According to the bit buffer device of the present invention, even if a bit is read twice in the bit buffer or is read incorrectly due to pip 1 to slip, the output stage position of the shift register on the read side is switched in the opposite direction.

Corrections are made by deleting or inserting bits.

As a result, the number of bits on the write side and the number of pins on the read side of the pin I-buffer device always match.

Even if transmission is performed using frame synchronization, a frame synchronization error will not occur (however, the bit value will be erroneous), and there is no need to initialize frame synchronization.

〔Example〕

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. In the figure, 1 is a bit buffer BB that allows jitter up to ±1 bit, 2 is an n-stage shift register SR, and 3 is an n-stage shift register.
Selector SEL.

4 is an m-bit counter CNTR whose full count value is n;
5 is a D-type flip-flop FF, DIN is input data, DOUT and DOUT' are output data, WC
K is write clock, RCK is read clock, TCK
is transfer lock, WST-IP is write slip signal,
R3LIP is a read slip signal.

The bit buffer BB1 is illustrated in FIG. 2 as a conventional bit buffer device.

Therefore, DIN, DOUT, WCK, RCK.

The signals TCK, WSLTP, and R3LTP are used here with the same meaning.

The output data DOUT of the bisothofa sofa BBI is set as the input data SD of the shift register SR2, and is continuously shifted and inputted to the SR2. Each of the n-stage outputs 01 to Q of SR2 is connected to the n output of selector 5EL3, and Q1 to Q
, is selected by the count value Q0 of CNTR4.

In CNTR4, the up enable UPEN is set to “1” by the read clock RCK input to the clock input CK.
When ゛°, count amplifier, down enable DNE
This is an up/down counter that performs a countdown operation when N is "1".However, UPEN and D
If both NENs are “0”, they are not counted and both are 1
The state of "' is a prohibited input. R3LIP output of bit buffer BBI is set to down enable DNB of CNTR4.
5 to N, and connect the WSLIP output to TCK and the output written to FF5 to amplifier enable UPBH.

In the normal state, if the count value QII of CNTR4 is a, the output Q8 of SR2 is selectively outputted from 5EL3 (1≦a≦n). If a write bit slip occurs here, UPEN of CNTR4 becomes "1" and count value Q7 of CNTR4 becomes a+]. As a result, the output of S E I-3 is changed from Q8 of SR2 to Qs
Switch to +1.

Therefore, the data DOUT output from BBI at the timing before switching is also output at the timing after switching, and the same data is read twice to DOUT'. This corrects reading errors caused by bit slips on the writing side, and although bit errors occur, the original data format is not destroyed.

Similarly, when a bit slip occurs on the read side,
Set the Karan I value Q1 of CNTR4 from a to a-1, and 5
By switching the EL3(7) input side to SR2117)Q, -,
Remove ~ and correct the data read twice.

Try to preserve the original data format.

In addition, focus errors caused by focus slip correction are
Treated as a data transmission error.

FIG. 5 shows an example of the operation when a bit slip occurs on the writing side. It is assumed that counter CNTR4 in FIG. 1 is in a state of count value Q, and output Qa of shift register SR2 is selected by selector SR3 and is operating.

Here, D3 of the input data DIN is written by WCK and before being read by the secondary TCK.

WCK occurs again due to jitter and D4 is written.

D3 is lost. However, with WCK at this time, the write slip signal WSLIP becomes "1", then FF5 is set in synchronization with TCK, and the up enable UPEN of the counter CNTR4 becomes "1".

As a result, the count value of CNTR4 at the secondary RCK is Q.
, changes to Q a + 1, and the selector S E I-
3 to change the output of shift register SR2 from Q, l to Q a + +. As a result DOUT', after Dl is read from 08 of shift register SR2, Qa. Dl is read again from 1 and after 3, Q,
1 to Dl, D4. D5. D6. . . . The data is read out.

Therefore, Dl is inserted in place of the lost data DI, and the missing bits are corrected. but.

Since Dl and Dl are arranged instead of Dl and D3 on the bit array, they become error bits.

FIG. 6 shows an example of operation when a hit slip occurs on the read side. In this case as well, the counter CNT
R4 outputs the count value Qll.

It is assumed that the output Q1 of the shift register SR2 is selected by the selector 5EL3.

Here, Dl is written with WCK, internally transferred with secondary TCK, and then Dl is written as output data D0UT with primary RCK.
is read out, but writing of the next D3 is delayed due to jitter, and RCK occurs before D3 is transferred by TCK.
Dl is read out again.

It will be read twice.

However, with RCK at this time, the read slip signal R3L
This is because IP becomes "1" and down enable DNEN of counter CNTR4 turns ON.

At the next RCK, CNTR4 changes from Qa to Q.

7 shift register SR2 by controlling selector 5EL3
Switch the output from Q3 to Qa-1.

As a result, as DOUT', from Q of SR2 to D8
After reading Qa-, skip 1 bit and read Dl
, and thereafter D2. D3. D4. Read out...

Therefore, the DOU has been read twice and has increased by 1 hit.
DO that deletes 1 bin 1~ from T and matches the number of bits
UT' is obtained. However, as shown in Figure 5, Dl is placed instead of DI, resulting in an error bit.

Note that the number of stages n of the shift register SR2 is appropriately set in consideration of the number of consecutive bit slips that may occur in the same direction within one data transmission unit.

〔Effect of the invention〕

According to the present invention, the original data format can be maintained even if a bit slip occurs.

When transmitting data with frame synchronization,
No pseudo-synchronization pull-in or out-of-synchronization occurs. Further, since processing such as initialization of frame synchronization is unnecessary, efficient data transmission is possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a device according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional device, FIG. 3 is a timing diagram of a write bit slip operation in a conventional device, and FIG. 4 is a diagram of a conventional device. Timing diagram for read bit slip operation, No. 5
The figure is a timing diagram of the write focus slip operation of the device according to the embodiment of the present invention. FIG. 6 is a timing diagram of the read bit slip operation of the device according to the embodiment of the present invention. In FIG. 1, 1 is a bit buffer BB, 2 is a shift register SR, 3 is a selector SEL, and 4 is a counter CN.
TR,5 represents a flip-flop FF.

Claims (1)

[Claims] A bit buffer (1) that is controlled by a write clock and a read clock whose phases are asynchronous and has a bit slip detection function, and a predetermined multi-stage shift register connected to the read side of the bit buffer (1). (2), and a selection circuit (3) that selects one of the multiple stages of the shift register (2) as an output stage.
and extracts data from the selection circuit, and when the bit buffer (1) detects a bit slip, controls the selection circuit (3) to change the output stage of the shift register and perform bit correction. Characteristic bit buffer device.