JPS61213933A - 論理評価回路 - Google Patents

論理評価回路

Info

Publication number
JPS61213933A
JPS61213933A JP60054072A JP5407285A JPS61213933A JP S61213933 A JPS61213933 A JP S61213933A JP 60054072 A JP60054072 A JP 60054072A JP 5407285 A JP5407285 A JP 5407285A JP S61213933 A JPS61213933 A JP S61213933A
Authority
JP
Japan
Prior art keywords
holding memory
address
bus
cpu
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60054072A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0411892B2 (enExample
Inventor
Hironobu Asai
浅井 浩暢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ando Electric Co Ltd
Original Assignee
Ando Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ando Electric Co Ltd filed Critical Ando Electric Co Ltd
Priority to JP60054072A priority Critical patent/JPS61213933A/ja
Publication of JPS61213933A publication Critical patent/JPS61213933A/ja
Publication of JPH0411892B2 publication Critical patent/JPH0411892B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP60054072A 1985-03-18 1985-03-18 論理評価回路 Granted JPS61213933A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60054072A JPS61213933A (ja) 1985-03-18 1985-03-18 論理評価回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60054072A JPS61213933A (ja) 1985-03-18 1985-03-18 論理評価回路

Publications (2)

Publication Number Publication Date
JPS61213933A true JPS61213933A (ja) 1986-09-22
JPH0411892B2 JPH0411892B2 (enExample) 1992-03-02

Family

ID=12960412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60054072A Granted JPS61213933A (ja) 1985-03-18 1985-03-18 論理評価回路

Country Status (1)

Country Link
JP (1) JPS61213933A (enExample)

Also Published As

Publication number Publication date
JPH0411892B2 (enExample) 1992-03-02

Similar Documents

Publication Publication Date Title
US4788683A (en) Data processing system emulation with microprocessor in place
US6557119B1 (en) Microcomputer debug architecture and method
US6598178B1 (en) Peripheral breakpoint signaler
US6463553B1 (en) Microcomputer debug architecture and method
JPH05233352A (ja) マイクロプロセッサ
US5438673A (en) Automatic interface for CPU real machine and logic simulator diagnostics
US5325365A (en) In a memory emulation test apparatus, a method of and system for fast functional testing of memories in microprocessor-based units
US4791356A (en) In-circuit testing system
US20130097462A1 (en) Embedded logic analyzer
JPH09282195A (ja) 集積回路テスト装置および方法
US5758059A (en) In-circuit emulator in which abrupt and deferred arming and disarming of several events on a microprocessor chip are controlled using a single-input pin
CN112527571B (zh) 一种cpu指令集覆盖率计算方法及装置
US6973405B1 (en) Programmable interactive verification agent
JPS61213933A (ja) 論理評価回路
EP0230219B1 (en) Apparatus for testing a data processing system
US20050192791A1 (en) Method for emulating an integrated circuit and semiconductor chip for practicing the method
CN119088688A (zh) 仿真测试方法、装置、设备、存储介质及程序产品
JP2575025B2 (ja) インサ−キット・エミュレ−タ
SU1100627A1 (ru) Устройство дл отладки программ
JPS6168647A (ja) データ処理装置
JPH03177937A (ja) マイクロプロセッサのフオルト・テスト装置
JPS6326741A (ja) デ−タ処理装置の試験装置
JPS59202546A (ja) デバツグ装置
JPS63300330A (ja) ファ−ムウェアのデバッグ方法
Bose et al. Modeling IP responses in test case generation for systems-on-chip verification