JPS6121317Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an intermittent wiper drive control device, which uses a signal obtained by frequency-dividing a relatively high-frequency signal extracted from the clock circuit of an electronic automobile clock using a frequency dividing circuit. To provide a device capable of highly accurate intermittent drive control, and capable of starting a wiper immediately by canceling the reset state of the frequency dividing circuit immediately after operating a switch, and capable of intermittent drive control of the wiper. With the goal.

2. Description of the Related Art Conventionally, there has been a device that controls the operation of wipers intermittently in order to wipe off raindrops from a windshield of an automobile, mainly when there is only a small amount of rain falling. However, since this conventional wiper intermittent drive control device was integrated as a wiper relay, the connection was complicated and disadvantageous in terms of cost and space. Moreover, the accuracy of the intermittent time was relatively low.

The present invention eliminates the above-mentioned drawbacks, and an embodiment thereof will be described below with reference to the drawings of FIG. 1 and FIGS. 2A to 2H.

In one embodiment of the device of the present invention shown in FIG.
Reference numeral 1 denotes a clock circuit, which is composed of a crystal oscillation circuit, a frequency dividing circuit, etc., and outputs an extremely stable pulse signal (hereinafter referred to as a clock signal) for displaying the time in an electronic automobile clock. The device of the present invention uses a clock signal with a relatively higher frequency than the clock circuit 1 (in this embodiment, 50
Hz) and supplies this clock signal to a frequency dividing circuit 2 such as a counter. This frequency dividing circuit 2 converts the 50Hz clock signal into 1/2 ⁶ , 1/2 ⁷ , and 1/2 as described later.
The output of the inverter ³ is used to enter a reset state in which the frequency dividing operation is stopped or a reset release state. On the other hand, SW is a switch for changing wiper speed; OFF, INT, LOW,
It is configured to be connected to one of the four HIGH contacts, but as a wiper intermittent drive control device, at least two contacts, OFF and INT, are sufficient. The contact OFF is an empty contact, and the contact INT is connected to the reset terminal of the frequency divider circuit 2 via the inverter 3, while it is directly connected to one input terminal of the two-input NOR gate 4.
The other input terminal of this NOR gate 4 is the contact above.
It is connected to LOW and grounded via resistor _R3 . The output terminal of the NOR gate 4 is connected to one input terminal of a two-input NAND gate 7 via an inverter 5.

On the other hand, the frequency divider circuit 2 has three output terminals.
The above NAND gate 7 via the input NOR gate 6
is connected to the other input terminal of This NAND
The output terminal of gate 7 is connected to the base of PNP transistor T _r via resistor R ₁ . A parallel circuit consisting of a protective diode _D1 and a relay coil 8-1 is connected between the collector of the transistor T _r and ground. Further, a normally open relay switch 8-2, which is closed only when the relay coil 8-1 is energized, and a wiper drive motor 9 are connected in series between the DC voltage source and the ground. The wiper drive motor 9 has a low speed input terminal connected to the relay switch 8-2 and a high speed terminal connected to the relay switch 10-2. It rotates at low speed when current (or voltage) is supplied, and rotates at high speed when current (or voltage) is supplied to the high-speed input terminal.

Next, the operation of the wiper drive control device having the above configuration will be explained. First, when the switch SW is connected to its contact OFF, the frequency dividing circuit 2 is in the reset state, the output h of the NAND gate 7 is at the H level, the transistor T _r is OFF, and the motor 9 is stopped. There is. From this state, when the switch SW is connected to its contact INT at time _t1 , the output a of the inverter 3 changes from the H level to the L level as shown in Figure 2A, and the reset state of the frequency divider circuit 2 is released. . As a result, the frequency divider circuit 2 immediately starts dividing the frequency and outputs the 50Hz clock signal.
Pulse b as shown in Figure 2B obtained by dividing the frequency by 1/2 ⁶
A pulse c as shown in C in the same figure obtained by dividing the frequency by 1/2 ⁷ , and a pulse d as shown in D in the same figure obtained by dividing the frequency in 1/2 ⁸ are applied to the NOR gate 6, respectively. do. this
Since the NOR gate 6 outputs a high-level pulse only when input pulses b, c, and d are all low-level, the width of the high-level pulse is the same as that of the NOR gate 6, as shown in FIG. 2E. A pulse e of approximately 0.64 seconds equal to that of b and a period of 5.12 seconds equal to that of pulse d is taken out,
It is applied to one input terminal of the NAND gate 7.
Here, as is clear from Fig. 2 B to E, pulses b, c, and d are all at L level for about 0.64 seconds from time t ₁ when switch SW is connected to contact INT, so from immediately after time t ₁ The output e of the NOR gate 6 remains at the H level for about 0.64 seconds.

On the other hand, the positive DC power supply voltage is applied to the NOR gate 4 whose one end is grounded via the switch SW, where the polarity is inverted and the pulse f of the L level as shown in FIG. A pulse g whose polarity is inverted and set to H level as shown in FIG. 3G is applied to the other input terminal of the NAND gate 7. Therefore, as shown in FIG. 2H, this NAND gate 7 takes out a pulse h, which is the output pulse e of the NOR gate 6 with its polarity inverted, and this pulse h is applied to the base of the transistor T _r through the resistor R ₁ . It is turned on during the L level period and turned off during the H level period. Therefore, current flows through the relay coil 8-1 only during the ON period of this transistor T _r , that is, only during the L level period of the pulse h, and the current flows through the relay coil 8-1.
1, the normally open relay switch 8-2 is closed and the motor 9 rotates at a low speed. Further, during the H level period of the pulse h, the relay switch 8-2 is returned to the open state by turning off the transistor T _r , and therefore the motor 9 stops its rotation.

Therefore, the wiper performs an intermittent operation that alternately repeats an operation of being driven for 0.64 seconds, which is the L level period of the pulse h, and an operation of stopping driving for 4.48 seconds, which is the H level period of the pulse h. In this way, the wiper is controlled to be driven intermittently at extremely accurate time intervals by the frequency-divided clock signal from the clock circuit 1. At this time, pulse h
is the contact point INT of the switch SW as shown in Figure 2H.
Since it is always at the L level for 0.64 seconds from the connection time _t1 , the motor 9 is started immediately from the time _t1 , and the intermittent operation of the wiper is started.

Next, when the switch SW is connected to the contact OFF again at time t ₂ , the two input terminals of the NOR gate 4 are grounded through the resistors R ₂ and R ₃ , respectively, so the output g of the inverter 5 is It becomes L level as shown in G, and regardless of the level of input pulse e of NAND gate 7, its output h becomes H as shown in H in the figure.
level. At the same time, inverter 3
Since the input terminal of is grounded through resistor R ₂ ,
As shown in FIG. 2A, the output a changes from the L level to the H level at time _t2 , setting the frequency dividing circuit 2 in the reset state and stopping the frequency dividing state. As a result, the transistor T _r is always turned off, the rotation of the motor 9 continues to stop, and the wiper is not driven.

The above is the main operation of one embodiment of the wiper intermittent drive control device according to the present invention, but in this embodiment, the wiper can also be driven continuously at low speed and high speed, and the operation will be explained. In other words, if you switch the switch SW from contact OFF to LOW, the input terminal of inverter 3 will become a resistor.
Since it remains grounded via _R2 , its output remains at the H level and does not change. Therefore, the frequency divider circuit 2 remains in the reset state, and the output of the NOR gate 6 remains at the H level. Further, since a positive DC power supply voltage is applied to one input terminal of the NOR gate 4 via the switch SW, the output of the inverter 5 changes from L level to H level.
Therefore, since H level signals are applied to both input terminals of the NAND gate 7, the output of the NAND gate 7 becomes an L level, and the transistor T _r
Turn on. When the terminal of this switch SW is connected to LOW, frequency divider circuit 2 does not operate, so the above NAND
The output of the gate 7 never becomes H level, so the transistor T _r is always turned on and the motor 9 continues to rotate at a predetermined low speed. Therefore, the wiper is driven continuously at low speed without interruption.

When the switch SW is connected to its contact HIGH, the relay coil 10-1 connected in parallel to the protective diode _D2 is energized, and the normally open relay switch 10-2 is closed. 9 rotates continuously at a predetermined high speed. Therefore, the wiper is driven continuously at high speed without interruption.

It goes without saying that the frequency division ratio of the frequency dividing circuit 2 is not limited to the above embodiment. Also the second
The circuit for obtaining the pulse e shown in FIG. E is not limited to the above embodiment.

As mentioned above, the wiper intermittent drive control device of the present invention resets and divides the relatively high frequency signal extracted from the clock circuit of the electronic clock installed in the car immediately after the switch is operated. A frequency circuit, a circuit that forms pulses with a predetermined pulse width from the frequency-divided signal taken out from the frequency divider circuit, a motor for driving the wiper, and the output pulses of the pulse forming circuit are supplied via a switch. It is composed of a logic circuit that passes or cuts off depending on the signal, and a circuit that drives the motor intermittently from immediately after the switch is operated using the pulses passed through the logic circuit, so it is extremely stable against temperature changes, etc., and has accurate timing. The wiper can be driven intermittently at intervals, and the wiper can be driven intermittently immediately after the above switch is operated.Since the conventional clock circuit is shared, it does not take up much space and the circuit configuration is simple. It has the advantage of being relatively simple and can be constructed at low cost.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the device of the present invention;
2A to 2E are signal waveform diagrams for explaining the operation of FIG. 1, respectively. 1... Clock circuit, 2... Frequency dividing circuit, 8-1,1
0-1... Relay coil, 8-2, 10-2...
Relay switch, 9...wiper drive motor,
SW...Wiper speed change switch.

Claims (1)

[Scope of utility model registration request] A frequency divider circuit that resets and divides a relatively high-frequency signal extracted from the clock circuit of an electronic clock installed in a car immediately after operating a switch, and a frequency-divided signal extracted from the frequency divider circuit. a circuit for forming a pulse of a predetermined pulse width from a motor, a motor for driving the wiper, a logic circuit for passing or cutting off the output pulse of the pulse forming circuit in accordance with a signal supplied via the switch, and the logic A wiper intermittent drive control device comprising a circuit for intermittently driving the motor immediately after the switch is operated by pulses passed through the circuit.