JPS6144915Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an intermittent wiper operating device for an automobile in which the intermittent operating time of the wiper can be freely varied by operating a watch switch.

2. Description of the Related Art Conventionally, some automobiles are equipped with a device for intermittently operating wipers. There is also a wiper in which the intermittent operating time of the wiper can be varied depending on the amount of rain. Generally, the intermittent operating time of the wiper is varied by rotating a variable resistor, but in order to obtain the desired intermittent operating time, it is necessary to rotate the variable resistor several times. It was bothersome. Furthermore, even if the variable resistor is rotated and set to a desired position, there is a risk that the set position may change due to vibrations of the automobile. Furthermore, since the variable resistor is required, installation space is increased and costs are increased.

This invention was devised in view of the above-mentioned problems, and the time from when the intermittent start switch is operated until when the watch switch is operated is digitally memorized, and this is used as the intermittent operation time when the wiper is activated. It was made to work.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of an intermittent wiper operating device for an automobile according to the present invention will be described in detail with reference to the drawings.

Reference numeral 1 denotes a reference frequency generator, which includes an oscillating section 1a, a first frequency dividing section 1b that divides the signal derived from the oscillating section 1a into a desired frequency, and a signal derived from the first frequency dividing section 1b that further divides the signal derived from the first frequency dividing section 1b. The second frequency dividing section 1c divides the frequency into a desired frequency. Reference numeral 2 denotes a third frequency dividing section, which includes J.K.
It is composed of d.2e. 3 is memory, D
Flip, flop 3a, 3b, 3c, 3d, 3
e and an inverter 3f. 4 is a coincidence detection circuit, which derives an output when the signal derived from the third frequency divider 2 and the signal derived from the memory match, which includes EX ORs 4a to 4e, NAND gates 4f and 4g, and an inverter 4h. It consists of

The output parts Q ₁ to Q ₅ of the JK flips and flops 2a to 2e that constitute the third frequency dividing section 2 are the output parts of the EX OR 4.
One of the inputs of a to 4e is connected to the D flip and the input D of the flops 3a to 3f, respectively, and the other input of EX OR 4a to 4e is connected to the D flip and the output part _Q6 of the flops 3a to 3e. ~ Connected to _Q10 . The outputs of the EX-ORs 4a to 4e and the output of the inverter 3f are connected to the input of a NAND gate 4f, and the output of the NAND gate 4f is connected to one input of the NAND gate 4g. The output part of the NAND gate 4g is connected to the reset terminals of the JK flips and flops 2a to 2e, and the other input part of the NAND gate 4g is connected to the output part of the inverter 4h. The input section of the inverter 4h is grounded via an intermittent start switch 5, and also connected to a resistor 6 and an ignition switch 7.
and is grounded via a DC power supply 8.

9 is the fourth dividing section, which is connected in cascade.
Consists of JK flip, flop 9a to 9e,
The input section of the JK flip and flop 9a is the first
It is connected to the output part of the frequency divider 1b, and the reset terminals of the JK flip-flops 9a to 9e are connected to the output part ₅ of the JK flip-flop 2a. The fourth frequency divider 9 counts the signal derived from the first frequency divider 1b at the time of setting, and derives a time signal necessary to start the wiper motor.

The reference frequency generator 1, the third frequency divider 2, the memory 3, the coincidence detection circuit 4, and the fourth frequency divider 9 constitute a program timer 10. 11 is a delay circuit, which includes a first delay circuit 12, a second delay circuit 13, and
It consists of an RS flip and a flop 14, and the first delay circuit 12 includes inverters 12a, 12b,
It consists of a JK flip, flops 12c and 12d, and a NAND gate 12e. First delay circuit 1
In 2, inverters 12a and 12b are connected in cascade, and the output section of inverter 12b is
Connected to the reset terminals of the JK flip and flops 12c and 12d. JK flip flop 1
2c and 12d are connected in cascade, and the input section of JK flip and flop 12c is connected to the second frequency dividing section 1.
Connect to the output part of c, JK flip, flop 1
The output parts Q ₂₀ and Q ₂₁ of 2c and 12d are connected to the input part of the NAND gate 12e. The second delay circuit 13 includes JK flips, flops 13a, 13b,
13c, 13d and NAND gates 13e, 13f
Consists of JK flip, flop 13a, 1
3d is connected in cascade. JK flip,
The reset terminals of the flops 13a to 13d are connected to the output part of the inverter 12a, and the output part ₂₂ of the JK flip, flops 13a to 13d,
Q ₂₃ , ₂₄ and Q ₂₅ are connected to the input part of the NAND gate 13f. The output part of the NAND gate 13e is
It is connected to the input section of JK flip and flop 13a.

RS flip, flop 14 is NAND gate 1
4a, 14b, resistor 14c and capacitor 14d
It consists of In the RS flip-flop 14, the NAND gate 14a connects the first input to the output of the NAND gate 12e and the second
The input part is connected to the output part of the NAND gate 14b, and the output part is connected to the first input part of the NAND gate 14b and the first input part of the NAND gate 13e. The second input part of the NAND gate 14b is grounded via a capacitor 14d and connected to a resistor 14c.
and DC power supply 8 via ignition switch 7
is connected to. The third input of the NAND gate 14b is connected to the output of the NAND gate 13f. A second input section of the NAND gate 13e is connected to an output section of the second frequency dividing section 1c.

Reference numeral 15 denotes a time discrimination circuit, which is composed of cascade-connected JK flip-flops 15a to 15d, a buffer amplifier 15e, and an inverter 15f. The input section of the JK flip-flop 15a is connected to the output section of the first frequency dividing section 1b, and the output section ₁₉ of the JK flip-flop 15b is connected to the reset terminals of the D flip-flops 3a to 3e and the input section of the inverter 3f. The reset terminals of the JK flip-flops 15a to 15c are connected to the output of a buffer amplifier 15e and the input of an inverter 15f, and the output of the inverter 15f is connected to the input CP of the JK flip-flop 15d. Furthermore, JK flip-flop 15d
The reset terminal of the buffer amplifier 15e is connected to the second input of the NAND gate 15b, and the input of the buffer amplifier 15e is connected to the capacitor 16 along with the input of the inverter 12a and the third input of the NAND gate 13e.
and is connected to one side of the resistor 17.

18 is a washer motor, one end of which is connected to a DC power supply 8 via an ignition switch 7;
The other end is connected to the other resistor 17 and grounded via the watch switch 19.

20 is a drive circuit, which includes a NAND gate 20a,
It is composed of an inverter 20b and a relay 21.
The relay 21 is composed of a relay coil 21a and a relay switch 21b. One input part of the NAND gate 20a is connected to the output part ₁₄ of the JK flip-flop 9d, and the other input part is connected to the output part of the NAND gate 14b. It is connected to the DC power supply 8 via. 22 is a wiper device, and wiper motor 2
2a and its automatic stop switch 22b. The wiper motor 22a is connected to the relay switch 21
b, is connected to a DC power source 8 via an automatic stop switch 22b, an ignition switch 7, etc.

Next, the operation will be explained.

The reference frequency generator 1 is always operating, and the first frequency dividing section 1b and the second frequency dividing section 1c derive a signal of a desired frequency.

Now, when the intermittent start switch 5 is in the OFF state, the output section of the inverter 4h is at L level,
The output part of the NAND gate 4g becomes H level, and the third frequency dividing part 2 is in a reset state, and the fourth frequency dividing part 9 is reset by the H level signal derived from the output part.
is also in the reset state. Also, at this time, an H level signal is derived from the fourth frequency dividing section 9.

Also, when the watch switch 19 is OFF, the output side of the inverter 12b and the buffer amplifier 1
The output side of 5e becomes H level, and the JK flip-flops 15a, 15b, 15c, 12c, 12d
is in the reset state, and JK flip-flop 1
The NAND gate 12e outputs an L level signal to one input portion of the NAND gate 14a by the H level signals derived from the output portions Q ₂₀ and Q ₂₁ of the NAND gates 2c and 12d.

By the way, when the ignition switch 7 is off, the capacitor 14d is in an uncharged state, and if the ignition switch 7 is turned on in this state, the second input part of the NAND gate 14b will maintain the L level until a predetermined charging time has elapsed. . Thus, the NAND gate 14b derives an H level signal to the other input part of the NAND gate 14a, and the NAND gate 14
The output section of a holds the L level. In this way, the intermittent start switch 5 and the watch switch 19
When OFF, the NAND gate 20 of the drive circuit 20
Since an H level signal is applied to one and the other input part of a, the NAND gate 20a derives an L level signal, and the output part of the inverter 20h outputs an H level signal.
level. Therefore, the relay coil 21a is not energized and the relay switch 21b is not operated, so the wiper motor 22a is inactive.

At this time, the JK flip-flop 15d of the time discrimination circuit 15 turns on the ignition switch 7.
When this happens, the output section ₁₉ of the JK flip-flop 15d is at the H level because it is always reset due to the delay effect of the resistor 14c and capacitor 14d. Therefore, the memory 3 is in a reset state, and the EX ORs 4a to 4e derive H level signals. However, since the inverter 3f derives an L level signal, the NAND gate 4f derives an H level signal.

Now, when the intermittent start switch 5 is turned on from this state, the inverter 4h starts to output an H level signal. Further, since the signal derived from the NAND gate 4f is at H level, the NAND gate 4g derives a signal at L level, and the third frequency dividing section 2
JK flip-flops 2a to 2c are set. At this time, the output sections ₁ to ₅ of the JK flip-flops 2a to 2e immediately go to L level, and the fourth frequency dividing section 9 is set. Then, JK flip-flops 9a to 9d start counting and JK
The output part of the output part ₁₄ of the flip-flop 9d is L.
Therefore, the output section of the NAND gate 20a of the drive circuit 20 becomes the H level, and the output section of the inverter 20b becomes the L level, and the relay 21
is activated, and the wiper motor 22a is started. Then, after a predetermined time has elapsed, the JK flip-flop 9
When the output section ₁₅ of the JK flip-flop 9d changes from the H level to the L level, the JK flip-flop 9d stops counting, and its output section ₁₄ goes to the H level, causing the drive circuit 20 to stop the operation of the wiper motor 22a. The fourth frequency dividing section 9 derives an output for, for example, 0.5 seconds necessary to start the wiper motor 22a. Further, the third frequency divider 2 counts the signals derived from the second frequency divider 1c, and derives a signal for resetting the fourth frequency divider 9 after, for example, 7 seconds. And part 7
After a second, the third frequency divider 2 outputs a set signal to the fourth frequency divider 9. In other words, the fourth frequency dividing section 9
An L level signal is derived to the drive circuit 20 for 0.5 seconds. Therefore, the wiper 22 is driven intermittently at 15 second intervals.

Now, when the amount of rainfall is gradually increasing and the driver wants to shorten the intermittent operation time of the wiper 22,
Determine the visibility through the windshield a desired time after the watch switch is activated, and then turn the watch switch 1 on.
Just turn on 9 for a very short time. The operation will be explained below.

When the intermittent start switch 5 is in the ON state, the JK flip-flops 2a to 2e of the third frequency dividing section 2 are counting the signals derived from the second frequency dividing section 1c, and the signals derived from the output sections _Q1 to _Q5 are counted. The signal is D
It is constantly applied to the input portions D of the flip-flops 3a to 3f. Now, if the watch switch 19 is turned ON from this state, the time discrimination circuit 15 is set, and the JK flip-flops 15a to 15c are set.
starts counting the signals derived from the first frequency dividing section 1b. When the watch switch 19 is turned on, the JK flip-flop 1 of the time discrimination circuit 15
5d derives an L level signal from the output section ₁₉ based on the signal derived from the inverter 15f. Therefore, D flip-flops 3a to 3e of memory 3
stores the signal applied to its input D.
Now, if the ON time of the watch switch 19 is relatively short, for example, 0.3 seconds or less, the JK flip-flops 15a to 15c of the time discrimination circuit 15 will not finish counting by the predetermined time, and the The memory is retained by the signal sent. When the washer switch 19 is turned on, the washer motor 18 operates, but when the energization time is short, substantially no washer fluid is injected. Therefore, if the signals derived from the outputs Q ₁ to Q ₅ of the JK flip-flops 2a to 2e and the signals derived from the outputs Q ₆ to Q ₁₀ of the D flip-flops 3a to 3e match, EX OR 4a to 4e An H level signal is derived from NAND gate 4.
An L level signal is derived from f.

Then, the NAND gate 4g outputs an H level signal, and the JK flip-flops 2a to 2e are immediately reset. At this moment, the signals derived from the JK flip-flops 2a to 2e and the signals derived from the D flip-flops 3a to 3e no longer match, so the EX ORs 4a to 4
Since e starts to derive an L level signal, an H level signal is also derived from the NAND gate 4f, and an H level signal is derived from the inverter 4h, so the NAND gate 4g outputs an L level signal. Begins to derive.

Therefore, the coincidence detection circuit 4 derives the reset signal only for a moment, and the third frequency divider 2 is immediately set. From this point on, an L level signal is derived from the output section ₅ of the JK flip-flop 2e, the fourth frequency dividing section 9 is set and starts operating, and the above operation is repeated.

In this way, in this invention, the intermittent start switch 5 is
The wiper motor 22a starts operating, and after the desired time, the washer switch 19 is turned on for a short time.
By doing so, the program timer 10 stores the intermittent operating time, and the wiper 22 can be operated at a desired intermittent operating time.

Now, if the amount of rainfall increases further and you want to shorten the intermittent operation time of the wiper device 22, turn on the watch switch 19 again for a short time, and after the wiper device 22 starts operating again, turn on the watch again after the desired time has elapsed. Turn on the shift switch 19 for a short time
do it. This operation will be explained below.

When the watch switch 19 is turned on again, the JK flip-flop 1 is turned on via the inverter 15f.
A count signal is derived from the JK flip-flop 15d, and an H level signal is derived from the output section ₁₉ of the JK flip-flop 15d. Then, the D flip and flops 3a to 3e of the memory 3 are reset to release their memories. While this state is maintained, the wiper 22 operates once every 15 seconds as described above. Now, the wiper 22 is activated and the washer switch 19 is turned on again after a desired time.
When turned on, the JK flip-flop 15d counts the re-operation of the watch switch 19 and outputs an L level signal from its output section ₁₉ to the memory 3. Therefore, the memory 3 stores the signal derived from the third frequency dividing section 2, and sets the period of time until the stored contents and the signal derived from the third frequency dividing section 2 match as an intermittent operation time to activate the wiper 22. can operate.

As described above, in the present invention, the intermittent operation time of the wiper 22 can be freely set by operating the washer switch 19.

However, in the present invention, the wiper device 22 can also be operated continuously in conjunction with the washer switch 19.

The operation will be explained below.

Now, when the washer switch 19 is turned on for a desired time, for example 5 seconds, the washer motor 18 is activated and sprays the washer fluid onto the windshield for 5 seconds. By the way, for example, if the watch switch 19 is turned on for more than 0.3 seconds, the time determination circuit 15's JK
The flip-flop 15c outputs an output to the input section JK of the JK flip-flop 15d, and the JK flip-flop 15d derives an H level signal from its output section ₁₉ to release the memory 3.

Also, at this time, the JK flip-flops 12c and 12d of the first delay circuit 12 are connected to the inverters 12a and 12d.
2b and starts counting the signal derived from the second frequency dividing section 1c.

After a predetermined period of time, when an L level signal as a wiper motor operation start signal is derived from the NAND gate 12e, the NAND gate 14a of the RS flip-flop 14 derives an H level signal, and the NAND gate 14b derives an L level signal. Then, the drive circuit 20 starts operating the wiper motor 22a. In this way, the first delay circuit 12 operates the wiper motor 22a after a predetermined period of time, for example, 2 to 3 seconds, has elapsed since the washer switch 19 was turned on, thereby causing the washer fluid to be sufficiently sprayed onto the windshield. While the wiper motor 22a is not being operated, the wiper motor 22a is prevented from operating, thereby preventing the occurrence of problems that could damage the windshield surface.

Here, when the watch switch 19 is ON, the output section of the inverter 12a is at H level, so the JK flip-flops 13a to 13d of the second delay circuit 13 are reset, and any input section of the NAND gate 13f is set at an L level. level signal is applied.

Now, if you turn off the watch switch 19, the output section of the inverter 12b will go to H level, and the JK
Flip-flops 12c and 12d are reset. Therefore, the NAND gate 12e derives an H level signal, but the RS flip-flop 14 does not respond to this, and continues to operate the wiper 22 via the drive circuit 20 with the L level signal derived from the NAND gate 14b. By the way, if the watch switch 19 is turned OFF, the output section of the inverter 12a becomes L level, so the JK flip-flop 1
3a to 13d are set. Here RS
An H level signal is derived from the NAND gate 14a of the flip-flop 14, and since the watch switch 19 is in the OFF state, the first and third input portions of the NAND gate 13e are at the H level. Therefore, the JK flip-flops 13a to 13d start counting the signal derived from the second frequency dividing section 1c via the NAND gate 13e. After a predetermined time, when all the signals applied to the input section of the NAND gate 13f become H level, the NAND gate 13f derives an L level signal as a wiper motor operation stop signal, and the L level signal derived from the NAND gate 14b of the RS flip-flop 14 signal is converted to an H level signal.
The wiper motor 22a then stops operating. Such a second delay circuit 13 is connected to the watch switch 1.
wiper motor 22a for a predetermined period of time after turning 9 off.
When activated, the washer liquid sprayed onto the windshield is completely wiped away.

Next, the effects achieved by the intermittent wiper operating device for automobiles according to the present invention will be described.

(b) Since it is equipped with a program timer that starts when the intermittent start switch is turned on and sets or cancels the desired intermittent operation time in conjunction with the operation of the watch switch, By making a judgment and operating the washer switch at an appropriate time, the optimum intermittent operation time can be quickly and easily set.

(b) Since the intermittent operating time is stored digitally, the intermittent operating time will not change due to vibrations of the vehicle, etc.

(c) Equipped with a delay circuit that generates a signal to operate the wiper motor a predetermined time after the washer switch is turned on and a predetermined time after the washer switch is turned off, so that the washer fluid reaches the windshield sufficiently. While the wiper motor is not being sprayed, the wiper motor is prevented from operating to prevent damage to the windshield surface, and the wiper motor can be operated after the washer switch is turned off until the washer fluid is completely wiped off.

(d) Equipped with a time discrimination circuit that detects the ON time of the watch switch and sets or cancels the program timer operation time program, so it can be used as a variable timer to set the intermittent operation time of the wiper motor as in the past. No need for resistors.

[Brief explanation of the drawing]

The drawing is an electrical circuit diagram showing a preferred embodiment of the intermittent wiper operating device for an automobile according to the present invention. 1... Reference frequency generator, 1a... Oscillation section, 1b
...First frequency dividing section, 1c... Second frequency dividing section, 2... Third frequency dividing section, 3... Memory, 4... Coincidence detection circuit, 5... Intermittent start switch, 9... Fourth Frequency divider, 10...Program timer, 11...Delay circuit, 12...First delay circuit, 13...Second delay circuit, 14...RS flip-flop, 15...Time discrimination circuit, 18...Washer motor, 19...
...Washer switch, 20...Drive circuit, 21
... Relay, 22 ... Wiper device, 22a ... Wiper motor.

Claims (1)

[Scope of utility model registration request] A program timer that starts when the intermittent start switch is turned on and sets and cancels the desired intermittent operation time in conjunction with the watch switch operation, and a wiper motor that starts when the watch switch is turned on for a predetermined period of time. a first delay circuit for deriving a start-of-operation signal;
a second delay circuit that derives a wiper motor operation stop signal after a predetermined time from the OFF operation time, and a time for detecting the ON time of the washer switch and setting and canceling the program of the operation time limit of the program timer. An intermittent wiper operating device for an automobile, comprising a discrimination circuit and a drive circuit that operates a wiper motor based on a signal derived from a program timer and a signal derived from a delay circuit.